CN109309056A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN109309056A
CN109309056A CN201710622855.1A CN201710622855A CN109309056A CN 109309056 A CN109309056 A CN 109309056A CN 201710622855 A CN201710622855 A CN 201710622855A CN 109309056 A CN109309056 A CN 109309056A
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Prior art keywords
layer
dielectric layer
substrate
semiconductor structure
doped epitaxial
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CN201710622855.1A
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CN109309056B (zh
Inventor
李勇
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
SMIC Advanced Technology R&D Shanghai Corp
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Priority to CN201710622855.1A priority Critical patent/CN109309056B/zh
Priority to US16/046,799 priority patent/US10529626B2/en
Publication of CN109309056A publication Critical patent/CN109309056A/zh
Priority to US16/702,688 priority patent/US11088265B2/en
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Abstract

一种半导体结构及其形成方法，方法包括：形成基底，基底上形成有栅极结构、栅极结构两侧基底内形成有掺杂外延层、基底上形成有覆盖栅极结构顶部的层间介质层；在栅极结构两侧的层间介质层内形成露出掺杂外延层的接触开口；形成接触开口后，形成覆盖掺杂外延层的介质层；对介质层进行修复处理；在修复处理后，在介质层上形成金属层；在形成有金属层的接触开口内形成接触孔插塞。所述修复处理用于对介质层进行致密化处理，并修复介质层中的悬挂键，因此减少所述介质层和掺杂外延层界面处的界面缺陷陷阱，从而改善所形成接触孔插塞与掺杂外延层界面处费米能级钉扎的现象，相应能够降低肖特基势垒高度，进而减小接触电阻。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
背景技术
在集成电路制造过程中，形成半导体器件结构后，需要将各半导体器件连接在一起形成电路。随着集成电路制造技术的不断发展，人们对集成电路的集成度和性能的要求变得越来越高。为了提高集成度，降低成本，元器件的关键尺寸不断变小，集成电路内部的电路密度越来越大，这种发展使得晶圆表面无法提供足够的面积来制作常规电路所需要的互连线。
为了满足关键尺寸缩小过后的互连线所需，目前不同金属层或者金属层与半导体器件结构的导通是通过互连结构实现的。互连结构包括互连线和位于接触孔内的接触孔插塞，所述接触孔插塞用于连接半导体器件，所述互连线将不同半导体器件上的插塞连接起来，从而形成电路。
随着集成电路工艺节点不断缩小、器件尺寸的减小，接触孔插塞的接触面积越来越小，所述接触孔插塞与半导体器件之间的接触电阻(Contact Resistance)随之增大，影响了所形成半导体结构的电学性能。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，以减小接触电阻。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：形成基底，所述基底上形成有栅极结构、所述栅极结构两侧基底内形成有掺杂外延层、所述基底上形成有覆盖所述栅极结构顶部的层间介质层；在所述栅极结构两侧的层间介质层内形成露出所述掺杂外延层的接触开口；形成所述接触开口后，形成覆盖所述掺杂外延层的介质层；对所述介质层进行修复处理；在所述修复处理后，在所述介质层上形成金属层；在形成有所述金属层的接触开口内形成接触孔插塞。
可选的，所述介质层的材料为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、氧化镍和氧化铝中的一种或多种。
可选的，形成所述介质层的工艺为化学氧化工艺、热氧化工艺、化学气相沉积工艺或原子层沉积工艺。
可选的，所述介质层的厚度为至
可选的，所述修复处理为退火处理和UV照射处理中的一种或两种。
可选的，所述退火处理的工艺为激光退火工艺或尖峰退火工艺。
可选的，所述退火处理的工艺为激光退火工艺，所述激光退火工艺的参数包括：退火温度为900摄氏度至1250摄氏度，退火时间为100微秒至3毫秒，工艺压强为一个大气压。
可选的，所述UV照射处理的参数包括：采用波长为100纳米至300纳米的紫外线。
可选的，所述金属层的材料为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
可选的，所述金属层的厚度为至
可选的，所述接触开口露出所述掺杂外延的顶部和侧壁。
可选的，形成基底的步骤中，所述基底包括衬底、以及位于所述衬底上分立的鳍部。
相应的，本发明还提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；掺杂外延层，位于所述栅极结构两侧的基底内；介质层，覆盖所述掺杂外延层，所述介质层在形成后经历了修复处理；金属层，位于所述介质层上；层间介质层，位于所述基底上且覆盖所述栅极结构顶部；接触孔插塞，位于所述金属层上且贯穿所述层间介质层。
可选的，所述介质层的材料为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、氧化镍和氧化铝中的一种或多种。
可选的，所述介质层的厚度为至
可选的，所述修复处理为退火处理和UV照射处理中的一种或两种。
可选的，所述金属层的材料为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
可选的，所述金属层的厚度为至
可选的，所述介质层覆盖所述掺杂外延层的顶部和侧壁。
可选的，所述基底包括衬底、以及位于所述衬底上分立的鳍部。
与现有技术相比，本发明的技术方案具有以下优点：
形成覆盖所述掺杂外延层的介质层后对介质层进行修复处理，所述修复处理用于修复所述介质层中的悬挂键(Dangling Bond)、对所述介质层起到致密化作用，因此能够减少所述介质层和掺杂外延层界面处的界面缺陷陷阱(Interface Defect Trap)，从而改善所形成接触孔插塞与掺杂外延层界面处费米能级钉扎(Fermi level pinning，FLP)的现象，相应能够降低肖特基势垒高度(Schottky Barrier Height，SBH)，进而减小接触电阻，有利于提高所形成半导体结构的性能。
可选方案中，所述接触开口露出所述掺杂外延层的顶部和侧壁，因此所述介质层覆盖所述掺杂外延层的顶部和侧壁，所述金属层相应包覆所述掺杂外延层，从而增加了所述金属层与所述掺杂外延层的接触面积，进而有利于进一步减小接触电阻。
附图说明
图1至图7是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
具体实施方式
由背景技术可知，具有接触孔插塞的半导体结构存在接触电阻过大的问题。为了减小接触电阻，通常采用的方法是引入金属硅化物层(Silicide)，使接触孔插塞和掺杂外延层之间形成低欧姆接触。
但是，金属硅化物层是由金属层和掺杂外延层相互反应所形成的，随着集成电路工艺节点不断缩小、器件尺寸的减小，形成掺杂外延层的空间越来越小、掺杂外延层的体积越来越小，形成金属硅化物层的工艺相应也越来越难，且容易导致所形成金属硅化物层的质量下降，从而导致所述接触孔插塞与掺杂外延层之间依旧具有较大的接触电阻。传统的金属硅化物层技术已经达到了降低接触电阻的极限。
所以，为了突破金属硅化物层技术对减小接触电阻的限制，金属-绝缘体-半导体(Metal-Insulator-Semiconductor，MIS)结构应运而生。其中，掺杂外延层、形成于所述掺杂外延层上的介质层、以及形成于所述介质层上的金属层构成MIS结构，从而可以改变接触孔插塞与掺杂外延层界面处费米能级的位置，降低肖特基势垒高度，进而达到减小接触电阻的目的。
但是，在所述掺杂外延层上形成介质层后，所述介质层的质量不佳，因此所述介质层和掺杂外延层界面处的界面缺陷陷阱较多，从而导致改善费米能级钉扎现象问题的效果仍旧不佳，相应的，难以降低肖特基势垒高度，进而导致减小接触电阻的效果不佳。
为了解决所述技术问题，本发明在形成介质层后对介质层进行修复处理，所述修复处理用于修复所述介质层中的悬挂键、对所述介质层起到致密化作用，因此能够减少所述介质层和掺杂外延层界面处的界面态缺陷，从而减小接触电阻，有利于提高所形成半导体结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图7是本发明半导体结构的形成方法一实施例中各步骤对应结构示意图。
参考图1，图1是沿垂直于鳍部延伸方向且在掺杂外延层位置处的剖面结构示意图，形成基底(未标示)，所述基底上形成有栅极结构(图未示)、所述栅极结构两侧基底内形成有掺杂外延层120、所述基底上形成有覆盖所述栅极结构顶部的层间介质层102。
本实施例中，所形成半导体结构具有鳍式结构，即所形成的器件为鳍式场效应晶体管，因此所述基底包括衬底100、以及位于所述衬底100上分立的鳍部110。在其他实施例中，所形成半导体结构也可以为平面结构，相应的，所述基底为平面衬底。
所述衬底100为后续形成半导体结构提供工艺操作平台，所述鳍部110用于提供所形成鳍式场效应晶体管的沟道。
本实施例中，所述衬底100为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述衬底的材料可以是适宜于工艺需要或易于集成的材料。
所述鳍部110的材料与所述衬底100的材料相同。本实施例中，所述鳍部110的材料为硅。在其他实施例中，所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟。
本实施例中，后续所形成半导体结构为CMOS，所以所述衬底100包括用于形成PMOS的PMOS区I以及用于形成NMOS的NMOS区II。在其他实施例中，所形成半导体结构也可以仅为PMOS或仅为NMOS，所述基底相应仅具有PMOS区或仅具有NMOS区。
本实施例中，所述PMOS区I与所述NMOS区II相邻设置。在其他实施例中，所述PMOS区与所述NMOS区也可以间隔设置。
具体地，形成所述衬底100和鳍部110的步骤包括：提供初始基底；在所述初始基底表面形成图形化的鳍部掩膜层(图未示)；以所述鳍部掩膜层为掩膜刻蚀所述初始基底，刻蚀后的剩余所述初始基底作为衬底100，位于所述衬底100上的凸起作为鳍部。
本实施例中，形成所述衬底100和鳍部110后，保留位于所述鳍部110顶部的鳍部掩膜层。所述鳍部掩膜层的材料为氮化硅，后续在进行平坦化处理工艺时，所述鳍部掩膜层顶部表面用于定义平坦化处理工艺的停止位置，并起到保护所述鳍部110顶部的作用。
需要说明的是，形成所述衬底100和鳍部110后，还包括步骤：在所述衬底100上形成隔离结构101，所述隔离结构101覆盖所述鳍部110的部分侧壁，且所述隔离结构101顶部低于所述鳍部110顶部。
所述隔离结构101作为半导体器件的隔离结构，用于对相邻器件和鳍部110起到隔离作用。本实施例中，所述隔离结构101的材料为氧化硅。在其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅等其他绝缘材料。
具体地，形成所述隔离结构101的步骤包括：在所述衬底100上形成隔离膜，所述隔离膜顶部高于所述鳍部掩膜层(图未示)顶部；研磨去除高于所述鳍部掩膜层顶部的隔离膜；通过回刻的方式去除部分厚度的剩余隔离膜，形成隔离结构101；去除所述鳍部掩膜层。
所述栅极结构用于控制所形成半导体结构沟道的导通和截断。所述掺杂外延层120用于作为所形成半导体结构沟道的源区(Source)或漏区(Drain)。
本实施例中，所述栅极结构为金属栅极结构，所述栅极结构包括栅介质层和金属栅极。在其他实施例中，所述栅极结构也可以为多晶硅栅极结构等其他结构。
本实施例中，所述掺杂外延层120形成于所述栅极结构两侧的鳍部110内。所述衬底100包括PMOS区I和NMOS区II，相应的，所述PMOS区I栅极结构两侧的鳍部110内形成有P型掺杂的掺杂外延层120，所述NMOS区II栅极结构两侧的鳍部110内形成有N型掺杂的掺杂外延层120。
需要说明的是，本实施例中，采用后形成高k栅介质层后形成栅电极层(high klast metal gate last)的工艺形成所述栅极结构，因此形成所述栅极结构和掺杂外延层120的步骤包括：形成所述基底后，形成横跨所述鳍部110且覆盖所述鳍部110部分顶部和部分侧壁的伪栅结构(图未示)；在所述PMOS区I伪栅结构两侧的鳍部110内形成P型掺杂的掺杂外延层120，在所述NMOS区II伪栅结构两侧的鳍部110内形成N型掺杂的掺杂外延层120；形成所述掺杂外延层120后，在所述衬底100上形成层间介质层102，所述层间介质层102露出所述伪栅结构顶部；去除所述伪栅结构，在所述层间介质层102内形成栅极开口(图未示)；在所述栅极开口中形成金属栅极结构。
所述伪栅结构用于为栅极结构的形成占据空间位置。
本实施例中，所述伪栅结构为叠层结构，包括伪氧化层(图未示)和位于所述伪氧化层上的伪栅极(图未示)。在其他实施例中，所述伪栅结构还可以为单层结构，相应的，所述伪栅结构仅包括伪栅层。
本实施例中，所述伪氧化层的材料为氧化硅。在其他实施例中，所述伪氧化层的材料还可以为氮氧化硅。
本实施例中，所述伪栅层的材料为多晶硅。在其他实施例中，所述伪栅层的材料还可以为氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳等其他材料。
具体的，形成所述伪栅结构的步骤包括：在所述隔离结构101露出的所述鳍部110表面形成氧化材料层；在所述氧化材料层上形成伪栅材料层；在所述伪栅材料层表面形成栅极掩膜层(图未示)；以所述栅极掩膜层为掩膜，刻蚀所述伪栅材料层，露出所述氧化材料层，形成位于所述氧化材料层上的伪栅层，所述伪栅层横跨所述鳍部110且位于所述鳍部110部分顶部和部分侧壁上；去除所述伪栅层露出的氧化材料层，露出所述鳍部110的表面，被所述伪栅层覆盖的剩余氧化材料层作为伪氧化层，所述伪氧化层横跨所述鳍部110且覆盖所述鳍部110部分顶部和部分侧壁的表面。
需要说明的是，形成所述伪栅结构后，保留位于所述伪栅结构顶部上的栅极掩膜层。所述栅极掩膜层的材料为氮化硅，所述栅极掩膜层在后续工艺过程中用于对所述伪栅结构顶部起到保护作用。在其他实施例中，所述栅极掩膜层的材料还可以为氮氧化硅、碳化硅或氮化硼。
所述PMOS区I的掺杂外延层120用于作为后续所形成PMOS的源区或漏区。
具体地，形成所述PMOS区I的P型掺杂外延层120的步骤包括：采用选择性外延工艺(EPI)，在所述PMOS区I伪栅结构两侧的鳍部110内形成第一外延层；对所述第一外延层进行P型离子掺杂以形成所述掺杂外延层120。
本实施例中，在形成所述第一外延层的过程中，原位自掺杂P型离子以形成所述P型掺杂的掺杂外延层120。
所述第一外延层的材料可以为Si或SiGe，所述P型离子包括B、Ga和In中的一种或多种。其中所述P型离子的掺杂浓度根据实际工艺需求而定。
本实施例中，所述第一外延层的材料为SiGe，所述P型离子为B离子。相应的，所述PMOS区I的掺杂外延层120的材料为SiGeB。
所述第一外延层为PMOS的沟道区提供压应力作用，从而提高PMOS的载流子迁移率。
所述NMOS区II的掺杂外延层120用于作为后续所形成NMOS的源区或漏区。
具体地，形成所述NMOS区II的掺杂外延层120的步骤包括：采用选择性外延工艺，在所述NMOS区II伪栅结构两侧的鳍部110内形成第二外延层；对所述第二外延层进行N型离子掺杂以形成N型材料的掺杂外延层120。
本实施例中，在形成所述第二外延层的过程中，原位自掺杂N型离子以形成所述N型掺杂的掺杂外延层120。
所述第二外延层的材料可以为Si或SiC，所述N型离子包括P、As和Sb中的一种或多种。其中所述N型离子的掺杂浓度根据实际工艺需求而定。
本实施例中，所述第二外延层的材料为Si，所述N型离子为P离子。相应的，所述NMOS区II的掺杂外延层120的材料为SiP。其中，SiP材料的掺杂外延层120有利于减小NMOS区II的接触电阻。
所述层间介质层102用于实现相邻半导体结构之间的电隔离。所述层间介质层102的材料为绝缘材料。本实施例中，所述层间介质层102的材料为氧化硅。在其他实施例中，所述层间介质层的材料还可以为氮化硅或氮氧化硅等其他介质材料。
具体地，形成所述层间介质层102的步骤包括：在所述衬底100上形成层间介质膜，所述层间介质膜还覆盖所述伪栅结构顶部；研磨去除高于所述伪栅结构顶部的底部介质膜，露出所述伪栅结构顶部，剩余层间介质膜作为所述层间介质层102。
需要说明的是，所述伪栅结构顶部形成有栅极掩膜层(图未示)，因此在研磨去除高于所述伪栅结构顶部的层间介质膜的过程中，还研磨去除所述栅极掩膜层，即所述层间介质层102顶部与所述伪栅结构顶部齐平。
本实施例中，形成所述栅极结构的步骤包括：在所述栅极开口底部露出的基底上形成所述栅介质层；在所述栅介质层上形成所述金属栅极。
所述栅介质层的材料为高k介质材料。其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介质材料。本实施例中，所述栅介质层的材料为HfO2。在其他实施例中，所述栅介质层的材料还可以为ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、或Al2O3等。
本实施例中，所述栅极开口底部露出所述鳍部110部分顶部和部分侧壁的表面，因此所述栅介质层横跨所述鳍部110，且覆盖所述鳍部110部分顶部和部分侧壁表面。
本实施例中，所述金属栅极的材料为W。在其他实施例中，所述金属栅极的材料还可以为Al、Cu、Ag、Au、Pt、Ni或Ti等。
需要说明的是，本实施例以后形成高K栅介质层后形成金属栅极(high K lastmetal gate last)的工艺顺序为例进行说明。在其他实施例中，还可以采用先形成高k栅介质层先形成栅电极层(high k first metal gate first)的工艺形成所述栅极结构。相应的，在形成所述栅极结构之后，形成所述掺杂外延层和层间介质层。
参考图2，在所述栅极结构(图未示)两侧的层间介质层102内形成露出所述掺杂外延层120的接触开口130。
所述接触开口130露出所述掺杂外延层120，从而为后续形成与所述掺杂外延层120电连接的接触孔插塞(CT)提供工艺基础。
需要说明的是，本实施例中，所述PMOS区I与所述NMOS区II相邻设置，为了增大后续形成接触孔插塞的工艺窗口，降低形成工艺难度，所述接触开口130横跨所述PMOS区I和NMOS区II。
相应的，所述接触开口130同时露出所述PMOS区I的掺杂外延层120和NMOS区II的掺杂外延层120，且还露出部分所述隔离结构101和鳍部110。
本实施例中，所述接触开口130露出所述掺杂外延层120的顶部和侧壁。后续步骤还包括形成覆盖所述掺杂外延层120的介质层、在所述介质层上形成金属层，与仅露出部分掺杂外延层顶部的方案相比，本实施例能够使所形成介质层覆盖所述接触开口130所露出的掺杂外延层120表面，相应的，使所形成金属层包覆所述掺杂外延层120，从而增加后续所形成金属层与所述掺杂外延层120的接触面积，进而有利于降低接触电阻。
本实施例中，通过掩膜干法刻蚀的方式，刻蚀所述掺杂外延层120上和部分隔离结构101上的层间介质层102，以形成贯穿层间介质层102的接触开口130。
具体的，所述干法刻蚀所采用的工艺气体包括CH4和CHF3。其中，根据所述层间介质层102的刻蚀量，合理设定所述干法刻蚀的工艺参数。
参考图4，形成所述接触开口130后，形成覆盖所述掺杂外延层120的介质层140。
所述介质层140的作用包括：用于作为MIS结构的一部分，即作为MIS结构中的绝缘层，以改变后续所形成接触孔插塞与所述掺杂外延层120界面处费米能级的位置，降低肖特基势垒高度，从而减小接触电阻；用于防止后续所形成金属层与所述掺杂外延层120之间材料的扩散，防止所述金属层与所述掺杂外延层120之间发生反应，能够起到扩散阻挡层的作用；用于作为遂穿介质层，使电子能够在所述介质层140内发生隧穿效应，以避免对后续所形成接触孔插塞与所述掺杂外延层120之间的导电性能产生不良影响。
因此，本实施例中，所述介质层140的材料可以为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、氧化镍和氧化铝中的一种或多种。
通常情况下，所述介质层140的导电性能较差，因此所述介质层140的厚度不宜太大。如果所述介质层140的厚度过大，则不利于实现隧穿效应，所述介质层140的存在容易导致接触电阻增大，从而影响所形成半导体结构的性能。所以本实施例中，所述介质层140的厚度小于
但是，当所述介质层140的厚度过小时，形成所述介质层140的工艺难度相应较大，且所述介质层140的质量和厚度均一性难以保证。
为此，本实施例中，在减小所述介质层140厚度的同时，考虑到工艺可实现性，所述介质层140的厚度为至
本实施例中，所述介质层140的厚度较小，因此电子能够在所述介质层140内发生隧穿效应，从而避免对所述接触孔插塞和掺杂外延层120之间的导电性能产生不良影响，且能够有效抑制所述接触孔插塞和掺杂外延层120界面处费米能级钉扎的现象，有利于降低所述接触孔插塞和掺杂外延层120之间的接触电阻，有利于提高所形成半导体结构的性能。
形成所述介质层140的工艺可以为化学氧化工艺、热氧化工艺、化学气相沉积工艺或原子层沉积工艺。
本实施例中，所述介质层140的厚度较小，为了精确控制所形成介质层140的厚度，采用化学氧化工艺形成所述介质层140，即所述介质层140的材料为化学氧化物(ChemicalOxide)。具体地，采用化学浸润(Chemical Dip)的方式形成所述介质层140。
本实施例中，所述介质层140的材料为氧化硅，形成所述介质层140的方法包括：采用臭氧水对所述掺杂外延层120进行浸润处理，浸润处理的反应温度为室温，反应时间为1分钟至5分钟，臭氧水的浓度为10PPM至80PPM。
在另一些实施例中，形成所述介质层的方法包括：采用硫酸和双氧水的混合溶液对所述掺杂外延层进行浸润处理，浸润处理的反应温度为120摄氏度至180摄氏度，反应时间为1分钟至5分钟，硫酸和双氧水的体积比为1:1至5:1。
在其他一些实施例中，形成所述介质层的方法包括：采用氨水和双氧水的混合溶液对所述掺杂外延层进行浸润处理，浸润处理的反应温度为25摄氏度至45摄氏度，反应时间为1分钟至5分钟，氨水和双氧水的体积比为1:4至1:25。
相应的，本实施例中，形成于所述PMOS区I掺杂外延层120表面的介质层140的材料为氧化锗，形成于所述NMOS区II掺杂外延层120表面的介质层140的材料为氧化硅。
需要说明的是，化学氧化工艺仅对所述掺杂外延层120进行反应，因此所形成介质层140位于所述掺杂外延层120表面。
还需要说明的是，所述接触开口130还露出部分所述鳍部110，因此所述介质层140还形成于暴露出的鳍部110表面，且位于所述鳍部110表面的介质层140材料为氧化硅。
参考图4，对所述介质层140进行修复处理145。
在所述掺杂外延层120上形成介质层140后，所述介质层140的质量不佳，所述介质层140中容易出现悬挂键等缺陷，从而使得所述介质层140和掺杂外延层120界面处的界面缺陷陷阱较多；因此通过所述修复处理145，减少所述介质层140中的悬挂键、对所述介质层140进行致密化处理，从而减少所述界面缺陷陷阱，进而改善后续所形成接触孔插塞与所述掺杂外延层120界面处费米能级钉扎的现象，相应能够降低肖特基势垒高度，以实现减小接触电阻的工艺效果。
本实施例中，所述修复处理145为退火处理145。
所述退火处理145能够提供足够的能量使得所述介质层140中的晶粒发生重排列，促进所述介质层140再生长，并减少所述介质层140中的缺陷，提高所述介质层140的致密度。
所述退火处理145的工艺可以为激光退火工艺或尖峰退火工艺。本实施例中，所述退火处理145的工艺为激光退火工艺，所述激光退火工艺的工艺压强为一个大气压。
所述激光退火工艺的退火温度不宜过高，也不宜过低；所述激光退火工艺的退火时间不宜过长，也不宜过短。
如果退火温度过低，或者退火时间过短，则会影响减少所述介质层140和掺杂外延层120界面处的界面缺陷陷阱的效果，从而容易导致减小接触电阻的效果不明显；如果退火温度过高，或者退火时间过长，相应会增大工艺风险，例如：容易对所述基底(未标示)内已有掺杂离子的分布或已形成结构的质量造成不良影响。为此，本实施例中，所述激光退火工艺的退火时间为100微秒至3毫秒，所述激光退火工艺的退火温度为900摄氏度至1250摄氏度。
在另一实施例中，所述修复处理还可以为UV照射处理(UV Curve)。
通过UV照射处理，提供能量以钝化所述介质层中的悬挂键，从而减少所述介质层140中的悬挂键、提高所述介质层140的致密度，进而减少所述介质层140和掺杂外延层120界面处的界面缺陷陷阱。
本实施例中，所述UV照射处理采用波长为100纳米至300纳米的紫外线进行照射。
紫外线的波长越短，能量越高。波长为100纳米至300纳米的紫外线能够有效地减少所述介质层140和掺杂外延层120界面处的界面缺陷陷阱，且避免过高的紫外线能量对所述掺杂外延层120、栅极结构(图未示)、基底(未标示)等结构造成损伤。
其中，根据实际工艺情况，在保证减少所述介质层140中的悬挂键效果、以及避免对所述掺杂外延层120、栅极结构(图未示)、基底(未标示)等结构造成损伤的前提下，合理设定所述UV照射处理的参数。
在一些具体实施例中，所述紫外线的光强为100毫瓦/平方厘米至2000毫瓦/平方厘米，所述UV照射处理的处理温度为300摄氏度至500摄氏度，处理时间为2分钟至10分钟。
在其他一些实施例中，所述修复处理还可以包括先后进行的退火处理和UV照射处理，从而能够进一步有效提高减少所述介质层和掺杂外延层界面处的界面缺陷陷阱的效果。
参考图5，在所述修复处理145(如图4所示)后，在所述介质层140上形成金属层150。
所述金属层150与所述介质层140、掺杂外延层120构成MIS结构，从而改变后续所形成接触孔插塞与所述掺杂外延层120界面处费米能级的位置，降低肖特基势垒高度，进而减小接触电阻。
本实施例中，所述金属层150的材料可以为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
所述金属层150的厚度越大，所述金属层150的阻值相应越大。因此所述金属层150的厚度不宜太大。如果所述金属层150的厚度过大，则容易对所述接触孔插塞和掺杂外延层120之间的导电性能产生不良影响，从而导致接触电阻增大，进而影响所形成半导体结构的性能。所以本实施例中，所述金属层150的厚度小于
但是，当所述金属层150的厚度过小时，形成所述金属层150的工艺难度相应较大，且所述金属层150的质量和厚度均一性难以保证。
为此，本实施例中，在减小所述金属层150厚度的同时，考虑到工艺可实现性，所述金属层150的厚度为至在一些具体实施例中，所述金属层150的厚度为至
本实施例中，形成所述金属层150的工艺可以为原子层沉积工艺或物理气相沉积工艺。
结合参考图6，需要说明的是，形成所述金属层150后，还包括步骤：在所述金属层150上形成阻挡层160。
所述阻挡层160的作用包括：一方面，可以防止后续在所述接触开口130中形成接触孔插塞时所采用的反应物与所述金属层150、介质层140或掺杂外延层120发生反应；另一方面，所述阻挡层160用于在后续形成接触孔插塞时，提高导电材料在所述接触开口130内的粘附性。
本实施例中，所述阻挡层160的材料为TiN。在其他实施例中，所述阻挡层的材料还可以为TaN。
还需要说明的是，本实施例中采用MIS结构，因此在形成所述阻挡层160后，无需对所述金属层150进行退火处理，相应还可以降低热预算(Thermal Budget)。
参考图7，在形成有所述金属层150的接触开口130(如图6所示)内形成接触孔插塞170。
所述接触孔插塞170与所述掺杂外延层120实现电连接，用于实现半导体器件内的电连接，还用于实现器件与外部电路之间的电连接。
所述接触孔插塞170的材料可以是Al、Cu、Ag、Co和Au等金属材料中的一种或多种。本实施例中，所述接触孔插塞170的材料为W，可以采用溅射工艺或电镀工艺形成所述接触孔插塞170。
需要说明的是，所述接触开口130横跨所述PMOS区I和NMOS区II，相应的，所述接触孔插塞170横跨所述PMOS区I和NMOS区II，且还位于部分所述隔离结构101上。
具体地，形成所述接触孔插塞170的步骤包括：向所述接触开口130内填充满导电材料，所述导电材料还位于所述层间介质层102顶部；对所述导电材料进行平坦化处理，去除高于所述层间介质层102顶部的导电材料，在所述接触开口130内形成所述接触孔插塞170。
相应的，本发明还提供一种半导体结构。
继续参考图7，示出了本发明半导体结构一实施例的结构示意图。所述半导体结构，包括：
基底(未标示)；栅极结构(图未示)，位于所述基底上；掺杂外延层120，位于所述栅极结构两侧的基底内；介质层140，覆盖所述掺杂外延层120，所述介质层140在形成后经历了修复处理；金属层150，位于所述介质层140上；层间介质层102，位于所述基底上且覆盖所述栅极结构顶部；接触孔插塞170，位于所述金属层150上且贯穿所述层间介质层102。
本实施例中，所述半导体结构具有鳍式结构，即半导体器件为鳍式场效应晶体管，因此所述基底包括衬底100、以及位于所述衬底100上分立的鳍部110。在其他实施例中，所述半导体结构也可以为平面结构，相应的，所述基底为平面衬底。
所述衬底100为所述半导体结构的形成提供工艺操作平台，所述鳍部110用于提供所述鳍式场效应晶体管的沟道。
本实施例中，所述衬底100为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述衬底的材料可以是适宜于工艺需要或易于集成的材料。
所述鳍部110的材料与所述衬底100的材料相同。本实施例中，所述鳍部110的材料为硅。在其他实施例中，所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟。
本实施例中，所述半导体结构为CMOS器件，所以所述衬底100包括具有PMOS的PMOS区I以及具有NMOS的NMOS区II。在其他实施例中，所述半导体结构也可以仅为PMOS或仅为NMOS，所述基底相应仅具有PMOS区或仅具有NMOS区。
本实施例中，所述PMOS区I与所述NMOS区II相邻设置。在其他实施例中，所述PMOS区与所述NMOS区也可以间隔设置。
需要说明的是，所述半导体结构还包括：位于所述衬底100上的隔离结构101，所述隔离结构101覆盖所述鳍部110的部分侧壁，且所述隔离结构101顶部低于所述鳍部110顶部。
所述隔离结构101作为半导体器件的隔离结构，用于对相邻器件和鳍部110起到隔离作用。本实施例中，所述隔离结构101的材料为氧化硅。
所述栅极结构用于控制所述半导体结构沟道的导通和截断。所述掺杂外延层120用于作为所述半导体结构沟道的源区或漏区。
所述栅极结构横跨所述鳍部110，且覆盖所述鳍部110部分顶部和部分侧壁。本实施例中，所述栅极结构为金属栅极结构，因此所述栅极结构包括栅介质层(图未示)、以及位于所述栅介质层上的金属栅极(图未示)。在其他实施例中，所述栅极结构也可以为多晶硅栅极结构等其他结构。
所述栅介质层的材料为高k介质材料。其中，高k介质材料是指相对介电常数大于氧化硅相对介电常数的介质材料。本实施例中，所述栅介质层的材料为HfO2。在其他实施例中，所述栅介质层的材料还可以为ZrO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、或Al2O3等。
本实施例中，所述金属栅极的材料为W。在其他实施例中，所述金属栅极的材料还可以为Al、Cu、Ag、Au、Pt、Ni或Ti等。
本实施例中，所述掺杂外延层120位于所述栅极结构两侧的鳍部110内。所述衬底100包括PMOS区I和NMOS区II，相应的，所述PMOS区I栅极结构两侧鳍部110内的掺杂外延层120为P型掺杂材料，所述NMOS区II栅极结构两侧鳍部110内的掺杂外延层120为N型掺杂材料。
所述PMOS区I的掺杂外延层120用于作为PMOS的源区或漏区，所述NMOS区II的掺杂外延层120用于作为NMOS的源区或漏区。
所述PMOS区I的掺杂外延层120的材料为掺杂有P型离子的Si或SiGe，其中，所述P型离子包括B、Ga和In中的一种或多种。本实施例中，所述PMOS区I的掺杂外延层120的材料为掺杂有B离子的SiGe，即所述PMOS区I的掺杂外延层120的材料为SiGeB。
也就是说，所述半导体结构还包括第一外延层，所述第一外延层的材料为SiGe，所述第一外延层位于所述PMOS区I栅极结构两侧的鳍部110内，且所述B离子位于所述第一外延层内。所述第一外延层为PMOS沟道区提供压应力作用，从而提高PMOS的载流子迁移率。
所述NMOS区II的掺杂外延层120的材料为掺杂有N型离子的Si或SiC，其中，所述N型离子包括P、As和Sb中的一种或多种。本实施例中，所述NMOS区II的掺杂外延层120的材料为掺杂有P离子的Si，即所述NMOS区II的掺杂外延层120的材料为SiP。SiP材料的掺杂外延层120有利于减小NMOS区II的接触电阻。
也就是说，所述半导体结构还包括第二外延层，所述第二外延层的材料为Si，所述第二外延层位于所述NMOS区II栅极结构两侧的鳍部110内，且所述P离子位于所述第一外延层内。
所述介质层140的作用包括：用于作为MIS结构的一部分，即作为MIS结构中的绝缘层，以改变所述接触孔插塞170与所述掺杂外延层120界面处费米能级的位置，降低肖特基势垒高度，从而减小接触电阻；用于防止所述金属层150与所述掺杂外延层120之间材料的扩散，防止所述金属层150与所述掺杂外延层120之间发生反应，能够起到扩散阻挡层的作用；用于作为遂穿介质层，使电子能够在所述介质层140内发生隧穿效应，以避免对所述接触孔插塞170和掺杂外延层120之间的导电性能产生不良影响。
因此，所述介质层140的材料可以为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、氧化镍和氧化铝中的一种或多种。
本实施例中，所述介质层140通过氧化工艺所形成，因此，位于所述PMOS区I掺杂外延层120表面的介质层140的材料为氧化锗，位于所述NMOS区II掺杂外延层120表面的介质层140的材料为氧化硅。
本实施例中，所述介质层140覆盖所述掺杂外延层120的顶部和侧壁，相应的，所述金属层150包覆所述掺杂外延层120，从而增加了所述金属层150与所述掺杂外延层120的接触面积，进而有利于进一步减小接触电阻。
需要说明的是，所述介质层140还位于部分所述鳍部110表面，且位于所述鳍部110表面的介质层140材料为氧化硅。
通常情况下，所述介质层140的导电性能较差，因此所述介质层140的厚度不宜太大。如果所述介质层140的厚度过大，则不利于实现遂穿效应，所述介质层140的存在容易导致接触电阻增大，从而影响所述半导体结构的性能。所以本实施例中，所述介质层140的厚度小于
但是，当所述介质层140的厚度过小时，形成所述介质层140的工艺难度相应较大，且所述介质层140的质量和厚度均一性难以保证。
为此，本实施例中，在减小所述介质层140厚度的同时，考虑到工艺可实现性，所述介质层140的厚度为至
本实施例中，所述介质层140的厚度较小，因此电子能够在所述介质层140内发生隧穿效应，从而避免对所述接触孔插塞170和掺杂外延层120之间的导电性能产生不良影响，且能够有效抑制所述接触孔插塞170和掺杂外延层120界面处费米能级钉扎的现象，有利于降低所述接触孔插塞170和掺杂外延层120之间的接触电阻，有利于提高所形成半导体结构的性能。
所述介质层140在形成后的质量不佳，所述介质层140中容易出现悬挂键等缺陷，从而使得所述介质层140和掺杂外延层120界面处的界面缺陷陷阱较多。本实施例中，所述介质层140在形成后经历了修复处理，从而使所述介质层140中的悬挂键减少、所述介质层140致密度得到提高，进而使得所述界面缺陷陷阱减少。
所述界面缺陷陷阱的减少，相应能够改善所述接触孔插塞170与所述掺杂外延层120界面处费米能级钉扎的现象，从而降低肖特基势垒高度，进而实现减小接触电阻的工艺效果。
本实施例中，所述修复处理为退火处理和UV照射处理中的一种或两种。
所述金属层150与所述介质层140、掺杂外延层120构成MIS结构，从而改变所述接触孔插塞170与所述掺杂外延层120界面处费米能级的位置，降低肖特基势垒高度，进而减小接触电阻。
本实施例中，所述金属层150的材料可以为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
所述金属层150的厚度越大，所述金属层150的阻值相应越大。因此所述金属层150的厚度不宜太大。如果所述金属层150的厚度过大，则容易对所述接触孔插塞170和掺杂外延层120之间的导电性能产生不良影响，从而导致接触电阻增大，进而影响所述半导体结构的性能。所以本实施例中，所述金属层150的厚度小于
但是，当所述金属层150的厚度过小时，形成所述金属层150的工艺难度相应较大，且所述金属层150的质量和厚度均一性难以保证。
为此，本实施例中，在减小所述金属层150厚度的同时，考虑到工艺可实现性，所述金属层150的厚度为至在一些具体实施例中，所述金属层150的厚度为至
需要说明的是，形成所述金属层150的工艺可以为原子层沉积工艺或物理气相沉积工艺，因此所述金属层150位于所述接触孔插塞170和所述介质层140之间、所述接触孔插塞170和所述隔离结构101之间、以及所述接触孔插塞170和所述层间介质层102之间。
所述层间介质层102用于实现相邻半导体结构之间的电隔离。
所述层间介质层102的材料为绝缘材料。本实施例中，所述层间介质层102的材料为氧化硅。在其他实施例中，所述层间介质层的材料还可以为氮化硅或氮氧化硅等其他介质材料。
所述接触孔插塞170与所述掺杂外延层120实现电连接，用于实现半导体器件内的电连接，还用于实现半导体器件内的电连接，还用于实现器件与外部电路之间的电连接。
所述接触孔插塞170的材料可以是Al、Cu、Ag、Co和Au等金属材料中的一种或多种。本实施例中，所述接触孔插塞170的材料为W。
需要说明的是，本实施例中，为了增加形成所述接触孔插塞170的工艺窗口，降低形成所述接触孔插塞170的工艺难度，所述接触孔插塞170横跨所述PMOS区I和NMOS区II，且还位于部分所述隔离结构101上。
需要说明的是，所述半导体结构还包括：阻挡层160，位于所述接触孔插塞170与所述金属层150之间。
所述阻挡层160的作用包括：一方面，可以防止形成所述接触孔插塞170时所采用的反应物与所述金属层150、介质层140或掺杂外延层120发生反应；另一方面，用于提高所述接触孔插塞170在所述层间介质层102内的粘附性。
本实施例中，所述阻挡层160的材料为TiN。在其他实施例中，所述阻挡层的材料还可以为TaN。
本实施例所述半导体结构采用前述形成方法所形成，对所述半导体结构的具体描述，请参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体结构的形成方法，其特征在于，包括：
形成基底，所述基底上形成有栅极结构、所述栅极结构两侧基底内形成有掺杂外延层、所述基底上形成有覆盖所述栅极结构顶部的层间介质层；
在所述栅极结构两侧的层间介质层内形成露出所述掺杂外延层的接触开口；
形成所述接触开口后，形成覆盖所述掺杂外延层的介质层；
对所述介质层进行修复处理；
在所述修复处理后，在所述介质层上形成金属层；
在形成有所述金属层的接触开口内形成接触孔插塞。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述介质层的材料为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、
氧化镍和氧化铝中的一种或多种。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述介质层的工艺为化学氧化工艺、热氧化工艺、化学气相沉积工艺或原子层沉积工艺。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述介质层的厚度为至
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述修复处理为退火处理和UV照射处理中的一种或两种。
6.如权利要求5所述的半导体结构的形成方法，其特征在于，所述退火处理的工艺为激光退火工艺或尖峰退火工艺。
7.如权利要求5或6所述的半导体结构的形成方法，其特征在于，所述退火处理的工艺为激光退火工艺，所述激光退火工艺的参数包括：退火温度为900摄氏度至1250摄氏度，退火时间为100微秒至3毫秒，工艺压强为一个大气压。
8.如权利要求5所述的半导体结构的形成方法，其特征在于，所述UV照射处理的参数包括：采用波长为100纳米至300纳米的紫外线。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，所述金属层的材料为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，所述金属层的厚度为至
11.如权利要求1所述的半导体结构的形成方法，其特征在于，所述接触开口露出所述掺杂外延层的顶部和侧壁。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，形成基底的步骤中，所述基底包括衬底、以及位于所述衬底上分立的鳍部。
13.一种半导体结构，其特征在于，包括：
基底；
栅极结构，位于所述基底上；
掺杂外延层，位于所述栅极结构两侧的基底内；
介质层，覆盖所述掺杂外延层，所述介质层在形成后经历了修复处理；
金属层，位于所述介质层上；
层间介质层，位于所述基底上且覆盖所述栅极结构顶部；
接触孔插塞，位于所述金属层上且贯穿所述层间介质层。
14.如权利要求13所述的半导体结构，其特征在于，所述介质层的材料为氧化硅、氮氧化硅、氮化硅、氮化锗、氧化锗、氧化钛、氧化钴、氧化镍和氧化铝中的一种或多种。
15.如权利要求13所述的半导体结构，其特征在于，所述介质层的厚度为至
16.如权利要求13所述的半导体结构，其特征在于，所述修复处理为退火处理和UV照射处理中的一种或两种。
17.如权利要求13所述的半导体结构，其特征在于，所述金属层的材料为Ti、Pt、Ni、Cr、W、Mo、Co和NiPt中的一种或多种。
18.如权利要求13所述的半导体结构，其特征在于，所述金属层的厚度为至
19.如权利要求13所述的半导体结构，其特征在于，所述介质层覆盖所述掺杂外延层的顶部和侧壁。
20.如权利要求13所述的半导体结构，其特征在于，所述基底包括衬底、以及位于所述衬底上分立的鳍部。
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