CN108281478B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN108281478B
CN108281478B CN201710010912.0A CN201710010912A CN108281478B CN 108281478 B CN108281478 B CN 108281478B CN 201710010912 A CN201710010912 A CN 201710010912A CN 108281478 B CN108281478 B CN 108281478B
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layer
dielectric layer
opening
substrate
forming
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CN108281478A (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/863,581 priority patent/US10573563B2/en
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Abstract

一种半导体结构及其形成方法，方法包括：提供基底，基底上形成有层间介质层，层间介质层内具有露出部分基底的开口，开口底部和侧壁形成有叠层结构，叠层结构还位于层间介质层的顶部；至少去除位于层间介质层顶部的叠层结构；至少去除部分所述叠层结构后，对基底进行退火处理；退火处理后，在开口中填充金属层，形成栅极结构。本发明通过采用至少去除位于层间介质层顶部的叠层结构的方法，以减小叠层结构的长度；从而可以减小叠层结构的膨胀量(或收缩量)，相应减小叠层结构因产生过大应力而发生破裂的可能性，以减小栅极漏电流、改善半导体结构中接触孔插塞和栅极结构之间的隔离效果，进而使所形成半导体结构的电学性能和良率得到提高。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体领域，尤其涉及一种半导体结构及其形成方法。
背景技术
集成电路尤其超大规模集成电路的主要半导体器件是金属-氧化物-半导体场效应管(MOS晶体管)。随着集成电路制作技术的不断发展，半导体器件技术节点不断减小，半导体器件的几何尺寸遵循摩尔定律不断缩小。当半导体器件尺寸减小到一定程度时，由半导体器件物理极限所带来的各种二级效应相继出现，半导体器件的特征尺寸按比例缩小变得越来越困难。其中，在半导体制作领域，如何解决半导体器件漏电流大的问题最具挑战性。半导体器件的漏电流大，主要是由传统栅介质层厚度不断减小所引起的。
当前提出的解决方法是，采用高k栅介质材料代替传统的二氧化硅栅介质材料，并使用金属作为栅电极，以避免高k材料与传统栅电极材料发生费米能级钉扎效应以及硼渗透效应。高k金属栅的引入，减小了半导体器件的漏电流。
尽管高k金属栅极的引入能够在一定程度上改善半导体器件的电学性能，但是现有技术形成的半导体器件的电学性能和良率仍有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，优化半导体器件的电学性能和良率。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有层间介质层，所述层间介质层内具有露出部分所述基底的开口，所述开口的底部和侧壁形成有叠层结构，所述叠层结构还位于所述层间介质层的顶部；至少去除位于所述层间介质层顶部的叠层结构；至少去除部分所述叠层结构后，对所述基底进行退火处理；退火处理后，在所述开口中填充金属层，形成栅极结构。
相应的，本发明还提供半导体结构，包括：基底；位于所述基底上的层间介质层，所述层间介质层内具有露出所述部分所述基底的开口；位于所述开口中的叠层结构，所述叠层结构的顶部低于所述开口顶部；金属层，位于所述开口中的叠层结构上。
与现有技术相比，本发明的技术方案具有以下优点：
本发明在提供基底的步骤中，所述基底上形成有层间介质层，所述层间介质层内具有露出部分所述基底的开口，所述开口的底部和侧壁形成有叠层结构，所述叠层结构还位于所述层间介质层的顶部上；在对所述基底进行退火处理之前，至少去除位于所述层间介质层顶部的叠层结构；在所述退火处理的影响下，所述叠层结构经历热胀冷缩，其中膨胀量(或收缩量)与所述叠层结构的长度相关；当所述叠层结构还位于所述层间介质层的顶部上时，所述长度为位于所述开口侧壁上的长度、位于所述开口底部的长度、以及位于所述层间介质层顶部上的长度之和，因此本发明通过采用至少去除位于所述层间介质层顶部的叠层结构的方法，以减小所述叠层结构的长度；从而可以减小所述叠层结构的膨胀量(或收缩量)，相应可以减小所述叠层结构因产生过大应力而发生破裂的可能性，以减小栅极漏电流、改善半导体结构中接触孔插塞和栅极结构之间的隔离效果，进而使所形成半导体结构的电学性能和良率得到提高。
可选方案中，至少去除位于所述层间介质层顶部的叠层结构的步骤中，去除位于所述层间介质层顶部的所述叠层结构，以及所述开口侧壁上部分所述叠层结构；一方面，可以进一步减小所述叠层结构的长度，有利于减小所述叠层结构的膨胀量(或收缩量)；另一方面，去除所述开口侧壁上部分所述叠层结构后，使所述开口的顶部尺寸增大，相应有利于提高后续在所述开口中填充金属层的效果，从而有利于提高所形成栅极结构的质量。
本发明提供一种半导体结构，包括基底；位于所述基底上的层间介质层，所述层间介质层内具有露出所述部分所述基底的开口；位于所述开口中的叠层结构，所述叠层结构的顶部低于所述开口顶部；金属层，位于所述开口中的叠层结构上。其中，在所述半导体结构的形成过程中，形成所述叠层结构时，所述叠层结构还位于所述层间介质层的顶部上，形成所述叠层结构后还经历退火处理，在所述退火处理的影响下，所述叠层结构经历热胀冷缩，其中膨胀量(或收缩量)与所述叠层结构的长度相关；当所述叠层结构还位于所述层间介质层的顶部上时，所述长度为位于所述开口侧壁上的长度、位于所述开口底部的长度、以及位于所述层间介质层顶部上的长度之和，因此本发明通过使所述叠层结构的顶部低于所述开口顶部的方式，以减小所述叠层结构的长度；从而可以减小所述叠层结构的膨胀量(或收缩量)，相应可以减小所述叠层结构因产生过大应力而发生破裂的可能性，以减小栅极漏电流、改善半导体结构中接触孔插塞和栅极结构之间的隔离效果；而且，所述开口的顶部尺寸得到增加，相应有利于提高所述金属层的形成质量，从而有利于提高所述半导体结构的栅极结构质量，因此本发明所述半导体结构的电学性能和良率得到了提高。
附图说明
图1和图2是一种半导体结构的形成方法中各步骤对应的结构示意图；
图3至图17是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图；
图18是本发明半导体结构一实施例的结构示意图。
具体实施方式
由背景技术可知，随着半导体器件技术节点不断减小，目前采用高k栅介质材料代替传统的二氧化硅栅介质材料，以改善半导体栅漏电流(Gate Leakage)和等效栅氧厚度(EOT)等问题。但是，半导体器件的电学性能仍有待提高。结合一种半导体结构的形成方法分析其原因。所述形成方法包括：
参考图1，提供基底，所述基底包括衬底10以及位于所述衬底10上分立的鳍部11；在所述鳍部11露出的衬底10上形成隔离结构12，所述隔离结构12还覆盖所述鳍部11的部分侧壁；形成横跨所述鳍部11的伪栅结构13，所述伪栅结构13还覆盖所述鳍部11的部分侧壁表面和顶部表面；在所述伪栅结构13的侧壁上形成侧墙14；形成所述侧墙14后，在所述伪栅结构13两侧的鳍部11内形成源漏掺杂区15；形成所述源漏掺杂区15后，在所述伪栅结构13露出的基底上形成层间介质层16，所述层间介质层16露出所述伪栅结构13顶部。
参考图2，去除所述伪栅结构13(如图1所示)，在所述层间介质层16内形成露出部分所述鳍部11的开口20；在所述开口20中形成叠层结构(未标示)。
具体地，形成所述叠层结构的步骤包括：在所述开口20的底部和侧壁上形成高k栅介质层21，所述高k栅介质层21还覆盖所述层间介质层16顶部；在所述高k栅介质层21上形成盖帽层22；在所述盖帽层22上形成无定形硅层23。
继续参考图2，形成所述叠层结构后，对所述基底进行退火处理。所述退火处理用于提高所述高k栅介质层21的形成质量。其中，所述退火处理的工艺主要为尖峰退火工艺和激光退火工艺中的一种或两种。
但是，所述退火处理的退火温度较高，由于所述叠层结构中各膜层的热膨胀系数(thermal expansion coefficient)不同，因此在所述退火处理的高温环境下，所述叠层结构内容易产生应力问题，例如所述侧墙14、高k栅介质层21、盖帽层22和无定形硅层23之间的应力问题。当所产生的应力过大时，所述叠层结构可能会出现破裂问题，从而容易引起栅极漏电流增加、接触孔插塞和栅极结构之间的隔离效果变差的问题，进而导致所形成半导体结构的电学性能和良率变差。
各膜层的膨胀量(或收缩量)越大，所产生的应力越大。且膨胀量(或收缩量)的大小与层膜层材料的热膨胀系数、温差以及长度的乘积相关，相应的，膜层的长度越大，膨胀量越大。其中，膜层的长度为位于所述开口20中的长度以及位于所述层间介质层16上的长度之和。以所述无定形硅层23为例，所述无定形硅层23的长度为位于所述开口20侧壁上的长度L2、位于所述开口20底部的长度L3、位于所述层间介质层16顶部上的长度L1以及L4之和，也就是说，所述无定形硅层23的长度为L1+2*L2+L3+L4。
为了解决所述技术问题，本发明在提供基底的步骤中，所述基底上形成有层间介质层，所述层间介质层内具有露出部分所述基底的开口，所述开口的底部和侧壁形成有叠层结构，所述叠层结构还位于所述层间介质层的顶部上；在对所述基底进行退火处理之前，至少去除位于所述层间介质层顶部的叠层结构；在所述退火处理的影响下，所述叠层结构经历热胀冷缩，其中膨胀量(或收缩量)与所述叠层结构的长度相关；当所述叠层结构还位于所述层间介质层的顶部上时，所述长度为位于所述开口侧壁上的长度、位于所述开口底部的长度、以及位于所述层间介质层顶部上的长度之和，因此本发明通过采用至少去除位于所述层间介质层顶部的叠层结构的方法，以减小所述叠层结构的长度；从而可以减小所述叠层结构的膨胀量(或收缩量)，相应可以减小所述叠层结构因产生过大应力而发生破裂的可能性，以减小栅极漏电流、改善半导体结构中接触孔插塞和栅极结构之间的隔离效果，进而使所形成半导体结构的电学性能和良率得到提高。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图17是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
结合参考图3至图9，提供基底(未标示)，所述基底上形成有层间介质层102(如图6所示)，所述层间介质层102内具有露出部分所述基底的开口(未标示)，所述开口的底部和侧壁形成有叠层结构(未标示)，所述叠层结构还位于所述层间介质层102的顶部上。
本实施例中，所述基底用于形成鳍式场效应管，因此所述基底包括衬底100以及位于所述衬底100上分立的鳍部(未标示)。在其他实施例中，所述基底还可以用于形成平面晶体管，相应的，所述基底相应为平面基底。
以下结合附图，对形成所述基底的步骤做详细说明。
结合参考图3和图4，图3是立体图(仅示出两个鳍部)，图4是图3沿AA1割线的剖面结构示意图，形成衬底100以及位于所述衬底100上分立的鳍部(未标示)。
所述衬底100为后续形成鳍式场效应管提供工艺平台，所述鳍部用于提供所形成鳍式场效应晶体管的沟道。
本实施例中，以所形成的鳍式场效应管为CMOS器件为例，所述衬底100包括PMOS区域I(如图4所示)和NMOS区域II(如图4所示)，所述PMOS区域I和NMOS区域II的衬底100上均形成有分立的鳍部。具体地，位于所述PMOS区域I衬底100上的鳍部为第一鳍部110，位于所述NMOS区域II衬底100上的鳍部为第二鳍部120。在其他实施例中，所形成的鳍式场效应管仅包括NMOS器件时，所述衬底仅包括NMOS区域；所形成的鳍式场效应管仅包括PMOS器件时，所述衬底仅包括PMOS区域。
本实施例中，所述PMOS区域I和NMOS区域II为相邻区域。在其他实施例中，所述PMOS区域和NMOS区域还可以相隔离。
所述基底的材料可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述基底还能够为绝缘体上的硅基底或者绝缘体上的锗基底。
为了提高PMOS器件的载流子迁移率，所述PMOS区域I基底为含锗基底。本实施例中，所述PMOS区域I基底为锗基底。在其他实施例中，所述PMOS区域基底的材料还可以为锗化硅，所述PMOS区域基底还能够为绝缘体上的锗基底。所述PMOS区域I基底的材料可以选取适宜于工艺需求或易于集成的材料。
为了提高NMOS器件的载流子迁移率，所述NMOS区域II基底为III－V族化合物基底，例如铟镓砷基底、氮化镓基底或砷化镓基底等。本实施例中，所述NMOS区域II基底的材料为铟镓砷。所述NMOS区域II基底的材料可以选取适宜于工艺需求或易于集成的材料。
具体地，形成所述衬底100和鳍部的步骤包括：提供初始衬底；在所述初始衬底表面形成图形化的鳍部掩膜层200(如图4所示)；以所述鳍部掩膜层200为掩膜刻蚀所述初始衬底，刻蚀后的初始衬底作为衬底100，位于所述衬底100表面的凸起作为鳍部。
本实施例中，形成所述衬底100和鳍部后，保留位于鳍部顶部的鳍部掩膜层200。所述鳍部掩膜层200的材料为氮化硅，后续在进行平坦化处理工艺时，所述鳍部掩膜层200顶部表面用于定义平坦化处理工艺的停止位置，并起到保护所述鳍部顶部的作用。
结合参考图5，需要说明的是，形成所述衬底100和鳍部后，所述形成方法还包括：在所述鳍部露出的衬底100上形成隔离结构101，所述隔离结构101覆盖所述鳍部的部分侧壁，且所述隔离结构101顶部低于所述鳍部顶部。
所述隔离结构101作为半导体器件的隔离结构，用于对相邻器件起到隔离作用，还用于对相邻鳍部起到隔离作用。本实施例中，所述隔离结构101的材料为氧化硅。在其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅。
具体地，形成所述隔离结构101的步骤包括：在所述鳍部露出的衬底100上填充隔离膜，所述隔离膜顶部高于所述鳍部掩膜层200(如图4所示)顶部；研磨去除高于所述鳍部掩膜层200顶部的隔离膜；回刻部分厚度的剩余隔离膜，暴露出所述鳍部的顶部以及部分侧壁，形成所述隔离结构101；去除所述鳍部掩膜层200。
参考图6，图6是基于图5沿鳍部延伸方向割线(如图3中BB1割线所示)的剖面结构示意图，形成横跨所述鳍部的伪栅结构105，所述伪栅结构105还覆盖所述鳍部(未标示)的部分顶部和侧壁表面。
本实施例中，采用后形成高k栅介质层后形成栅电极层(high k last metal gatelast)的工艺，所述PMOS区域I的伪栅结构105为后续形成PMOS器件的栅极结构占据空间位置，所述NMOS区域II的伪栅结构105为后续形成NMOS器件的栅极结构占据空间位置。
所述伪栅结构105为单层结构或叠层结构。所述伪栅结构105包括伪栅层；或者所述伪栅结构105包括伪氧化层以及位于所述伪氧化层上的伪栅层。其中，所述伪栅层的材料为多晶硅、氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳，所述伪氧化层的材料为氧化硅或氮氧化硅。
本实施例中，形成所述伪栅结构105后，所述形成方法还包括：在所述伪栅结构105的侧壁上形成侧墙130；形成所述侧墙130后，在所述伪栅结构105两侧的鳍部内形成源漏掺杂区(未标示)。
所述侧墙130用于定义所述源漏掺杂区的位置。所述侧墙130的材料可以为氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼或碳氮化硼，所述侧墙130可以为单层结构或叠层结构。本实施例中，所述侧墙130为单层结构，所述侧墙130的材料为氮化硅。
本实施例中，所述衬底100包括PMOS区域I以及NMOS区域II，因此形成所述源漏掺杂区的步骤中，在所述PMOS区域I伪栅结构105两侧的第一鳍部110内形成第一源漏掺杂区112，在所述NMOS区域II伪栅结构105两侧的第二鳍部120内形成第二源漏掺杂区122。具体地，所述第一源漏掺杂区112的掺杂离子为P型离子，例如为B、Ga和In中的一种或多种；所述第二源漏掺杂区122的掺杂离子为N型离子，例如为P、As和Sb中的一种或多种。
继续参考图6，形成所述源漏掺杂区(未标示)后，在所述伪栅结构105露出的基底上形成层间介质层102，所述层间介质层102露出所述伪栅结构105的顶部。
所述层间介质层102为后续形成PMOS器件和NMOS器件的栅极结构提供工艺平台，且为接触孔插塞(CT)形成工艺提供工艺平台，同时对相邻器件之间起到隔离作用。
所述层间介质层102的材料为绝缘材料。所述层间介质层102的材料可以为氧化硅、氮化硅、氮氧化硅或碳氮氧化硅。本实施例中，所述层间介质层102的材料为氧化硅。
本实施例中，所述层间介质层102顶部与所述伪栅结构105顶部齐平。具体地，形成所述层间介质层102的工艺步骤包括：在所述伪栅结构105露出的基底上形成层间介质膜，所述层间介质膜的顶部高于所述伪栅结构105的顶部；去除高于所述伪栅结构105顶部的层间介质膜，形成所述层间介质层102。
参考图7，去除所述伪栅结构105(如图6所示)，在所述层间介质层102内形成露出部分所述鳍部(未标示)的开口(未标示)。
本实施例中，位于所述PMOS区域I的开口为第一开口141，位于所述NMOS区域II的开口为第二开口142。具体地，去除所述PMOS区域I的伪栅结构105，在所述PMOS区域I的层间介质层102内形成露出部分所述第一鳍部110的第一开口141；去除所述NMOS区域II的伪栅结构105，在所述NMOS区域II的层间介质层102内形成露出部分所述第二鳍部120的第二开口142。
结合参考图8和图9，在所述开口(未标示)的底部和侧壁上形成高k栅介质层300(如图8所示)，所述高k栅介质层300还覆盖所述层间介质层102顶部；在所述高k栅介质层300上形成盖帽层310(如图9所示)；在所述盖帽层320上形成牺牲层330(如图9所示)；其中，所述高k栅介质层300、盖帽层310和牺牲层320构成所述叠层结构(未标示)。
所述高k栅介质层300的材料为相对介电常数大于氧化硅相对介电常数的栅介质材料。本实施例中，所述高k栅介质层300的材料为HfO2。在其他实施例中，所述高k栅介质层的材料还可以为HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
本实施例中，采用原子层沉积工艺形成所述高k栅介质层300，所述高k栅介质层300除位于第一开口141内以及第二开口142内，还位于所述层间介质层102的顶部上。
需要说明的是，为了使得所述高k栅介质层300与基底之间具有良好的界面性能，提高所述高k栅介质层300的形成质量，在形成所述高k栅介质层300之前，所述形成方法还包括：在所述第一开口141底部以及第二开口142底部形成界面层(IL，Interfacial Layer)(图未示)。本实施例中，采用化学浸润氧化工艺形成所述界面层，所述界面层的材料为氧化硅。
后续在所述第一开口141和第二开口142中形成功函数层时，所述盖帽层(Caplayer)310用于对所述高k栅介质层300起到保护作用，避免所述功函数层中的金属离子扩散至所述高k栅介质层300中；同时，所述盖帽层310还可以防止所述高k栅介质层300中的氧离子扩散至所述功函数层中，从而避免所述高k栅介质层300出现氧空位含量增加的问题。本实施例中，所述盖帽层310的材料为TiN。在其他实施例中，所述盖帽层的材料还可以为TiSiN或TaN。
所述牺牲层320用于提高后续所形成器件的电学性能稳定性。本实施例中，所述牺牲层320的材料为无定形硅(a-Si)。
后续步骤包括：在所述第一开口141和第二开口142中形成填充层，所述填充层还覆盖所述牺牲层320顶部；去除高于所述牺牲层320顶部的填充层。其中，在去除高于所述牺牲层320顶部的填充层的步骤中，所述牺牲层320的顶部表面用于定义停止位置；而且所述牺牲层320在后续步骤中被去除。因此，所述牺牲层320的厚度不宜过小，也不宜过大。如果所述牺牲层320的厚度过小，则难以较好地起到定义停止位置的作用；如果所述牺牲层320的厚度过大，容易增加后续去除所述牺牲层320的工艺难度。为此，本实施例中，所述牺牲层320的厚度为
Figure BDA0001204511940000101
至
Figure BDA0001204511940000102
还需要说明的是，结合参考图8，为了提高所述高k栅介质层300的质量和性能，形成所述高k栅介质层300后，形成所述盖帽层310之前，所述形成方法还包括：对所述基底进行第一退火处理301。
本实施例中，所述第一退火处理301为快速热退火处理。所述快速热退火处理的参数包括：退火温度为600℃至800℃。在其他实施例中，所述第一退火处理还可以为尖峰退火处理。
结合参考图10至图14，至少去除位于所述层间介质层102顶部的叠层结构(未标示)。
后续步骤包括对所述基底进行第二退火处理，在所述第二退火处理的影响下，所述叠层结构经历热胀冷缩，其中膨胀量(或收缩量)与所述叠层结构的长度相关；所述长度为位于所述开口侧壁上的长度、位于所述开口底部的长度、以及位于所述层间介质层102顶部上的长度之和；因此通过采用至少去除位于所述层间介质层102顶部的叠层结构的方式，以减小所述叠层结构的长度，从而减小所述叠层结构的膨胀量(或收缩量)。
本实施例中，至少去除位于所述层间介质层102顶部的叠层结构的步骤中，去除位于所述层间介质层102顶部的所述叠层结构、以及所述开口(未标示)侧壁上部分所述叠层结构。具体地，去除位于所述层间介质层102顶部的所述高k栅介质层300、盖帽层310和牺牲层320，还去除所述开口(未标示)侧壁上部分所述高k栅介质层300、盖帽层310和牺牲层320。在其他实施例中，可以仅去除位于所述层间介质层顶部的所述叠层结构。
去除所述开口(未标示)侧壁上部分所述叠层结构的做法，一方面，可以进一步减小所述叠层结构的长度，有利于减小所述叠层结构的膨胀量(或收缩量)；另一方面，可以使所述开口的顶部尺寸增大，相应有利于提高后续在所述开口中填充金属层的效果，从而有利于提高后续所形成栅极结构的质量。
需要说明的是，被去除的开口侧壁上所述叠层结构的高度M(如图13所示)不宜过大。如果所述高度M过大，则所述开口侧壁上所述叠层结构的剩余量过少，而所述高k栅介质层300和盖帽层310作为后续所形成栅极结构的一部分，因此容易导致后续所形成栅极结构的质量下降。为此，本实施例中，为了提升减小所述叠层结构长度效果的同时，避免对后续所形成栅极结构的质量造成不良影响，在去除所述开口侧壁上部分所述叠层结构的步骤中，被去除的开口侧壁上所述叠层结构的高度M占所述开口深度的比例小于或等于1/3。
以下将结合附图，对去除位于所述层间介质层102顶部以及所述开口侧壁上部分所述叠层结构的步骤做详细说明。
参考图10，在所述开口中形成填充层400，所述填充层400还覆盖所述叠层结构(未标示)的顶部。
后续去除所述开口中部分厚度的所述填充层400，剩余所述填充层400为去除部分所述叠层结构提供工艺基础，且在去除高于所述层间介质层102顶部以及所述开口侧壁上预设厚度M(如图13所示)的所述叠层结构后，去除所述填充层400。
因此，所述填充层400的材料与所述叠层结构的材料不同，与所述层间介质层102的材料不同，且所述填充层400的材料为易于被去除的材料，从而减小后续去除所述填充层400的工艺对所述叠层结构和层间介质层102造成的损伤。
本实施例中，所述填充层400的材料为ODL(Organic Dielectric Layer)材料，采用旋转涂覆工艺形成所述填充层400。具体地，所述填充层400填充于所述第一开口141(如图9所示)和第二开口142(如图9所示)中，且所述填充层400的顶部高于所述牺牲层320的顶部。在其他实施例中，所述填充层的材料还可以为BARC(Bottom Anti-ReflectiveCoating)材料、DUO(Deep UV Light Absorbing Oxide)材料或光刻胶材料。其中，所述DUO材料是一种硅氧烷聚合体材料，包括CH3-SiOX、Si-OH、或SiOH3等。
参考图11，采用第一去除工艺，去除位于所述叠层结构顶部的填充层400，露出所述叠层结构400的顶部。
通过所述第一去除工艺，为后续去除所述开口中部分厚度的所述填充层400提供工艺基础，从而使后续所述开口中的剩余填充层400的厚度均一性得到提高。
具体地，以所述牺牲层320的顶部表面为停止位置，去除高于所述牺牲层320的填充层400，即所述第一去除工艺后，剩余所述填充层400的顶部与所述牺牲层230的顶部齐平。本实施例中，所述第一去除工艺为化学机械研磨工艺。在其他实施例中，所述第一去除工艺还可以为干法刻蚀工艺。
参考图12，采用第二去除工艺，去除所述开口(未标示)中部分厚度的所述填充层400。
所述第二去除工艺后，剩余所述填充层400为后续对所述叠层结构进行刻蚀提供工艺基础，即后续步骤包括去除高于剩余所述填充层400的叠层结构；且所述填充层400还可以在后续去除所述叠层结构的工艺过程中，对所述开口底部的叠层结构起到保护作用。因此，在所述第二去除工艺的步骤中，所述填充层400的去除量H根据后续被去除的开口侧壁上所述叠层结构的高度M(如图13所示)而定。
具体地，去除所述第一开口141(如图9所示)以及第二开口142(如图9所示)中部分厚度所述填充层400。本实施例中，所述第二去除工艺为干法刻蚀工艺。
参考图13，在所述第二去除工艺后，去除高于剩余所述填充层400顶部的叠层结构。
具体地，去除位于所述层间介质层102顶部的所述高k栅介质层300、盖帽层310和牺牲层320后，还去除所述第一开口141(如图9所示)以及第二开口142(如图9所示)侧壁上部分所述高k栅介质层300、盖帽层310和牺牲层320。
本实施例中，去除高于剩余所述填充层400顶部的叠层结构的步骤中，所采用的工艺为干法刻蚀工艺。具体地，去除高于剩余所述填充层400顶部的牺牲层320后，去除高于剩余所述填充层400顶部的盖帽层310，再去除高于剩余所述填充层400顶部的高k栅介质层300。其中，通过分别设定所述牺牲层320、盖帽层310和高k栅介质层300所对应干法刻蚀工艺的工艺参数至合理值，以达到工艺所需去除量。
参考图14，去除高于剩余所述填充层400(如图13所示)顶部的叠层结构后，去除剩余所述填充层400。
本实施例中，采用干法刻蚀工艺刻蚀去除所述填充层400。具体地，所述干法刻蚀工艺采用的刻蚀气体包括CF4或CHF3。在其他实施例中，还可以采用湿法刻蚀工艺刻蚀去除所述填充层。
参考图15，至少去除部分所述叠层结构(未标示)后，对所述基底进行第二退火处理302。
所述第二退火处理302用于对所述高k栅介质层300进行修复，提高所述高k栅介质层300的致密度，从而有利于提高所述高k栅介质层300的质量和性能。
本实施例中，所述第二退火处理302的工艺为尖峰退火处理。其中，为了提高所述高k栅介质层300的质量和性能的同时，避免对所述基底内已有掺杂离子的分布造成不良影响，所述尖峰退火处理的参数包括：退火温度为800℃至1000℃，压强为一个标准大气压。
在另一实施例中，所述第二退火处理的工艺为激光退火处理。其中，所述激光退火处理的参数包括：退火温度为950℃至1150℃，压强为一个标准大气压。
在其他实施例中，所述第二退火处理的步骤包括：对所述基底进行尖峰退火处理，并在尖峰退火处理后，对所述基底进行激光退火处理。通过先进行温度较低的尖峰退火处理，再进行温度较高的激光退火的方式，可以避免掺杂离子发生钝化的问题。
需要说明的是，至少去除位于所述层间介质层102顶部的叠层结构后，所述形成方法还包括：去除剩余所述牺牲层320(如图15所示)。
本实施例中，采用湿法刻蚀工艺去除剩余所述牺牲层320，所述湿法刻蚀工艺所采用的刻蚀溶液包括四甲基氢氧化铵(TMAH)溶液或氨水(NH4OH)，溶液温度为25℃至75℃。
结合参考图16和图17，第二退火处理302(如图15所示)后，在所述开口(未标示)中填充金属层350(如图17所示)，形成栅极结构(未标示)。
本实施例中，形成所述栅极结构的步骤中，所述开口中的剩余高k栅介质层300、盖帽层310以及所述金属层350用于构成所述栅极结构，所述栅极结构横跨所述鳍部(未标示)，且还覆盖所述鳍部的部分顶部和侧壁表面。
本实施例中，所述金属层350的材料为W。在其他实施例中，所述金属层的材料还可以为Al、Cu、Ag、Au、Pt、Ni或Ti。
需要说明的是，结合参考图16，至少去除部分所述叠层结构后，填充所述金属层350之前，所述形成方法还包括：在所述第一开口141的底部和侧壁上、所述第二开口142的底部和侧壁上形成P型功函数层330，所述P型功函数层330还覆盖所述层间介质层102顶部；去除所述NMOS区域II的P型功函数层330；去除所述NMOS区域II的P型功函数层330后，在所述第二开口142的底部和侧壁上形成N型功函数层340，所述N型功函数层340还覆盖所述NMOS区域II的层间介质层102顶部，还覆盖所述P型功函数层330。其中，为了降低工艺难度、节约光罩，本实施例中，形成所述N型功函数层340后，保留位于所述P型功函数层330上的所述N型功函数层340。
由于所述高k栅介质层300和盖帽层310的顶部低于所述开口(未标示)的顶部，因此形成所述P型功函数层330的步骤中，所述P型功函数层330位于所述第一开口141中的盖帽层310上以及所述第一开口141露出的侧墙130上；形成所述N型功函数层340的步骤中，所述N型功函数层340位于所述第二开口142中的盖帽层310上以及所述第二开口142露出的侧墙130上。
所述P型功函数层330用于调节P型器件的阈值电压，所述P型功函数层330的材料为P型功函数材料，P型功函数材料功函数范围为5.1eV至5.5eV，例如，5.2eV、5.3eV或5.4eV。所述P型功函数层330的材料可以为TiN、TaN、TaSiN和TiSiN中的一种或几种，可以采用化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺形成所述P型功函数层330。
所述N型功函数层340用于调节N型器件的阈值电压，所述N型功函数层340的材料为N型功函数材料，N型功函数材料功函数范围为3.9eV至4.5eV，例如为4eV、4.1eV或4.3eV。所述N型功函数层340的材料可以为TiAl、TiAlC、TaAlN、TiAlN、TaCN和AlN中的一种或多种，可以采用化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺形成所述N型功函数层340。
相应的，形成所述栅极结构的步骤包括：在所述第一开口141(如图16所示)和第二开口142(如图16所示)中填充金属层350，所述金属层350还覆盖所述N型功函数层340的顶部；去除位于所述层间介质层102顶部的金属层350，且还去除位于所述层间介质层102顶部的N型功函数层340和P型功函数层330；所述第一开口141中的高k栅介质层300、盖帽层310、P型功函数层330、N型功函数层340和金属层350构成所述PMOS区域I的栅极结构，且所述PMOS区域I的栅极结构为第一栅极结构510；所述第二开口142中的高k栅介质层300、盖帽层310、N型功函数层340和金属层350构成所述NMOS区域II的栅极结构，且所述NMOS区域II的栅极结构为第二栅极结构520。
参考图18，示出了本发明半导体结构一实施例的结构示意图。相应的，本发明还提供一种半导体结构。所述半导体结构包括：
基底；位于所述基底上的层间介质层602，所述层间介质层602内具有露出所述部分所述基底的开口(未标示)；位于所述开口中的叠层结构(未标示)，所述叠层结构的顶部低于所述开口顶部；金属层750，位于所述开口中的叠层结构上。
本实施例中，所述基底具有鳍式场效应管，因此所述基底包括衬底600以及位于所述衬底600上分立的鳍部(未标示)。在其他实施例中，所述基底具有平面晶体管，相应的，所述基底相应为平面基底。
本实施例中，以所述基底上的鳍式场效应管为CMOS器件为例，所述衬底600包括PMOS区域I和NMOS区域II，所述PMOS区域I和NMOS区域II的衬底600上均具有分立的鳍部。具体地，位于所述PMOS区域I衬底600上的鳍部为第一鳍部610，位于所述NMOS区域II衬底600上的鳍部为第二鳍部620。在其他实施例中，所述鳍式场效应管仅包括NMOS器件时，所述衬底仅包括NMOS区域；所述鳍式场效应管仅包括PMOS器件时，所述衬底仅包括PMOS区域。
本实施例中，所述PMOS区域I和NMOS区域II为相邻区域。在其他实施例中，所述PMOS区域和NMOS区域还可以相隔离。
所述基底的材料可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述基底还能够为绝缘体上的硅基底或者绝缘体上的锗基底。
为了提高PMOS器件的载流子迁移率，所述PMOS区域I基底为含锗基底。本实施例中，所述PMOS区域I基底为锗基底。在其他实施例中，所述PMOS区域基底的材料还可以为锗化硅，所述PMOS区域基底还能够为绝缘体上的锗基底。所述PMOS区域I基底的材料可以选取适宜于工艺需求或易于集成的材料。
为了提高NMOS器件的载流子迁移率，所述NMOS区域II基底为III－V族化合物基底，例如铟镓砷基底、氮化镓基底或砷化镓基底等。本实施例中，所述NMOS区域II基底的材料为铟镓砷。所述NMOS区域II基底的材料可以选取适宜于工艺需求或易于集成的材料。
需要说明的是，所述半导体结构还包括：位于所述鳍部所露出衬底600上的隔离结构601，所述隔离结构601覆盖所述鳍部的部分侧壁，且所述隔离结构601顶部低于所述鳍部顶部。所述隔离结构101作为半导体器件的隔离结构，用于对相邻器件起到隔离作用，还用于对相邻所述鳍部起到隔离作用。本实施例中，所述隔离结构601的材料为氧化硅。在其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅。
所述层间介质层602的材料为绝缘材料，用于为接触孔插塞(CT)的形成工艺提供工艺平台，同时还用于对相邻器件之间起到隔离作用。所述层间介质层602的材料可以为氧化硅、氮化硅、氮氧化硅或碳氮氧化硅。本实施例中，所述层间介质层602的材料为氧化硅。
本实施例中，位于所述PMOS区域I的开口为第一开口(未标示)，位于所述NMOS区域II的开口为第二开口(未标示)。所述第一开口露出部分所述第一鳍部610，所述第二开口露出部分所述第二鳍部620。相应的，位于所述PMOS区域I的叠层结构横跨所述第一鳍部610，且覆盖所述第一鳍部610的部分顶部和侧壁表面，位于所述NMOS区域II的叠层结构横跨所述第二鳍部620，且覆盖所述第二鳍部620的部分顶部和侧壁表面。
本实施例中，所述叠层结构包括：位于所述开口底部以及部分开口侧壁上的高k栅介质层700；位于所述高k栅介质层700上的盖帽层710。所述开口中的高k栅介质层700、盖帽层710和金属层750用于构成所述半导体结构的栅极结构，所述栅极结构顶部与所述层间介质层602顶部齐平。具体地，位于所述第一开口中的高k栅介质层700、盖帽层710和金属层750用于构成第一栅极结构810，位于所述第二开口中的高k栅介质层700、盖帽层710和金属层750用于构成第二栅极结构820。
需要说明的是，所述半导体结构还包括：位于所述开口侧壁上的侧墙630；位于所述开口两侧鳍部内的源漏掺杂区。
所述侧墙630用于定义所述源漏掺杂区的位置。所述侧墙630的材料可以为氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼或碳氮化硼，所述侧墙630可以为单层结构或叠层结构。本实施例中，所述侧墙630为单层结构，所述侧墙630的材料为氮化硅。
本实施例中，位于所述第一开口两侧第一鳍部610内的源漏掺杂区为第一源漏掺杂区612，位于所述第二开口两侧第二鳍部620内的源漏掺杂区为第二源漏掺杂区622。也就是说，所述第一源漏掺杂区612位于所述第一栅极结构810两侧的第一鳍部610内，所述第二源漏掺杂区622位于所述第二栅极结构820两侧的第二鳍部620内。具体地，所述第一源漏掺杂区612的掺杂离子为N型离子，例如为P、As或Sb，所述第二源漏掺杂区622的掺杂离子为P型离子，例如为B、Ga或In。
相应的，所述述高k栅介质层700位于所述开口底部以及部分所述侧墙630上。所述高k栅介质层700的材料为相对介电常数大于氧化硅相对介电常数的栅介质材料。本实施例中，所述高k栅介质层700的材料为HfO2。在其他实施例中，所述高k栅介质层的材料还可以为HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。
需要说明的是，为了使得所述高k栅介质层700与基底之间具有良好的界面性能，提高所述高k栅介质层700的质量，所述半导体结构还包括：位于所述第一开口底部以及第二开口底部的界面层(IL，Interfacial Layer)(图未示)。本实施例中，所述界面层的材料为氧化硅。
还要说明的是，在所述半导体结构的形成过程中，形成所述叠层结构时，所述叠层结构还位于所述层间介质层602的顶部上，形成所述叠层结构后还经历退火处理；在所述退火处理的影响下，所述叠层结构经历热胀冷缩，其中膨胀量(或收缩量)与所述叠层结构的长度相关；当所述叠层结构还位于所述层间介质层602的顶部上时，所述长度为位于所述开口侧壁上的长度、位于所述开口底部的长度、以及位于所述层间介质层602顶部上的长度之和。
因此，本实施例中，所述叠层结构的顶部低于所述开口顶部，一方面，有利于进一步减小所述叠层结构的长度，以减小所述叠层结构的膨胀量(或收缩量)，另一方面，有利于增加所述开口的顶部尺寸，从而有利于提高所述金属层530的质量。
需要说明的是，所述叠层结构顶部与所述开口顶部的距离占所述开口深度的比例不宜过大。如果所述比例过大，则位于所述开口部分侧壁上叠层结构的厚度过小，而所述高k栅介质层300和盖帽层310作为所述栅极结构的一部分，因此容易导致所述栅极结构的质量下降。为此，本实施例中，所述叠层结构顶部与所述开口顶部的距离占所述开口深度的比例小于或等于1/3。
本实施例中，所述半导体结构还包括用于调节器件阈值电压的功函数。具体地，所述功函数层包括：P型功函数层730，位于所述金属层750和所述第一开口中的叠层结构之间；N型功函数层740，位于所述金属层750和所述第二开口中的叠层结构之间。
所述P型功函数层730用于调节P型器件的阈值电压，所述P型功函数层730的材料为P型功函数材料，P型功函数材料功函数范围为5.1eV至5.5eV，例如，5.2eV、5.3eV或5.4eV。所述P型功函数层730的材料可以为TiN、TaN、TaSiN和TiSiN中的一种或几种。
所述N型功函数层740用于调节N型器件的阈值电压，所述N型功函数层740的材料为N型功函数材料，N型功函数材料功函数范围为3.9eV至4.5eV，例如为4eV、4.1eV或4.3eV。所述N型功函数层740的材料可以为TiAl、TiAlC、TaAlN、TiAlN、TaCN和AlN中的一种或多种。
需要说明的是，为了降低形成所述N型功函数层740的工艺难度、节约光罩，所述N型功函数层740还位于所述金属层750和所述P型功函数层730之间。相应的，所述第一栅极结构810还包括所述P型功函数层730和N型功函数层740，所述第二栅极结构820还包括所述N型功函数层740。
所述盖帽层710的作用包括：一方面，用于对所述高k栅介质层700起到保护作用，避免所述功函数层中的金属离子扩散至所述高k栅介质层700中；另一方面，所述盖帽层710还可以防止所述高k栅介质层700中的氧离子扩散至所述功函数层中，从而避免所述高k栅介质层700出现氧空位含量增加的问题。本实施例中，所述盖帽层710的材料为TiN。在其他实施例中，所述盖帽层的材料还可以为TiSiN或TaN。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (13)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底上形成有层间介质层，所述层间介质层内具有露出部分所述基底的开口，所述开口的底部和侧壁形成有叠层结构，所述叠层结构还位于所述层间介质层的顶部；
至少去除位于所述层间介质层顶部及所述开口部分侧壁上的叠层结构；
至少去除部分所述叠层结构后，对所述基底进行退火处理；
退火处理后，在所述开口的底部和侧壁上形成功函数层，所述功函数层覆盖剩余的叠层结构的顶部；
在所述开口中填充金属层，所述金属层还覆盖所述功函数层，所述开口中剩余的叠层结构和金属层用于构成栅极结构形成栅极结构。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，去除所述开口侧壁上部分所述叠层结构的步骤中，被去除的开口侧壁上所述叠层结构的高度占所述开口深度的比例小于或等于1/3。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，去除位于所述层间介质层顶部以及所述开口侧壁上部分所述叠层结构的步骤包括：在所述开口中形成填充层，所述填充层还覆盖所述叠层结构的顶部；
采用第一去除工艺，去除位于所述叠层结构顶部的填充层，露出所述叠层结构的顶部；
采用第二去除工艺，去除所述开口中部分厚度的所述填充层；
在所述第二去除工艺后，去除高于剩余所述填充层顶部的叠层结构；
去除高于剩余所述填充层顶部的叠层结构后，去除剩余所述填充层。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，所述第一去除工艺为干法刻蚀工艺或化学机械研磨工艺。
5.如权利要求3所述的半导体结构的形成方法，其特征在于，所述第二去除工艺为干法刻蚀工艺。
6.如权利要求3所述的半导体结构的形成方法，其特征在于，所述填充层的材料为ODL材料、BARC材料、DUO材料或光刻胶。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，至少去除位于所述层间介质层顶部的叠层结构的步骤中，所采用的工艺为干法刻蚀工艺。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，对所述基底进行退火处理的步骤中，所述退火处理的步骤包括：对所述基底进行尖峰退火处理；或者，对所述基底进行激光退火处理；或者，对所述基底进行尖峰退火处理，并在尖峰退火处理后，对所述基底进行激光退火处理。
9.如权利要求8所述的半导体结构的形成方法，其特征在于，所述尖峰退火处理的参数包括：退火温度为800℃至1000℃，压强为一个标准大气压。
10.如权利要求8所述的半导体结构的形成方法，其特征在于，所述激光退火处理的参数包括：退火温度为950℃至1150℃，压强为一个标准大气压。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，提供基底的步骤包括：形成衬底以及位于所述衬底上分立的鳍部；形成横跨所述鳍部的伪栅结构，所述伪栅结构还覆盖所述鳍部的部分顶部和侧壁表面；在所述伪栅结构的侧壁上形成侧墙；形成所述侧墙后，在所述伪栅结构两侧的鳍部内形成源漏掺杂区；形成所述源漏掺杂区后，在所述伪栅结构露出的基底上形成层间介质层，所述层间介质层露出所述伪栅结构的顶部；去除所述伪栅结构，在所述层间介质层内形成露出部分所述鳍部的开口；在所述开口的底部和侧壁上形成高k栅介质层，所述高k栅介质层还覆盖所述层间介质层顶部；在所述高k栅介质层上形成盖帽层；在所述盖帽层上形成牺牲层；其中，所述高k栅介质层、盖帽层和牺牲层构成所述叠层结构；
至少去除位于所述层间介质层顶部的叠层结构的步骤中，去除位于所述层间介质层顶部的所述高k栅介质层、盖帽层和牺牲层、以及所述开口侧壁上部分所述高k栅介质层、盖帽层和牺牲层；
对所述基底进行退火处理后，在所述开口中填充金属层之前，所述形成方法还包括：去除剩余所述牺牲层；
形成栅极结构的步骤中，所述开口中的剩余高k栅介质层、盖帽层以及所述金属层用于构成所述栅极结构，所述栅极结构横跨所述鳍部，且还覆盖所述鳍部的部分顶部和侧壁表面。
12.如权利要求11所述的半导体结构的形成方法，其特征在于，所述牺牲层的材料为无定形硅。
13.如权利要求11所述的半导体结构的形成方法，其特征在于，所述牺牲层的厚度为
Figure FDA0003035235890000031
至
Figure FDA0003035235890000032
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