CN109309051B - 集成电路及其形成方法 - Google Patents
集成电路及其形成方法 Download PDFInfo
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- CN109309051B CN109309051B CN201810834899.5A CN201810834899A CN109309051B CN 109309051 B CN109309051 B CN 109309051B CN 201810834899 A CN201810834899 A CN 201810834899A CN 109309051 B CN109309051 B CN 109309051B
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- Element Separation (AREA)
Abstract
本发明的不同实施例涉及一种将NVM器件与逻辑或BCD器件集成的方法。在一些实施例中,隔离结构在半导体衬底中形成。隔离结构划分半导体衬底的存储区域,并且进一步地划分半导体衬底的外围区域。外围区域可诸如对应于BCD器件或逻辑器件。掺杂阱在外围区域中形成。介电密封层形成为覆盖存储区域和外围区域并且进一步覆盖掺杂阱。介电密封层从存储区域而非从外围区域去除。使用热氧化工艺在存储区域上形成存储单元结构。介电密封层从外围区域去除,并且包括栅电极的外围器件结构在外围区域上形成。本发明的实施例还提供了利用所述方法所形成的集成电路结构。
Description
背景技术
集成电路(IC)制造工业在之前的几十年中经历了指数型增长。随着IC发展,在几何尺寸(也就是说,能够制造的最小组件)普遍减小的同时,功能密度(也就是说,每芯片面积互连器件的数量)普遍增大。IC发展中的进展包括非易失性存储器(NVM)与逻辑技术或双极互补金属氧化物半导体(CMOS)双扩散金属氧化物半导体(DMOS)(BCD)集成的技术。BCD技术可能为或包括诸如将双极结型晶体管(BJT)、CMOS器件、以及DMOS器件一起集成在同一半导体芯片上。除此之外,NVM与逻辑或BCD集成的技术在电源管理、物联网(LoT)、智能卡、微控制器单元(MCU)以及车载设备中获得应用。
发明内容
根据本发明的一个方面,提供了一种用于形成集成电路的方法,所述方法包括:提供包括第一器件区域和第二器件区域的半导体衬底,所述第一器件区域和所述第二器件区域由隔离结构分隔;在所述第二器件区域中形成掺杂阱;形成覆盖所述第一器件区域和所述第二器件区域并且还覆盖所述掺杂阱的密封层;从所述第一器件区域而不是从所述第二器件区域处去除所述密封层;在所述第一器件区域上形成存储单元结构;在形成所述存储单元结构之后,从所述第二器件区域处去除所述密封层;以及在所述第二器件区域上形成器件结构。
根据本发明的另一个方面,提供了一种集成电路,包括:半导体衬底,包括第一器件区域和第二器件区域;隔离结构,延伸进入所述半导体衬底的顶面,其中,所述隔离结构划分和分隔所述第一器件区域和所述第二器件区域;存储单元,覆盖所述第一器件区域;金属氧化物半导体(MOS)器件,覆盖所述第二器件区域;以及伪结构,覆盖所述隔离结构,其中,所述伪结构包括伪密封元件。
根据本发明的又一个方面,提供了一种用于形成集成电路的方法,该方法包括:在半导体衬底中形成隔离结构,其中,所述隔离结构划分半导体衬底的存储区域,并且还划分所述半导体衬底的外围区域;在所述外围区域中形成掺杂阱;形成覆盖所述存储区域和所述外围区域并且还覆盖所述掺杂阱的密封层;从所述存储区域而非从所述外围区域处去除所述密封层;通过热氧化工艺在所述存储区域形成栅极介电层,其中,所述热氧化工艺使所述半导体衬底的顶面在所述存储区域而非在所述外围区域凹陷;在所述栅极介电层上方形成存储栅电极;在形成所述存储栅电极之后,从所述外围区域处去除所述密封层;以及在同时形成邻接所述存储栅电极的第二存储栅电极的同时,在所述外围区域上形成外围栅电极。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减小。
图1A和图1B示出了包括存储器件以及双极互补金属氧化物半导体(CMOS)双扩散金属氧化物半导体(DMOS)(BCD)或逻辑器件的集成电路(IC)的截面图;
图2A和图2B分别示出了图1A和图1B中的IC的一些更详细的实施例的截面图;
图3至图23示出了形成包括存储器件以及BCD或逻辑器件的IC的密封方法的一些实施例的一系列截面图;
图24示出了图3至图23中的密封方法的一些实施例的流程图;
图25至图32示出了图3至图23中的密封方法的另一些实施例的一系列截面图。
具体实施方式
本公开提供许多不同的实施例或示例,用于实施本公开的不同特征。组件和设置的具体的示例在下方描述以简化本公开。当然,这些仅为示例并且并不旨在为限制性的。例如,在描述中第一特征在第二特征上方的形成可包括第一特征和第二特征直接接触形成的实施例,并且还可包括另外的特征可形成在第一特征和第二特征之间的实施例,从而第一特征和第二特征可不直接接触。另外,本公开在不同的示例中可重复参考数字和/或字母。该重复出于简化和清晰的目的并且其本身并不指定在讨论的不同实施例和/或配置之间的关系。
进一步地,空间相对词语,诸如“在…下方”、“在…下”、“低于”、“在…上方”、“上部”以及类似的,为了简化说明书以描述如图中示出的一个元素或特征相对于另一个元素或特征的关系可在此使用。空间相对词语旨在包含除了图中描述的方向之外使用或操作中的器件的不同方向。装置可以其他方式定向(转动90度或以其他方向)并且在此使用的空间相对词语可相应地类似解释。
一种用于将非易失性存储器(NVM)器件与逻辑器件和/或双极互补金属氧化物半导体(CMOS)双扩散金属氧化物半导体(DMOS)(BCD)器件集成的方法包括:形成延伸进入半导体衬底的顶面以及划分半导体衬底的存储区域、半导体衬底的逻辑区域和半导体衬底的BCD区域的浅沟道隔离(STI)结构。BCD阱和逻辑阱分别在BCD区域和逻辑区域形成,并且BCD栅氧层随后形成为覆盖逻辑区域、BCD区域、以及存储区域。BCD栅极氧化物层从存储区域而非从逻辑和BCD区域去除,并且执行一系列工艺以在存储区域上形成存储结构。工艺包括热工艺和氧化工艺,并且存储结构包括存储栅极氧化物层。此后,BCD栅极氧化物层从逻辑区域而从非BCD区域去除,并且执行一系列工艺以在逻辑区域上形成逻辑栅极氧化物层。导电层形成为覆盖存储区、逻辑区、以及BCD区域,并且导电层被图案化为存储栅电极、逻辑栅电极、以及BCD栅电极。
该方法的挑战在于用于形成存储结构的热工艺和氧化工艺可能影响待制造的逻辑和BCD器件。例如,在热工艺和氧化工艺期间使用的氧化剂可穿过BCD栅氧层迁移至逻辑和BCD区域,并且促使逻辑和BCD区域的氧化。这样的氧化部分地消耗逻辑和BCD区域,从而减少逻辑和BCD阱的深度并且改变逻辑阱和BCD阱的掺杂分布。通过改变逻辑阱和BCD阱的掺杂分布,热工艺和氧化工艺导致逻辑和BCD器件性能参数的巨大偏移。热工艺和氧化工艺包括,例如,在超过大约850摄氏度的温度下、和/或在大约850至1000摄氏度之间、大约750至950摄氏度之间、或大约850至1250摄氏度之间的温度下执行的工艺。对于该挑战的解决方法为使用p型金属氧化物半导体(PMOS)一次性可编程(OTP)存储器,因为存储器可不使用热工艺和氧化工艺形成。然而,PMOS OTP存储器为一次性可编程的,因此限制了应用。
鉴于前述,本应用的不同的实施例针对一种使用密封层将NVM器件与逻辑或BCD器件集成的密封方法,以及由该方法形成的集成电路(IC)。根据该方法的一些实施例,隔离结构形成在半导体衬底上。隔离结构使半导体衬底的存储区域与半导体衬底的外围区域分隔。掺杂阱形成在外围区域。密封层形成为覆盖存储和外围区域,并且进一步覆盖掺杂阱。密封层可为诸如介电的和/或可为或包括诸如氮化硅、氧氮化硅、碳化硅、多晶硅(掺杂或未掺杂)、或一些其他适合的密封材料。密封层从存储区域而非从外围区域去除,并且存储单元结构使用热工艺和氧化工艺在存储区域上形成。密封层从外围区域去除,并且逻辑或BCD器件结构在外围区域上形成。
密封层保护包括掺杂阱的外围区域免受用于形成存储单元结构的热工艺和氧化工艺的影响。例如,密封层可阻止在热工艺和氧化工艺期间使用的氧化剂迁移至外围区域并且引起外围区域的氧化和消耗。这样的氧化和消耗减少掺杂阱的深度并且因此改变掺杂阱的掺杂分布。因此,密封层防止掺杂阱的掺杂分布的偏移,这防止了在掺杂阱上形成的逻辑或BCD器件的性能的偏移。这转而促成了IC批量生产的高产量。
参考图1A,提供了包括存储单元102和逻辑或BCD器件104的IC的一些实施例的截面图100A。存储单元102处于IC的第一部分I中,在半导体衬底106的存储区域106m上。进一步地,存储单元102在存储区域106m中覆盖在存储阱108上。存储单元102可为诸如第一代嵌入式超级快闪(ESF1)器件、第三代嵌入式超级快闪(ESF3)器件、1.5晶体管硅氧化氮氧化硅(SONOS)器件、双晶体管SONOS器件、1.5晶体管金属氧化氮氧化硅(MONOS)器件、双晶体管MONOS器件、单晶体管浮栅器件、双晶体管浮栅器件、薄膜存储器(TFS)器件或一些其他适合的存储单元。半导体衬底106可为或包括诸如块状硅衬底、硅外延层、绝缘体上硅衬底(SOI)、一些其他适合的半导体结构或前述的任何组合。在一些实施例中,半导体衬底106包括块状硅衬底(未示出)以及覆盖块状硅衬底的硅外延层(未示出)。
逻辑或BCD器件104处于IC的第二部分II中,在半导体衬底106的逻辑或BCD区域106Lb上。在一些实施例中,半导体衬底106的逻辑或BCD区域106lb处于IC的外围和/或半导体衬底106的存储区域106m的外围。进一步地,逻辑或BCD器件104覆盖在逻辑或BCD区域106lb中的逻辑或BCD阱110上。在一些实施例中,逻辑或BCD阱110具有比存储阱108的顶面高过距离D的顶面。距离D可为诸如大约10至100埃、大约40至60埃、或大约25至75埃。逻辑或BCD器件104可为诸如金属氧化物半导体(MOS)器件、DMOS器件、双极结型晶体管(BJT)、或一些其他适合的逻辑或BCD器件。
相对于彼此和/或相对于半导体衬底106的块体112,存储阱108和逻辑或BCD阱110具有不同的掺杂分布、不同的掺杂浓度、不同的掺杂类型、或前述的任意组合。在一些实施例中,存储阱108具有单一掺杂类型和/或逻辑或BCD阱110具有单一掺杂类型。进一步地,存储阱108和逻辑或BCD阱110由延伸进入半导体衬底106的顶面的隔离结构114环绕。隔离结构114包括一对位于存储阱108的相对两侧上的存储段。类似地,隔离结构114包括一对位于逻辑或BCD阱110的相对两侧上的逻辑或BCD段。隔离结构114可为或包括诸如浅沟槽隔离(STI)结构、深沟槽隔离(DTI)结构、或一些其他适合的隔离结构。
在一些实施例中,伪结构116在半导体衬底106的存储区域106m上,并且邻近存储单元102。在一些实施例中,伪结构116还覆盖隔离结构114的存储段上。伪结构116包括一对位于存储单元102的相对两侧的伪段。在一些实施例中,伪结构116的平面顶部布局以封闭路径沿存储阱108的边界横向延伸,以完全封闭存储阱108,和/或沿封闭路径从伪段中的一者至伪段中的另一者是连续的。封闭路径可诸如为圆环形、正方环形、矩形环形、或一些其他适合的封闭路径形状。注意的是,封闭路径在图1A中的截面图100A之外延伸(例如,进入和离开页面),所以它在图1A的截面图100A中是不可见的。伪结构116由伪密封元件118d和在一些实施例中位于伪密封元件118d之下的伪介电元件120d限定。
在一些实施例中,伪密封元件118d具有大约100至500埃、大约100至250埃、大约250至500埃、大约150至350埃、大约50至150埃、或大约450至550埃的第一厚度T1。在一些实施例中,伪介电元件120d具有大约60至200埃、大约60至130埃、大约130至200埃、大约20至100埃、或大约160至240埃的第二厚度T2。在一些实施例中,第一厚度T1为第二厚度T2的大约0.5至8.5倍、为第二厚度T2的大约0.25至0.75倍、为第二厚度T2的大约8至9倍、为第二厚度T2的大约1至5倍、或为第二厚度T2的大约4至9倍。
如此后所见,在执行用于形成IC的方法的同时,密封层用来保护逻辑或BCD阱110。进一步地,如此后所见,在执行方法的同时密封层大部分去除,并且伪密封元件118d为密封层的残余部分。类似地,如此后所见,伪介电元件为用于形成BCD器件的BCD栅极介电层的介电层的残余部分。伪密封元件118d可为或包括诸如氮化硅、氮氧化硅、碳化硅、一些其他适合的电介质、多晶硅(掺杂的或未掺杂的)、或前述的任意组合。进一步地,伪密封元件118d可为阻止或以其他方式防止氧化剂穿过其中的材料。伪介电元件120d可为诸如氧化硅、一些其他适合的氧化物、高k电介质、一些其他的电介质、或前述的任意组合。如在此使用的,高k电介质可为诸如具有大于大约3.9、5、10、15或20的介电常数的电介质。在一些实施例中,伪密封元件118d为同质的(例如,单一材料)和/或伪介电元件120d为同质的。
层间绝缘(ILD)层122覆盖半导体衬底106、伪结构116、存储单元102、逻辑或BCD器件104、以及隔离结构114。进一步地,接触通孔124延伸穿过ILD层122并且与存储单元102以及逻辑或BCD器件104电连接。ILD层122可为或包括诸如二氧化硅、低k电介质、氮化硅、一些其他适合的电介质、或前述的任意组合。如在此使用的,低k电介质可为诸如具有小于大约3.9、3、2或1的介电常数k的电介质。接触通孔124可为或包括诸如铜、铝铜、铝、钨、一些其他适合的金属、或前述的任意组合。
参考图1B,提供了图1A中的IC的一些其他实施例的截面图100B。如所示出的,图1B为图1A的变型,其中图1A中的伪介电元件120d省略。在一些这样的实施例中,伪密封元件118d直接接触隔离结构114。
参考图2A,提供了图1A中的部分I的一些更详细的实施例的截面图200A。部分I示出了图1A中的部分I的一些更详细的实施例。部分II’示出了图1A中的部分II的一些更详细的BCD实施例。半导体衬底106的BCD区域106b对应于图1A中的逻辑或BCD区域106lb,BCD器件104b对应于图1A中的逻辑或BCD器件104,并且一个或多个BCD阱110b1至110b5对应于图1A中的逻辑或BCD阱110。部分II’示出了图1A中的部分II的一些更详细的逻辑实施例。半导体衬底106的逻辑区域106l对应于图1A中的逻辑或BCD区域106lb,逻辑器件104l对应于图1A中的逻辑或BCD器件104,并且逻辑阱110l对应于图1A中的逻辑或BCD阱110。尽管图2A示出了部分II’以及部分II这两者,然而部分II’或部分II(但不是两者皆有)在其他实施例中可省略。
如图2A中的部分II’所示,逻辑阱110l在半导体衬底106的逻辑区域106l中。相对于半导体衬底106的块体112,逻辑阱110l具有不同的掺杂分布、不同的掺杂浓度、不同的掺杂类型、或前述的任意组合。在一些实施例中,逻辑阱110l具有单一掺杂类型。进一步地,逻辑阱110l由隔离结构114环绕,并且隔离结构114包括一对位于逻辑阱110l相对两侧上的逻辑段。
逻辑器件104I覆在逻辑阱110l上,并且在半导体衬底106的逻辑区域106l上。逻辑器件104l可为诸如金属氧化物半导体场效应晶体管(MOSFET)、一些其他适合的金属氧化物半导体(MOS)器件、绝缘栅场效应晶体管(IGFET)、或一些其他适合的逻辑器件。在一些实施例中,逻辑器件104l包括一对逻辑源极/漏极区域222。为了说明的简化,仅将逻辑源极/漏极区域222中的一个标为222。逻辑源极/漏极区域222分别位于逻辑阱110l的相对两侧,凹陷至逻辑阱110l的顶面内。进一步地,逻辑源极/漏极区域222具有相同的掺杂类型。在一些实施例中,一对逻辑源极/漏极延伸件222e也横向位于逻辑源极/漏极区域222之间且凹陷至逻辑阱110l的顶面内。为了说明的简化,仅将逻辑源极/漏极延伸件222e的一个标为222e。逻辑源极/漏极延伸件222e分别从逻辑源极/漏极区域222延伸,并且与逻辑源极/漏极区域222相比,具有相同的掺杂类型和更小的掺杂浓度。
选择性传导逻辑沟道224在逻辑源极/漏极区域222之间。在一些没有逻辑源极/漏极延伸件222e的实施例中,选择性传导逻辑沟道224从逻辑源极/漏极区域222中的一个不间断地延伸至逻辑源极/漏极区域222中的另一个。在一些具有逻辑源极/漏极延伸件222e的实施例中,选择性传导逻辑沟道224从逻辑源极/漏极延伸件222e中的一个不间断地延伸至逻辑源极/漏极延伸件222e中的另一个。选择性导电逻辑沟道224由逻辑阱110l限定,并且逻辑阱110l具有与逻辑源极/漏极区域222相反的掺杂类型。例如,逻辑源极/漏极区域222可为p型并且逻辑阱110l可为n型,或者反之亦然。
逻辑栅电极226和逻辑栅极介电层228堆叠在选择性导电逻辑沟道224上,并且逻辑栅电极226覆在逻辑栅极介电层228上。逻辑栅极介电层228可为或包括诸如氧化物、高k电介质、一些其他适合的电介质、或前述的任意组合。逻辑栅电极226可为或包括诸如掺杂多晶硅、金属、或一些其他适合的导电材料。
如图2A中的部分II’所示,BCD阱110b1至110b5在半导体衬底106的BCD区域106b中。BCD阱110b1至110b5中的至少一些(例如,全部)中的每个相对于半导体衬底106的主体112具有不同的掺杂分布、不同的掺杂浓度、不同的掺杂类型、或前述的任意组合。进一步地,在一些实施例中,BCD阱110b1至110b5中的至少一些(例如,全部)中的每个具有单一掺杂类型。
在一些实施例中,第一BCD阱110b1和第二BCD阱110b2沿半导体衬底106的顶面位于半导体衬底106的BCD区域106b中。第二BCD阱110b2覆在第一BCD阱110b1上并且定位在第一BCD阱110b1的第一侧。第一BCD阱110b1具有第一掺杂类型,并且第二BCD阱110b2具有与第一掺杂类型相反的第二掺杂类型。在一些实施例中,半导体衬底106的主体112也具有第二掺杂类型。第一和第二掺杂类型可分别为诸如p型和n型,或者反之亦然。进一步地,在一些实施例中,第三BCD阱110b3、第四BCD阱110b4、第五BCD阱110b5、或前述的任意组合在半导体衬底106的BCD区域106b中。
在一些实施例中,第三BCD阱110b3覆在第一BCD阱110b1上并且定位在第一BCD阱110b1的第二侧上,该第二侧与第一BCD阱110b1的第一侧相对。在一些实施例中,第四BCD阱110b4在第一和第二BCD阱110b1、110b2下方,并且还在第三BCD阱110b3(如果存在的话)的下方。第三BCD阱110b3具有第一掺杂类型,并且第四BCD阱110b4具有第二掺杂类型。在一些实施例中,第三BCD阱110b3具有比第一BCD阱110b1高的掺杂浓度。在一些实施例中,第五BCD阱110b5环绕第一和第二BCD阱110b1、110b2,并且进一步环绕第三BCD阱110b3(如果存在的话)和/或第四BCD阱110b4(如果存在的话)。进一步地,第五BCD阱110b5沿半导体衬底106的顶面。第五BCD阱110b5包括一对分别位于第一BCD阱110b1的相对两侧上的阱段,从而第一和第二BCD阱110b1、110b2夹置在该对阱段之间。在一些实施例中,第三BCD阱110b3和/或第四BCD阱110b4也夹置在该对阱段之间。第五BCD阱110b5具有第二掺杂类型。
在一些实施例中,掩埋半导体层230在BCD阱110b1至110b5下、和/或隔离结构114环绕和/或分隔BCD阱110b1至110b5。在一些实施例中,掩埋半导体层230具有第一掺杂类型。在一些实施例中,隔离结构114环绕第一和第二BCD阱110b1、110b2,并且进一步环绕第三BCD阱110b3(如果存在的话)和/或第四BCD阱110b4(如果存在的话)。例如,隔离结构114可包括三个BCD段,为了说明的简化仅将其中的一些标为114。三个BCD段中的第一BCD段和三个BCD段中的第二BCD段可分别位于第一BCD阱110b1的相对两侧上。第一BCD段可将第二BCD阱110b2与第五BCD阱110b5分隔,并且第二BCD段可将第三BCD阱110b3与第五BCD阱110b5分隔。进一步地,三个BCD段中的第三BCD段可在第一和第二BCD段之间,并且可进一步将第一BCD阱110b1与第三BCD阱110b3分隔。
BCD器件104b覆在BCD阱110b1至110b5上且在半导体衬底106的BCD区域106b上。BCD器件104b可为诸如横向扩散MOS(LDMOS)器件、一些其他适合的MOS器件、一些其他适合的DMOS器件、BJT、或一些其他适合的BCD器件。进一步地,BCD器件104b可被配置为在高于大约50、100、200或500伏的高电压下操作。
在一些实施例中,BCD器件104b包括一对BCD源极/漏极区域232。为了说明的简化,仅将BCD源极/漏极区域232中的一个标为232。BCD源极/漏极区域232覆在第一BCD阱110b1上,并且分别在第一BCD阱110b1的相对两侧,并且凹陷在半导体衬底106的顶面内。BCD源极/漏极区域232中的第一BCD源极/漏极区域进一步覆在第二BCD阱110b2上,并且BCD源极/漏极区域232中的第二BCD源极/漏极区域进一步覆在第三BCD阱110b3上(如果存在的话)。在一些实施例中,第一BCD源极/漏极区域还覆在半导体衬底106的主体阱234上,阱234覆在第二BCD阱110b2上。主体阱234具有第二掺杂类型并且可诸如具有与第二BCD阱110b2不同的掺杂浓度。BCD源极/漏极区域232具有相同的掺杂类型并且进一步具有第一掺杂类型。进一步地,在一些实施例中,BCD源极/漏极区域延伸件232e覆在第二BCD阱110b2和主体阱234(如果存在的话)上。BCD源极/漏极区域延伸件232e相比BCD源极/漏极区域232具有相同的掺杂类型和较低的掺杂浓度。
选择性导电BCD沟道236在第一BCD源极/漏极区域和第一BCD阱110b1之间,并且由第二BCD阱110b2限定。在没有BCD源极/漏极区域延伸件232e的一些实施例中,选择性导电BCD沟道236从第一BCD源极/漏极区域不间断延伸至第一BCD阱110b1。在具有BCD源极/漏极区域延伸件232e的一些实施例中,选择性导电BCD沟道236从BCD源极/漏极区域延伸件232e不间断延伸至第一BCD阱110b1。第一BCD阱110b1和第三BCD阱110b3(如果存在的话)作为用于BCD器件104b的漂移区域。漂移区域提供从选择性导电BCD沟道236至第二BCD源极/漏极区域的传导路径,并且尽管漂移区域为传导的,具有比选择性导电BCD沟道236的导通(ON)电阻更高的电阻以使得BCD器件104b在高电压下操作。漂移区域具有第一掺杂类型。
BCD栅电极238和一个或多个BCD栅极介电层240a至240c堆叠在选择性导电BCD沟道236上,并且BCD栅电极238覆在BCD栅极介电层240a至240c上。例如,第一BCD栅极介电层240a覆在第二BCD栅极介电层240b上,第二BCD栅极介电层240b覆在第三BCD栅极介电层240c上,并且第三BCD栅极介电层240c覆在选择性导电BCD沟道236上。在一些实施例中,第二BCD栅极介电层240b具有伪介电元件120d的第二厚度T2。BCD栅极介电层240a至240c可为或包括诸如氧化物、高k电介质、一些其他适合的电介质、或前述的任意组合。BCD栅电极238可为或包括诸如掺杂多晶硅、金属、或一些其他适合的导电材料。
如图2A中的部分I所示,存储阱108在半导体衬底106的存储区域106m中。存储阱108相对半导体衬底106的主体112具有不同的掺杂分布、不同的掺杂浓度、不同的掺杂类型、或前述的任意组合。进一步地,存储阱108由隔离结构114环绕。在一些实施例中,存储阱108的顶面比逻辑阱110l的顶面、BCD阱110b1至110b5的顶面、半导体衬底106的主体112的顶面、或前述任意的组合低了距离D。距离D可为诸如大约10至100埃、大约40至60埃、或大约25至75埃。
存储单元102覆在存储阱108上且在半导体衬底106的尺寸区域106m上。在一些实施例中,存储单元包括一对存储源极/漏极区域202。为了说明的简化,仅将存储源极/漏极区域202中的一个标为202。存储源极/漏极区域202分别位于存储阱108的相对两侧,并且凹陷于存储阱108的顶面内。进一步地,存储源极/漏极区域202具有相同的掺杂类型。在一些实施例中,一对存储源极/漏极延伸件202e也横向位于存储源极/漏极区域202之间且凹陷于存储阱108的顶面内。为了说明的简化,仅将存储源极/漏极延伸件202e中的一个标为202e。存储源极/漏极延伸件202e分别从存储源极/漏极区域202延伸,并且与存储源极/漏极区域202具有相同的掺杂类型和更低的掺杂浓度。
选择性导电存储沟道204在存储源极/漏极区域202之间。在一些没有存储源极/漏极延伸件202e的实施例中,选择性导电存储沟道204从存储源极/漏极区域202中的一个不间断延伸至存储源极/漏极区域202中的另一个。在一些具有存储源极/漏极延伸件202e的实施例中,选择性导电存储沟道204从存储源极/漏极延伸件202e中的一个不间断延伸至存储源极/漏极延伸件202e中的另一个。进一步地,选择性导电存储沟道204由存储阱108限定,并且存储阱108具有与存储源极/漏极区域202相反的掺杂类型。例如,存储源极/漏极区域202可为p型并且存储阱108可为n型,或者反之亦然。
浮栅硬掩模206、浮栅电极208、以及浮栅介电层210堆叠在选择性导电存储沟道204上。浮栅硬掩模206覆在浮栅电极208上,并且浮栅电极208覆在浮栅介电层210上。浮栅硬掩模206和浮栅介电层210可为或包括诸如氧化物、一些其他适合的电介质、或前述的任意组合。在一些实施例中,浮栅介电层210具有大约50至400埃、大约75至125埃、大约50至200埃、或大约200至400埃的第三厚度T3。在一些实施例中,第三厚度为距离D的大约1.5至2.5倍、为距离D的大约1.75至2.25倍、为距离D的大约1.9至2.1倍、或为距离D的大约2倍。浮栅电极208可为或包括诸如掺杂多晶硅或一些其他适合的导电材料。
第一选择栅极介电层214覆在选择性导电存储沟道204上直至浮栅电极208的两侧,并且包括分别衬垫在浮栅电极208的相对侧壁上的一对选择栅极介电段。为了说明的简化,仅将选择栅极介电段中的一个标为214。另外,选择栅极介电段衬垫在浮栅介电层210的相对侧壁上,浮栅介电层210的相对侧壁分别与浮栅电极208的相对侧壁持平,并且选择栅极介电段从浮栅介电层210的相对侧壁分别朝向存储源极/漏极区域202延伸。第一选择栅极介电层214可为或包括诸如氧化硅、高k电介质、一些其他适合的电介质、或前述的任意组合。
选择栅电极216覆在第一选择栅极介电层214和选择性导电存储沟道204上,并且进一步覆在浮栅硬掩模206上。进一步地,存储侧壁间隔件218以及在一些实施例中的第二选择栅极介电层220位于第一选择栅极介电层214与选择栅电极216之间且覆在第一选择栅极介电层214上。存储侧壁间隔件218包括一对存储间隔件段,该对存储间隔件段分别衬垫在位于浮栅电极208相对两侧的第一选择栅极介电层214的侧壁上。为了说明的简化,仅将存储侧壁间隔件段中的一个标为218。第二选择栅极介电层220进一步覆在存储侧壁间隔件218和浮栅硬掩模206上。选择栅电极216可为或包括诸如掺杂多晶硅、金属、或一些其他适合的导电材料。第二选择栅极介电层220可为或包括诸如氧化硅、高k电介质、一些其他适合的电介质、或前述的任意组合。存储侧壁间隔件218可为或包括诸如氧化硅、氮化硅、氮氧化硅、一些其他适合的电介质、或前述的任意组合。
伪结构116在半导体衬底106的存储区域106m上且邻近存储单元102。伪结构116由伪密封元件118d和在一些实施例中的在伪密封元件118d下的伪介电元件120d限定。伪密封元件118d包括一对分别位于存储单元102的相对两侧上的伪密封段。进一步地,伪介电元件120d包括一对分别位于存储器件的相对两侧以及分别在伪密封段下的伪介电段。为了说明的简化,仅将伪密封段中的一个标为118d,并且仅将伪介电段中的一个标为120d。
主侧壁间隔件242衬垫在存储单元102、伪结构116、逻辑器件104l、以及BCD器件104b的侧壁上。为了说明的简化,仅将主侧壁间隔件242中的一些段标为242。进一步地,ILD层122覆盖半导体衬底106、主侧壁间隔件242、伪结构116、存储单元102、逻辑器件104l、BCD器件104b、以及隔离结构114。再进一步地,接触通孔124延伸穿过ILD层122并且与存储单元102、逻辑器件104l、以及BCD器件104b电连接。为了说明的简化,仅将接触通孔124中的一些标为124。主侧壁间隔件242可为或包括诸如氮化硅、氧化硅、氮氧化硅、一些其他适合的电介质、或前述的任意组合。
参考图2B,提供了图1B中的IC的一些更详细的实施例的截面图200B。如所示的,图2B为图2A的变型,其中图2A中的伪介电元件120d省略。在一些这样的实施例中,伪密封元件118d直接接触隔离结构114。进一步地,第三选择栅极介电层144将第二选择栅极介电层220与第一选择栅极介电层214隔离,和/或图2A中的第三BCD栅极介电层240c省略。第三选择栅极介电层244可为或包括诸如氧化硅、一些其他适合的电介质、或前述的任意组合。
参考图3至图23,提供了一种形成包括存储单元和BCD或逻辑器件的IC的密封方法的一些实施例的截面图300至2300。密封方法关于ESF1器件示出,然而应当理解的是,密封方法可应用于其他类型的存储器件,诸如SONOS器件、MONOS器件、ESF3器件、或其他适合类型的NVM器件。进一步地,该密封方法诸如可执行来形成图2A中的IC。
如图3中的截面图300所示,提供了半导体衬底106。半导体衬底106包括存储区域106m,BCD区域106b,以及逻辑区域106l。存储区域106m位于待制造的IC的部分I中。BCD区域106b位于待制造的IC的部分II’中。逻辑区域106l位于待制造的IC的部分II’中。半导体衬底106可为或包括块状硅衬底、硅外延层、SOI衬底、III-V族元素半导体衬底、一些其他适合的半导体结构、或前述的任意组合。在一些实施例中,掩埋半导体层230掩埋在半导体衬底106中并且定位在BCD区域106b。进一步地,在一些实施例中,掩埋半导体层230具有第一掺杂类型并且半导体层106的主体112具有与第一掺杂类型相反的第二掺杂类型。第一掺杂类型极耳第二掺杂类型可分别为n型和p型,或者反之亦然。
由图3中的截面图300同样示出的,隔离结构114形成在半导体层106中以将半导体衬底106的存储区域106m、半导体衬底106的BCD区域106b、半导体衬底106的逻辑区域106l划分开。此外,隔离结构114将半导体衬底106的存储区域106m、半导体衬底106的BCD区域106b、半导体衬底106的逻辑区域106l与周围的环境电隔离,反之亦然。为了说明的简化,仅将隔离结构114的一些段标为114。隔离结构114可为诸如STI结构、DTI结构、或一些其他适合类型的隔离结构。
在一些实施例中,用于形成隔离结构114的工艺包括形成覆盖半导体衬底106的下部衬垫层302,并且进一步形成覆盖下部衬垫层302的上部衬垫层304。下部衬垫层302可为或包括诸如二氧化硅、一些其他适合的氧化物、或一些其他适合的电介质。上部衬垫层304可为或包括诸如氮化硅、一些其他适合的氮化物、或一些其他适合的电介质。进一步地,下部衬垫层302和上部衬垫层304可由诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、一些其他适合的增长或沉积工艺、或前述的任意组合形成。在形成下部衬垫层302和上部衬垫层304之后,下部衬垫层302和上部衬垫层304被图案化为具有隔离结构114的布局,并且随后在存在下部衬垫层302和上部衬垫层304的情况下,对半导体衬底106执行蚀刻以在半导体衬底106中限定具有隔离结构114的布局的沟槽。沟槽介电层形成为覆盖上部衬垫层304并且填充沟槽。进一步地,对沟槽介电层执行平坦化直至达到上部衬垫层304,以此由沟槽介电层形成隔离结构114。下部衬垫层302和上部衬垫层304可诸如由光刻/蚀刻工艺或一些其他适合的图案化工艺图案化。沟槽介电层可诸如由诸如CVD、PCD、溅射、或一些其他适合的沉积工艺形成。平坦化可诸如由化学机械抛光(CMP)或一些其他适合的平坦化工艺执行。
如图4中的截面图400所示,上部衬垫层(图3中可见)从半导体衬底106的存储区域106m、BCD区域106b、以及逻辑区域106l去除。该去除可诸如由平坦化、蚀刻工艺、或一些其他适合的去除工艺执行。平坦化可诸如由CMP或一些其他适合的平坦化工艺执行。
由图4中的截面图400同样示出的,一个或多个BCD阱110b1至110b5形成在半导体衬底106的BCD区域106b中。在一些实施例中,第一BCD阱110b1和第二BCD阱110b2沿半导体衬底106的顶面形成在半导体衬底106的BCD区域106b中。第二BCD阱110b2覆在第一BCD阱110b1上并且定位在第一BCD阱110b1的第一侧上。第一BCD阱110b1具有第一掺杂类型,并且第二BCD阱110b2具有与第一掺杂类型相反的第二掺杂类型。在一些实施例中,第三BCD阱110b3、第四BCD阱110b4、以及第五BCD阱也形成在半导体衬底106的BCD区域106b中。第三BCD阱110b3覆在第一BCD阱110b1上并且沿半导体衬底106的顶面。进一步地,第三BCD阱110b3定位在第一BCD阱110b1的第二侧上,并且具有第一掺杂类型,该第二侧与第一BCD阱110b1的第一侧相对。第四BCD阱110b4在第一BCD阱110b1、第二BCD阱110b2、第三BCD阱110b3下并且具有第二掺杂类型。第五BCD阱110b5环绕第一BCD阱110b1、第二BCD阱110b2、第三BCD阱110b3、以及第四BCD阱110b4并且沿半导体衬底106的顶面。进一步地,第五BCD阱110b5包括一对分别位于第一BCD阱110b1相对两侧上的阱段并且具有第二掺杂类型。
在一些实施例中,用于形成BCD阱100b1至110b5的工艺包括重复执行选择性掺杂工艺以循序形成BCD阱100b1至110b5。在一些实施例中,选择性掺杂工艺循序包括:将光刻层沉积在下部衬垫层302上;图案化光刻层使得BCD阱的布局形成;在图案化的光刻层存在的情况下将掺杂剂注入半导体衬底106的BCD区域106b;以及去除图案化的光刻层。如在此使用的,光刻层的沉积可诸如由旋涂或一些其他适合的沉积工艺上来执行。如在此使用的,光刻层的图案化可诸如由光刻工艺或一些其他适合的图案化工艺来执行。如在此使用的,掺杂剂的注入可诸如由离子注入或一些其他适合的掺杂工艺来执行。如在此使用的,光刻层的益处可诸如由等离子灰化或一些其他适合的去除工艺来执行。
如图5中的截面图500所示,逻辑阱110l形成在半导体衬底106的逻辑区106l中。在一些实施例中,逻辑阱110l以与半导体衬底106的主体112相反的掺杂类型形成。在一些实施例中,一种用于形成逻辑阱110l的工艺循序包括:将光刻层沉积在下部衬垫层302上;将光刻层图案化为具有逻辑阱110l的布局;在图案化光刻层存在的情况下,将掺杂剂注入至半导体衬底的逻辑区域106l;以及循序去除图案化光刻层。沉积、图案化、注入、去除或前述的任意组合可诸如关于图4描述。
如图6中的截面图600所示,第一栅极介电层120形成为覆盖半导体衬底106的存储区域106m、BCD区域106b以及逻辑区域106l。进一步地,密封层118形成为覆盖第一栅极介电层120。第一栅极介电层120可为或包括诸如氧化硅、一些其他适合的氧化物、一些其他适合的电介质、或前述的任意组合。密封层118为在随后的工艺期间使用的氧化剂的阻挡层,并且可为或包括诸如氮化硅、氮氧化硅、碳化硅、一些其他适合的电介质、多晶硅(掺杂或未掺杂)、一些其他适合的密封材料、或前述的任意组合。在一些实施例中,第一栅极介电层120和密封层118通过CVD、PVD、热氧化、一些其他适合的沉积工艺、或前述的任意组合形成。
在一些实施例中,密封层118具有大约100至500埃、大约100至250埃、大约250至500埃、大约150至350埃、大约50至150埃、或大约450至550埃的第一厚度T1。在一些实施例中,第一栅极介电层120具有大约60至200埃、大约60至130埃、大约130至200埃、大约20至100埃、或大约160至240埃的第二厚度T2。在一些实施例中,第一厚度T1为第二厚度T2的大约0.5至8.5倍、为第二厚度T2的大约0.25至0.75倍、为第二厚度T2的大约8至9倍、为第二厚度T2的大约1至5倍、为第二厚度T2的大约4至9倍。在一些实施例中,第一厚度T1对于封层118足够大(例如,大约大约100埃或一些其他适合的厚度值),以保护(例如,完全保护)逻辑区域106l和BCD区域106b免受热工艺和氧化工艺的损害。注意的是,随后解释这种保护。在一些实施例中,第一厚度T1足够小(例如,小于大约500埃或一些其他适合的厚度值),因此封封层118可高效率形成并且用于形成封层118的成本可较低。
如图7中的截面图700所示,图案化密封层118以在半导体106的存储区域106m上形成覆在第一栅极介电层120上的第一器件开口702。密封层118的图案化可诸如由光刻/蚀刻工艺或一些其他适合的图案化工艺来执行。在一些实施例中,光刻/蚀刻工艺包括:在密封层118上沉积第一光刻层704;将第一光刻层704图案化为具有第一器件开口702的图案;穿过第一光刻层704执行蚀刻进入密封层118以将图案化转印至密封层118、并且去除第一光刻层704。
同样由图7中的截面图700示出的,存储阱108形成在半导体衬底106的存储区域106m中。在一些实施例中,存储阱108形成为具有与半导体衬底106的主体112相反的掺杂类型。进一步地,在一些实施例中,用于形成存储阱108的工艺包括穿过第一器件开口702的离子注入或一些其他适合的掺杂工艺。
如图8中的截面图800所示,对第一栅极介电层120和下部衬垫层302执行第一蚀刻。第一蚀刻将密封层118用作掩模,并且因此将封层118的图案化转印至第一栅极介电层120和下部衬垫层302。进一步地,第一蚀刻停止在半导体衬底106上,并且扩展第一器件开口702以暴露存储阱108。
在一些实施例中,尽管未示出,B清洁工艺在第一蚀刻之后执行。在一些实施例中,B清洁工艺包括:对第一器件开口702施加硫酸/过氧化氢/去离子水的混合物;对第一器件开口702施加盐酸/去离子水的混合物;对第一器件开口702施加氢氧化铵/过氧化氢/去离子水的混合物;对第一器件开口702施加盐酸/过氧化氢/去离子水的混合物。硫酸/过氧化氢/去离子水可诸如去除第一器件开口702中的有机残留物。盐酸/去离子水的混合物可诸如去除第一器件开口702中的自然氧化层。盐酸/过氧化氢/去离子水的混合物可诸如去除第一器件开口702中的有机残留和/或颗粒。硫酸/过氧化氢/去离子水的混合物可诸如去除第一器件开口702中的有机金属离子。在一些实施例中,以如上的顺序,对第一器件开口702循序施加四种混合物。
如图9中的截面图900所示的,第二栅极介电层902形成在密封层118上方且覆盖半导体衬底106的存储区域106m、BCD区域106b和逻辑区域106l。进一步地,第二栅极介电层902形成为衬垫第一器件开口702(图8可见)。在一些实施例中,第二栅极介电层902为或包括二氧化硅、一些其他适合的氧化物、或一些其他适合的电介质。在一些实施例中,第二栅极介电层902通过共形沉积形成、和/或通过热氧化、CVD、PVD、或一些其他适合的沉积或生长工艺形成。
在第二栅极介电层902通过热氧化形成的一些实施例中,存储阱106m通过氧化被部分消耗,从而存储阱106m的顶面相对于BCD阱110b1至110b5的顶面、逻辑阱110l的顶面、半导体衬底106的主体112的顶面、或前述的任意组合凹陷了距离D。如果缺少密封层118的话,BCD阱110b1至110b5的顶面、逻辑阱110l的顶面、半导体衬底106的主体112的顶面同样也会凹陷,因为密封层118在热氧化期间防止BCD阱110b1至110b5、逻辑阱110l、以及半导体衬底106的主体112受到氧化。距离D可为诸如大约10至100埃、大约40至60埃、或大约25至75埃。
进一步地,在第二栅极介电层902通过热氧化形成的一些实施例中,第二栅极介电层902在存储阱106m上比在密封层118上更快地形成,从而第二栅极介电层902在存储阱106m上具有第三厚度T3以及在密封层118上具有小于第三厚度T3的第四厚度T4。例如,在密封层119为氮化硅并且存储阱106m为单晶硅的情况下,第二栅极介电层902的热氧化在密封层118的氮化硅上比在存储阱106m的单晶硅上形成的更慢。第三厚度T3可为诸如大约50至400埃、大约75至125埃、大约50至200埃、或大约200至400埃。进一步地,第三厚度T3可为距离D的大约1.5至2.5倍、为距离D的大约1.75至2.25倍、为距离D的大约1.9至2.1倍、为距离D的大约2倍。
同样由图9中的截面图900示出的,第一栅电极层904形成为覆盖第二栅极介电层902,并且盖层906形成为覆盖第一栅电极层904。第一栅电极层904可为或包括诸如掺杂多晶硅或一些其他适合的导电材料,和/或盖层906可为或包括诸如氮化硅、一些其他适合的氮化物、或一些其他适合的电介质。在一些实施例中,盖层906与密封层118材料相同。在一些实施例中,用于形成第一栅电极层904的工艺包括沉积第一栅电极层904、以及循序掺杂和退火第一栅电极层904。第一栅电极层904的沉积可诸如由CVD、PVD、或一些其他适合的沉积工艺执行。第一栅电极层904的掺杂可诸如由离子注入或一些其他适合的掺杂工艺执行。盖层906可诸如通过CVD、PVD、或一些其他适合的沉积工艺形成。
如图10中的截面图1000所示,图案化盖层906以在半导体衬底106的存储区域106m上形成上覆第一栅电极层904的硬掩模开口1002。盖层906的图案化可诸如通过光刻/蚀刻工艺或一些其他适合的图案化工艺来执行。在一些实施例中,光刻/蚀刻工艺包括:在盖层906上沉积第二光刻层1004;利用硬掩模开口1002的图案来图案化第二光刻层1004;穿过第二光刻层1004对盖层906执行蚀刻以将图案转印至盖层906;以及去除第二光刻层1004。
如图11中的截面图1100所示,浮栅硬掩模206在硬掩模开口1002(图10中可见)中形成。浮栅硬掩模206可为或包括氧化硅、一些其他适合的氧化物、或一些其他适合的电介质。进一步地,浮栅硬掩模206可为或包括诸如与第二栅极介电层902相同的材料。在一些实施例中,通过热氧化第一栅电极层904在硬掩模开口1002中的部分来形成浮栅硬掩模206。在其他实施例中,浮栅硬掩模206通过一些其他适合的生长或沉积工艺形成。进一步地,在一些实施例中,浮栅硬掩模206的形成消耗了浮栅硬掩模206在硬掩模开口1002中的部分。
如图12中的截面图1200所示,对盖层906(图11中可见)执行第二蚀刻以去除封盖层906。在一些实施例中,第二蚀刻将第一栅电极层904用作蚀刻停止层。进一步地,在一些实施例中,第二蚀刻使用的蚀刻剂对于盖层906具有的蚀刻速率比对于第一栅电极层904具有的蚀刻速率和/或对于浮栅硬掩模206具有的蚀刻速率更高(例如,10、20、50或100倍的)。
同样通过图12中的截面图1200示出的,在浮栅硬掩模206存在的情况下对第一栅电极层904执行第三蚀刻(图11可见)以形成在浮栅硬掩模206下的浮栅电极208。第三蚀刻诸如还可部分清洗第一器件开口702。在一些实施例中,第三蚀刻将第二栅电极层902用作蚀刻停止层。进一步地,在一些实施例中,第三蚀刻使用的蚀刻剂对于第一栅电极层904具有的蚀刻速率比对于浮栅硬掩模206具有的蚀刻速率和/或对于第二栅电极层902具有的蚀刻速率更高(例如,10、20、50或100倍的)。
如图13中的截面图1300所示,对第二栅电极层902(图12可见)执行第四蚀刻以形成在浮栅电极208下的浮栅介电层210。第四蚀刻可诸如还清洗第一器件开口702。浮栅硬掩模206和浮栅电极208用作第四蚀刻的掩模,并且在一些实施例中,半导体衬底106用作第四蚀刻的蚀刻停止层。在一些实施例中,第四蚀刻作为第一器件开口702的B清洗工艺的部分执行。B清洗工艺的实例如上文中在图8的步骤和图9的步骤之间描述。
同样通过图13中的截面图1300示出的,第三栅极介电层1302形成为覆盖半导体衬底106的BCD区域106b和逻辑区域106l。进一步地,第三栅极介电层1302形成为衬垫第一器件开口702,并且形成为衬垫浮栅电极208的侧壁和浮栅介电层210的侧壁。在一些实施例中,第三栅极介电层1302为或包括氧化硅、高温氧化物(HTO)、一些其他适合的氧化物、或一些其他适合的电介质。进一步地,在一些实施例中,第三栅极介电层1302通过热氧化或一些其他适合的沉积工艺形成。在第三栅极介电层1302通过热氧化工艺形成并且浮栅硬掩模206是或包括氧化物的情况下,第三栅极介电层1302可诸如最低限度地在浮栅硬掩模206上形成(如果存在的话)。
如图14中的截面图1400所示,存储侧壁间隔件210形成为衬垫第三栅极介电层1302的邻接浮栅电极208的浮栅侧壁,并且进一步地形成为上覆第三栅极介电层1302。存储侧壁间隔件包括一对分别位于浮栅电极208的相对两侧上的段部,并且可为或包括诸如氮化硅、氧化硅、氮氧化硅、一些其他适合的电介质、或前述的任意组合。
在一些实施例中,用于形成存储侧壁间隔件218的工艺包括:沉积覆盖图13中的结构的存储间隔件层;以及随后对存储间隔件层执行回蚀。回蚀沿第三栅极介电层1302的浮栅侧壁去除存储间隔件层的水平段而不去除存储间隔件层的垂直段。这些垂直段限定存储侧壁间隔件218。进一步地,在一些实施例中,回蚀沿第三栅极介电层1302的其他侧壁去除存储间隔件层的垂直段。这可能是诸如由于回蚀的长蚀刻时间,并且由于沿第三栅极介电层1302的浮栅侧壁的垂直段具有比沿第三栅极介电层1302的其他侧壁的垂直段更高的高度。沉积可诸如通过共形沉积执行,和/或可通过CVD、PCD、一些其他适合的沉积工艺、或前述的任意组合来执行。第三栅极介电层1302可诸如作为用于回蚀的蚀刻停止层。
如图15中的截面图1500所示,图案化第三栅极介电层1302(图14中可见)和密封层118(图14中可见)以从半导体衬底106的逻辑区域106l和BCD区域106b去除第三栅极介电层1302和密封层118。进一步地,图案化在半导体衬底106的存储区域106m上形成第一选择栅极介电层214和伪密封元件118d。图案化可诸如通过光刻/蚀刻工艺或一些其他适合的图案化工艺来执行。在一些实施例中,光刻/蚀刻工艺包括:在第三栅极介电层1302上沉积第三光刻层1502;将第三光刻胶层1502图案化为具有第一选择栅极介电层214的图案;在第三光刻层1502存在的情况下对第三栅极介电层1302和密封层118执行蚀刻以将图案转印至第三栅极介电层1302和密封层118;以及去除第三光刻层1502。蚀刻可诸如为等离子蚀刻或一些其他适合的蚀刻。
在图7至图14的步骤期间,可执行热工艺和氧化工艺。热工艺和氧化工艺可包括诸如热氧化以形成第二栅极介电层902(图9可见)、热氧化以形成浮栅硬掩模206(图11可见)、热氧化以形成第三栅极介电层1302(图13可见)、对第一栅电极层904(图9可见)退火、其他适合的热工艺和/或氧化工艺、或前述的任意组合。进一步地,至少一些热工艺和氧化工艺可诸如在大约800摄氏度至1200摄氏度(℃)之间、大约900℃至1000℃之间、或大约700℃至900℃之间的高温下执行。密封层118(图7至图14可见)保护半导体衬底106的逻辑区域106l和BCD区域106b免受热工艺和氧化工艺的损坏。例如,密封层118可阻止在热工艺和氧化工艺期间使用的氧化剂迁移至半导体衬底106的逻辑区域106l和BCD区域106b。在没有密封层118的话,氧化剂会导致半导体衬底106的逻辑区域106l和BCD区域106b的氧化和消耗,这使逻辑阱110l和BCD阱110b1至110b5变浅并且因此分别改变逻辑阱110l和BCD阱110b1至110b5的掺杂分布。掺杂分布的这种改变转而导致逻辑阱110l和BCD阱110b1至110b5上的待制造的逻辑和BCD器件的低产并且操作参数改变。因此,密封层118还使得待制造的逻辑和BCD器件的高产并且防止逻辑和BCD器件的参数的偏移。
同样通过图16中的截面图1600示出的,图案化第一栅极介电层120和下部衬垫层302以形成上覆以及暴露逻辑阱110l的第二器件开口1602。第一栅极介电层120和下部衬垫层320的图案化可诸如通过光刻/蚀刻工艺或一些其他适合的图案化工艺来执行。在一些实施例中,光刻/蚀刻工艺包括:在第一栅极介电层120上沉积第四光刻层1604;将第四光刻层1604图案化为具有第二器件开口1602的图案;穿过第四光刻层1604对第一栅极介电层120和下部衬垫层302执行蚀刻以将图案转印至第一栅极介电层120和下部衬垫层302;以及去除第四光刻层1604。
如图17中的截面图所示,第四栅极介电层1702形成为覆盖半导体衬底106的存储区域106m、BCD区域106b以及逻辑区域106l,并且进一步衬垫第二器件开口1602(图16可见)。在一些实施例中,第四栅极介电层1702为或包括氧化物、一些其他适合的氧化物、高k电介质、一些其他适合的电介质、或前述的任意组合。进一步地,在一些实施例中,第四栅极介电层1702通过CVD、PVD、或一些其他适合的沉积工艺形成。
同样通过图17中的截面图1700示出的,第二栅电极层1704形成为覆盖第四栅极介电层1702。第二栅电极层1704可为或包括诸如掺杂多晶硅、金属、或一些其他适合的导电材料。在一些实施例中,用于形成第二栅电极层1704的工艺包括通过诸如CVD、PVD、化学镀、电镀或一些其他适合的沉积或电镀工艺沉积第二栅电极层1704。进一步地,在第二栅电极层1704为或包括多晶硅的一些实施例中,掺杂剂添加到第二栅电极层1704。掺杂剂可通过离子注入或一些其他适合的掺杂工艺添加到第二栅电极层1704。
如图18中的截面图1800所示,图案化第二栅电极层1704(图17可见)、第四栅极介电层1702(图17中可见)、第一栅极介电层120(图17中可见)、下部衬垫层302(图17中可见)、以及第一选择栅极介电层214。该图案化形成堆叠在逻辑阱110l上的逻辑栅电极226以及逻辑栅极介电层228,从而逻辑栅电极226覆在逻辑栅极介电层228上。逻辑栅电极226可诸如由第二栅电极层1704形成,和/或逻辑栅极介电层228可诸如由第四栅极介电层1702形成。进一步地,该图案化形成BCD栅电极238以及堆叠在BCD阱110b1至110b5上的多个BCD栅极介电层240a至240c。第一BCD栅极介电层240a位于BCD栅电极238之下并且可诸如由第四栅极介电层1702形成。第二BCD栅极介电层240b位于第一BCD栅极介电层240a之下并且可诸如由第一栅极介电层120形成。第三BCD栅极介电层240c位于第二BCD栅极介电层240b之下并且可诸如由下部衬垫层302形成。进一步地,该图案化形成彼此堆叠并且覆盖第一选择栅极介电层214、存储侧壁间隔件218、以及浮栅硬掩模206的选择栅电极216以及第二选择栅极介电层220。第二选择栅电极216上覆第二选择栅极介电层220并且可诸如由第二栅电极层1704形成。第二选择栅极介电层220可诸如由第四栅极介电层1702形成。进一步地,该图案化形成位于伪密封元件118d之下并且包括一对分别位于存储阱108的相对两侧的伪介电段的伪介电元件120d。伪介电元件120d可诸如由第一栅极介电层120形成。
该图案化可诸如通过光刻/蚀刻工艺或一些其他适合的图案化工艺来执行。在一些实施例中,光刻/蚀刻工艺包括:在第二栅电极层1704上沉积第五光刻层1802;利用图案来图案化第五光刻层1802;在第五光刻层1802存在的情况下对第二栅电极层1704、第四栅极介电层1702、第一栅极介电层120、下部衬垫层302、以及第一选择栅极介电层214执行蚀刻以将图案转印至第二栅电极层1704、第四栅极介电层1702、第一栅极介电层120、下部衬垫层302、以及第一选择栅极介电层214;以及去除第五光刻层1802。在一些实施例中,在执行蚀刻的同时伪密封元件118d还作为硬掩模。
如图19中的截面图1900所示,图案化BCD栅电极238以及多个BCD栅极介电层240a至240c。该图案化露出第二BCD阱110b2在第二BCD阱110b2的第一侧上的第一部分,而使第二BCD阱110b2在第二BCD阱110b2的第二侧上的第二部分仍由BCD栅电极238覆盖,第一侧与第二侧相对。该图案化可诸如通过光刻/蚀刻工艺或一些其他适合的图案化工艺执行。在一些实施例中,光刻/蚀刻工艺包括:在图18中的结构上沉积第六光刻层1902;将第六光刻层1902图案化为具有图案;在第六光刻层1902存在的情况下对BCD栅电极238以及多个BCD栅极介电层240a至240c执行蚀刻以将图案转印至BCD栅电极238和多个BCD栅极介电层240a至240c;以及去除第六光刻层1902。
同样通过图19中的截面图1900示出的,在第二BCD阱110b2的第一侧上形成覆盖第二BCD阱110b2的主体阱234。在一些实施例中,主体阱234形成为具有与第二BCD阱110b2相同的掺杂类型但不同的掺杂浓度。进一步地,在一些实施例中,主体阱234通过选择掺杂工艺或一些其他适合的掺杂工艺形成。在一些实施例中,选择掺杂工艺包括穿过第六光刻层1902将掺杂剂注入半导体衬底106内。掺杂剂的注入可诸如通过离子注入或一些其他适合的掺杂工艺执行。
如图20中的截面图2000所示,一对存储源极/漏极延伸件202e、BCD源极/漏极延伸件232e、以及一对逻辑源极/漏极延伸件222e分别形成为上覆存储阱108、主体阱234以及逻辑阱110l。为了说明的简化,仅将存储源极/漏极延伸件202e中的一个标为202e。存储源极/漏极延伸件202e分别位于存储阱108的相对两侧,从而选择栅电极216和浮栅电极208夹置在存储源极/漏极延伸件202e之间。存储源极/漏极延伸件202e可诸如具有与存储阱108相反的掺杂类型。BCD源极/漏极延伸件232e可诸如具有与第一BCD阱110b1相同的掺杂类型。逻辑源极/漏极延伸件222e分别位于逻辑阱110l的相对两侧,从而逻辑栅电极226夹置在逻辑源极/漏极延伸件222e之间。逻辑源极/漏极延伸件222e可诸如具有与逻辑阱110l相反的掺杂类型。
在一些实施例中,用于形成存储源极/漏极延伸件202e、BCD源极/漏极延伸件232e、以及逻辑源极/漏极延伸件222e的工艺包括重复执行选择掺杂工艺。例如,可执行第一选择掺杂工艺以形成存储源极/漏极延伸件202e,随后执行第二选择掺杂工艺以形成逻辑源极/漏极延伸件222e,随后执行第三选择掺杂工艺以形成BCD源极/漏极延伸件232e。在一些实施例中,选择掺杂工艺包括:在图19的结构上沉积光刻层;图案化光刻层,形成源极/漏极延伸件的布局;在图案化的光刻层存在的情况下将掺杂剂注入半导体衬底106内;以及去除图案化的光刻层。
如图21中的截面图2100所示,主侧壁间隔件242在图20中的结构的侧壁上形成。为了说明的简化,仅一些主侧壁间隔件242标为242。主侧壁间隔件242可为或包括诸如氮化硅、一些其他适合的氮化物、一些其他适合的电介质、或前述的任意组合。在一些实施例中,用于形成主侧壁间隔件242的工艺包括:沉积覆盖图20中的结构的主间隔件层;以及随后对主间隔件层执行蚀刻。回蚀去除主间隔件层的水平段而不去除主间隔件层的垂直段,因此保留的垂直段限定主侧壁间隔件242。沉积可诸如通过共形沉积执行、和/或诸如通过CVD、PVD、一些其他适合的沉积工艺、或前述的任意组合来执行。
如图22中的截面图2200所示,一对存储源极/漏极区域202、一对BCD源极/漏极区域232、以及一对逻辑源极/漏极区域222分别形成为上覆存储阱108、第一BCD阱110b1、以及逻辑阱110l。存储源极/漏极区域202分别位于存储阱108的相对两侧,从而选择栅电极216和浮栅电极208夹置在存储源极/漏极区域202之间。进一步地,存储源极/漏极区域202分别邻接存储源极/漏极延伸件202e,并且存储源极/漏极区域202与存储源极/漏极延伸件202e相比,具有相同的掺杂类型和更高的掺杂浓度。BCD源极/漏极区域232分别在第一BCD阱110b1的相对两侧,从而BCD栅电极238夹置在BCD源极/漏极区域232之间。进一步地,BCD源极/漏极区域232中的一个邻接BCD源极/漏极延伸件232e,并且BCD源极/漏极区域232中的一个与BCD源极/漏极延伸件232e相比具有相同的掺杂类型和更高的掺杂浓度。逻辑源极/漏极区域222分别位于逻辑阱110l的相对两侧,从而逻辑栅电极226夹置在逻辑源极/漏极区域222之间。进一步地,逻辑源极/漏极区域222分别邻接逻辑源极/漏极延伸件222e,并且存储源极/漏极区域202与存储源极/漏极延伸件202e相比具有相同的掺杂类型和更高的掺杂浓度。
在一些实施例中,用于形成存储源极/漏极区域202、BCD源极/漏极区域232、以及逻辑源极/漏极区域222的工艺包括重复执行选择掺杂工艺。例如,可执行第一选择掺杂工艺以形成存储源极/漏极区域202,随后执行第二选择掺杂工艺以形成逻辑源极/漏极区域222,随后执行第三选择掺杂工艺以形成BCD源极/漏极区域232。在一些实施例中,选择掺杂工艺包括:在图21中的结构上沉积光刻层;图案化光刻层,形成的源极/漏极区域的布局;在图案化的光刻层存在的情况下将掺杂剂注入半导体衬底106;以及去除图案化的光刻层。
如图23中的截面图2300所示,ILD层122形成为覆盖图22中的结构,并且接触通孔124形成为延伸穿过ILD层122至存储源极/漏极区域202、BCD源极/漏极区域232、逻辑源极/漏极区域222、选择栅电极216、BCD栅电极238、逻辑栅电极226、或前述的任意组合。ILD层122可为或包括诸如二氧化硅、氮化硅、一些其他适合的电介质、或前述的任意组合。进一步地,ILD层122可诸如通过沉积ILD层122和对ILD层122的顶部执行蚀刻而形成。沉积可诸如通过CVD、PVD、或一些其他适合的沉积工艺来执行。平坦化可诸如通过CMP或一些其他适合的平坦化工艺来执行。接触通孔124可为或包括诸如钨、铜、铝铜、铝、一些其他适合的金属、或一些其他适合的导电材料。进一步地,接触通孔124可诸如通过单或双镶嵌工艺来形成。
尽管未示出,在一些实施例中,在形成ILD层122之前在存储源极/漏极区域202、BCD源极/漏极区域232、以及逻辑源极/漏极区域222上形成硅化物焊盘。硅化物焊盘降低接触通孔124与源极/漏极区域之间的接触电阻并且可为或包括诸如镍硅化物或一些其他适合的硅化物。
参考图24,提供了图3至图23中的密封方法的一些实施例的流程图。
在步骤2402处,形成在半导体衬底中划分存储区域、BCD区域、以及逻辑区域的隔离结构。例如,图3中可见。
在步骤2404处,一个或多个BCD阱在半导体衬底的BCD区域中形成。例如,图4中可见。
在步骤2406处,一个或多个逻辑阱在半导体衬底的逻辑区域中形成。例如,图5中可见。
在步骤2408处,密封层形成为覆盖半导体衬底的存储区域、逻辑区域、以及BCD区域。例如,图6中可见。在一些实施例中,密封层为或包括氮化硅或一些其他适合的电介质。进一步地,在一些实施例中,密封层为用于此后在步骤2410中使用的氧化剂的阻挡层。
在步骤2410处,存储单元结构在半导体衬底的存储区域上形成。存储单元结构的形成包括热工艺和/或氧化工艺。例如,图7至图14可见。
在步骤2412处,密封层从BCD区域和逻辑区域处去除。例如,图15可见。密封层保护逻辑阱和BCD阱免受在步骤2410处用来形成存储单元结构的热工艺和/或氧化工艺的损害。例如,密封层防止在步骤2410的热工艺和/或氧化工艺期间使用的氧化剂氧化逻辑阱和BCD阱,从而防止减少逻辑阱和BCD阱的深度并且因此改变逻辑阱和BCD阱的掺杂分布。因此,密封层导致高产以及在逻辑阱和BCD阱上的逻辑器件和BCD器件的稳定的/统一的器件参数。
在步骤2414处,逻辑结构和BCD结构分别在逻辑阱和BCD阱上。例如,图16至图19可见。在一些实施例中,在形成逻辑结构和BCD结构的同时,存储栅电极(例如,选择栅电极)沿存储结构的侧壁形成。
在步骤2416处,形成存储结构、逻辑结构、以及BCD结构的源极/漏极区域。例如,图20至图22可见。
在步骤2418处,后端制程(BEOL)互连结构形成为覆盖半导体衬底、存储结构、逻辑结构、以及BCD结构。例如,图23可见。BEOL互连结构包括ILD层和延伸穿过ILD层至源极/漏极区域的接触通孔。
在图24的流程图2400在此示出和描述为一系列的步骤或时间,应当领会的是,这些步骤或时间的示出的顺序不应在限制的意义中解释。例如,除了在此示出和/或描述的之外,一些步骤可以不同的顺序和/或与其他步骤或时间同时地发生。进一步地,并非所有示出的步骤需要实施在此描述的一个或多个方面或实施例,并且在此描绘的一个或多个步骤可在一个或多个独立的步骤和/或阶段中实施。
参考图25至图32,提供了图3至图23中的密封方法的一些其他实施例的一系列截面图2500至3200。如此后所见,与图3至图23中的密封方法实施例相比,在图25至图32中的密封方法的实施例中,第一栅极介电层120在密封层118之后形成。例如,可执行图25至图32中的密封方法实施例以形成图2B中的IC。
如图25中的截面图2500所示,隔离结构114形成在半导体衬底106中以划分半导体衬底106的存储区域106m、半导体衬底106的BCD区域106b、以及半导体衬底106的逻辑区域106l。进一步地,一个或多个BCD阱110b1至110b5形成在半导体衬底106的BCD区域106b中,并且逻辑阱110l形成在半导体衬底的逻辑区域106l中。隔离结构114、BCD阱110b1至110b5、以及逻辑阱110l可诸如参考图3至图5所述形成。
同样通过图25中的截面图2500示出的,密封层118形成为覆盖半导体衬底106的存储区域106m、BCD区域106b以及逻辑区域106l。密封层118可诸如参考图6所述形成。相比图6,图6中的第一栅极介电层120省略。
如图26中的截面图2600所示,图案化密封层118和下部衬垫层302以在半导体衬底106的存储区域106m上形成第一器件开口702。进一步地,存储阱108穿过第一器件开口702在半导体衬底106的存储区域106m中形成。图案化和形成存储阱108可参考图7和图8所述执行。
如图27中的截面图2700所示,浮栅介电层210、浮栅电极208、以及浮栅硬掩模206在存储阱108上堆叠形成。进一步地,第三栅极介电层1302形成为覆盖密封层118和存储阱108。更进一步地,存储侧壁间隔件218在第三栅极介电层1302上邻近浮栅电极208的侧壁形成。该形成可参考诸如图9至图14所述执行。
如图28中的截面图2800所示,图案化第三栅极介电层1302(图27中可见)、密封层118(图27中可见)、以及下部衬垫层302(图27中可见)以将第三栅极介电层1302、密封层118、以及下部衬垫层302从半导体衬底106的逻辑区域106l和BCD区域106b处去除。该图案化可参考诸如图15所述执行。相比图15,下部衬垫层302同样图案化。
如图29中的截面图2900所示,第一栅极介电层120形成为覆盖半导体衬底106的存储区域106m、BCD区域106b以及逻辑区域106l。第一栅极介电层120可为或包括诸如氧化硅、一些其他适合的氧化物、一些其他适合的电介质、或前述的任意组合。在一些实施例中,第一栅极介电层120通过CVD、PCD、热氧化、一些其他适合的沉积工艺、或前述的任意组合形成。
在第一栅极介电层120通过热氧化形成的一些实施例中,第一栅极介电层120在BCD区域106b和逻辑区域106l上比在存储区域106m上形成的更快,从而第一栅极介电层120在BCD区域106b和逻辑区域106l上具有第二厚度T2并且在存储区域106m上具有小于第二厚度T2的第五厚度T5。在一些实施例中,第二厚度T2为大约60至200埃、大约60至130埃、大约130至200埃、大约20至100埃、或大约160至240埃。由于被氧化的材料不同,第一栅极介电层120可诸如在BCD区域106b和逻辑区域106l上比在存储区域106m上形成的更快。
如图30中的截面图3000所示,图案化第一栅极介电层120以将第一栅极介电层120从逻辑阱110l去除。进一步地,第四栅极介电层1702和第二栅电极1704形成为覆盖半导体衬底106的存储区域106m、BCD区域106b、以及逻辑区域106l。图案化和形成可诸如参考图17和图18所述来执行。
如图31中的截面图3100所示,图案化第二栅电极层1704(图30可见)、第四栅极介电层1702(图30可见)、第一栅极介电层120(图30可见)、以及第一选择栅极介电层214。该图案化形成堆叠在逻辑阱110l上的逻辑栅电极226和逻辑栅极介电层228。进一步地,该图案化形成堆叠在BCD阱110b1至110b5上的BCD栅电极238和多个BCD栅极介电层240a、240b。进一步地,该图案化形成相互堆叠并且上覆第一选择栅极介电层214、存储侧壁间隔件218、以及浮栅硬掩模206的选择栅电极216、第二选择栅极介电层220、以及第三选择栅极介电层244。该图案化和形成可诸如参考图18所述来执行。相比图18,该图案化还形成第三选择栅极介电层244,但是图18的第三BCD栅极介电层240c省略。
如图32中的截面图3200所述,进一步图案化BCD栅电极238和多个BCD栅极介电层240a、240b,并且主体阱234形成为上覆第二BCD阱110b2。进一步地,一对存储源极/漏极延伸件202e、BCD源极/漏极延伸件232e、以及一对逻辑源极/漏极延伸件222e形成为分别上覆存储阱108、主体阱234、以及逻辑阱110l。进一步地,形成主侧壁间隔件242,随后形成一对存储源极/漏极区域202、一对BCD源极/漏极区域232、以及一对逻辑源极/漏极区域222。进一步地,形成ILD层122和接触通孔124。该形成可诸如参考图19至图23所述来执行。
在一些实施例中,本公开公开了一种用于形成集成电路的方法,该方法包括:提供包括第一器件区域和由隔离结构分隔的第二器件区域的半导体衬底;在第二器件区域中形成掺杂阱;形成覆盖第一和第二器件区域、并且进一步覆盖掺杂阱的密封层;从第一器件区域而非从第二器件区域去除密封层;在第一器件区域上形成存储单元结构;在存储单元结构形成之后,从第二器件区域去除密封层;以及在第二器件区域上形成器件结构。在一些实施例中,存储单元结构的形成包括使半导体衬底的顶面在第一器件区域而非在第二器件区域凹陷。在一些实施例中,该方法进一步包括在隔离结构、第一器件区域、以及第二器件区域上形成栅极介电层,其中栅极介电层相比密封层为不同的材料并且在密封层从第二器件区域去除之后形成。在一些实施例中,该方法包括在隔离结构、第一器件区域、以及第二器件区域上形成栅极介电层,其中栅极介电层相比密封层为不同的材料,并且其中密封层形成为覆盖栅极介电层。在一些实施例中,密封层包括氮化硅、碳化硅、多晶硅、或氮氧化硅。在一些实施例中,存储单元结构使用氧化工艺形成。在一些实施例中,存储单元结构的形成包括形成存储栅极介电层、覆盖存储栅极介电层的存储栅电极、以及覆盖存储栅电极的存储栅极硬掩模,其中存储栅极介电层通过氧化工艺形成。在一些实施例中,该方法进一步包括在密封层从第一器件区域去除之后并且在存储单元结构的形成之前在第一器件区域上形成第二掺杂阱。在一些实施例中,该方法进一步包括:沉积覆盖第一和第二器件区域并且进一步覆盖存储单元结构的导电层;以及图案化导电层以形成覆盖掺杂阱并且至少部分限定器件结构的器件栅电极,并且以进一步形成邻接存储单元结构的存储栅电极。
在一些实施例中,本公开提供了一种集成电路,包括:包括第一器件区域和第二器件区域的半导体衬底;延伸进入半导体衬底的顶面的隔离结构,其中隔离结构划分和分隔第一和第二器件区域;覆盖第一器件区域的存储单元;覆盖第二器件区域的MOS器件;以及覆盖隔离结构的伪结构,其中伪结构包括伪密封元件。在一些实施例中,伪密封元件包括氮化硅、碳化硅、氮氧化硅或多晶硅。在一些实施例中,伪密封元件直接接触隔离结构。在一些实施例中,伪结构进一步包括伪介电元件,其中伪密封元件覆盖伪介电元件。在一些实施例中,伪结构包括一对分别在存储单元的相对两侧上的伪段。在一些实施例中,半导体衬底的顶面在第一器件区域具有第一顶面部分,并且进一步在第二器件区域具有第二顶面部分,其中第一顶面区域凹陷低于第二顶面部分。在一些实施例中,存储单元包括存储栅极介电层和覆盖存储栅极介电层的存储栅电极,其中第一顶面部分比第二顶面部分凹进去了凹陷深度,并且存储栅极介电层的厚度为凹陷深度的大约1.75至2.25倍。
在一些实施例中,本公开提供用于形成集成电路的另一种方法,该方法包括:在半导体衬底中形成隔离结构,其中隔离结构划分半导体衬底的存储区域,并且进一步划分半导体衬底的外围区域;在外围区域中形成掺杂阱;形成覆盖存储区域和外围区域并且进一步覆盖掺杂阱的密封层;从存储区域而非从外围区域将密封层去除;在存储区域上通过热氧化工艺形成栅极介电层,其中热氧化工艺使半导体衬底的顶面在存储区域而非在外围区域凹陷;在栅极介电层上方形成存储栅电极;在存储栅电极形成之后,将密封层从外围区域去除;以及在同时形成邻接存储栅电极的第二存储栅电极的同时在外围区域上形成外围栅电极。在一些实施例中,该方法进一步包括:形成覆盖存储区域和外围区域并且进一步覆盖掺杂阱的第二栅极介电层,其中密封层形成为覆盖第二栅极介电层;以及在栅极介电层的形成之前将第二栅极介电层从存储区域而非从外围区域去除。在一些实施例中,该方法进一步包括:形成覆盖存储区域和外围区域并且进一步覆盖掺杂阱的第二栅极介电层,其中从外围区域去除密封层是在形成第二栅极介电层之前执行;以及图案化第二栅极介电层以在外围区域上形成外围栅极介电层,其中外围栅极介电层覆盖外围栅电极。在一些实施例中,第二栅极介电层的图案化进一步在存储区域上形成存储栅极介电层,其中存储栅极介电层位于第二存储栅电极之下。
上文概括了若干实施例的特征从而本领域中的技术人员可更优理解本公开的各个方面。本领域中的技术人员应当领会到的是,可易于将本公开用作用于设计或修改其他用于实施与在此介绍的实施例的同样的目的和/或达到同样的益处工艺和结构的基础。本领域中的技术人员应当理解,这样的等效结构并不背离本公开的主旨和范围,并且在不背离本公开的主旨和范围的前提下,在此其可作出不同的修改、代替、以及替代。
Claims (20)
1.一种用于形成集成电路的方法,所述方法包括:
提供包括第一器件区域和第二器件区域的半导体衬底,所述第一器件区域和所述第二器件区域由隔离结构分隔;
在所述第二器件区域中形成掺杂阱;
形成覆盖所述第一器件区域和所述第二器件区域并且还覆盖所述掺杂阱的密封层;
从所述第一器件区域而不是从所述第二器件区域处去除所述密封层;
在所述第一器件区域上形成存储单元结构,形成所述存储单元结构包括使所述半导体衬底在所述第一器件区域处而非在所述第二器件区域处的顶面凹陷,其中,所述半导体衬底的在所述第一器件区域的第一顶面部分凹陷在所述半导体衬底的在所述第二器件区域的第二顶面部分的下方;
在形成所述存储单元结构之后,从所述第二器件区域处去除所述密封层;以及
在所述第二器件区域上形成器件结构。
2.根据权利要求1所述的方法,其中,从所述第一器件区域而不是从所述第二器件区域处去除所述密封层以在所述密封层中形成贯通孔,其中,所述存储单元结构穿过所述贯通孔。
3.根据权利要求1所述的方法,还包括:
在所述隔离结构、所述第一器件区域以及所述第二器件区域上形成栅极介电层,其中,所述栅极介电层是与所述密封层不同的材料并且在所述密封层从所述第二器件区域处去除之后形成。
4.根据权利要求1所述的方法,还包括:
在所述隔离结构、所述第一器件区域以及所述第二器件区域上形成栅极介电层,其中,所述栅极介电层是与所述密封层不同的材料,并且所述密封层形成为覆盖所述栅极介电层。
5.根据权利要求1所述的方法,其中,所述密封层包括氮化硅、碳化硅、多晶硅或氮氧化硅。
6.根据权利要求1所述的方法,其中,使用氧化工艺形成所述存储单元结构。
7.根据权利要求6所述的方法,其中,形成所述存储单元结构包括:
形成存储栅极介电层、覆盖所述存储栅极介电层的存储栅电极、以及覆盖所述存储栅电极的存储栅极硬掩模,其中,所述存储栅极介电层通过所述氧化工艺形成。
8.根据权利要求1所述的方法,还包括:
在从所述第一器件区域去除所述密封层之后且在形成所述存储单元结构之前,在所述第一器件区域中形成第二掺杂阱。
9.根据权利要求1所述的方法,还包括:
沉积覆盖所述第一器件区域和所述第二器件区域并且还覆盖所述存储单元结构的导电层;以及
图案化所述导电层,以形成覆盖所述掺杂阱和至少部分限定所述器件结构的器件栅电极,并且以形成邻接所述存储单元结构的存储栅电极。
10.一种集成电路,包括:
半导体衬底,包括第一器件区域和第二器件区域;
隔离结构,延伸进入所述半导体衬底的顶面,其中,所述隔离结构划分和分隔所述第一器件区域和所述第二器件区域;
存储单元,覆盖所述第一器件区域;
金属氧化物半导体(MOS)器件,覆盖所述第二器件区域;以及
伪结构,覆盖所述隔离结构,其中,所述伪结构包括伪密封元件,
其中,所述半导体衬底的顶面在所述第一器件区域具有第一顶面部分,并且在所述第二器件区域还具有第二顶面部分,并且所述第一顶面部分凹陷在所述第二顶面部分的下方。
11.根据权利要求10所述的集成电路,其中,所述伪密封元件包括氮化硅、碳化硅、氮氧化硅或多晶硅。
12.根据权利要求10所述的集成电路,其中,所述伪密封元件直接接触所述隔离结构。
13.根据权利要求10所述的集成电路,其中,所述伪结构还包括伪介电元件,并且所述伪密封元件覆盖所述伪介电元件。
14.根据权利要求10所述的集成电路,其中,所述伪结构包括一对分别位于所述存储单元的相对两侧上的伪段。
15.根据权利要求14所述的集成电路,其中,所述所述第一器件区域中包括存储阱,所述伪结构的平面顶部布局以封闭路径沿所述存储阱的边界横向延伸,以完全封闭所述存储阱,沿所述封闭路径从所述伪段中的一者至所述伪段中的另一者是连续的。
16.根据权利要求15所述的集成电路,其中,所述存储单元包括存储栅极介电层和覆盖所述存储栅极介电层的存储栅电极,其中,所述第一顶面部分比所述第二顶面部分凹进去了凹陷深度,并且所述存储栅极介电层的厚度为所述凹陷深度的1.75至2.25倍。
17.一种用于形成集成电路的方法,该方法包括:
在半导体衬底中形成隔离结构,其中,所述隔离结构划分半导体衬底的存储区域,并且还划分所述半导体衬底的外围区域;
在所述外围区域中形成掺杂阱;
形成覆盖所述存储区域和所述外围区域并且还覆盖所述掺杂阱的密封层;
从所述存储区域而非从所述外围区域处去除所述密封层;
通过热氧化工艺在所述存储区域形成栅极介电层,其中,所述热氧化工艺使所述半导体衬底的顶面在所述存储区域而非在所述外围区域凹陷,其中,所述半导体衬底的在所述存储区域的第一顶面部分凹陷在所述半导体衬底的在所述外围区域的第二顶面部分的下方;
在所述栅极介电层上方形成存储栅电极;
在形成所述存储栅电极之后,从所述外围区域处去除所述密封层;以及
在同时形成邻接所述存储栅电极的第二存储栅电极的同时,在所述外围区域上形成外围栅电极。
18.根据权利要求17所述的方法,还包括:
形成覆盖所述存储区域和所述外围区域并且还覆盖所述掺杂阱的第二栅极介电层,其中,所述密封层形成为覆盖所述第二栅极介电层;以及
在形成所述栅极介电层之前,从所述存储区域而非从所述外围区域处去除所述第二栅极介电层。
19.根据权利要求17所述的方法,还包括:
形成覆盖所述存储区域和所述外围区域并且还覆盖所述掺杂阱的第二栅极介电层,其中,在形成所述第二栅极介电层之前,执行所述密封层从所述外围区域处的去除;以及
图案化所述第二栅极介电层以在所述外围区域上形成外围栅极介电层,其中,所述外围栅极介电层位于所述外围栅电极下方。
20.根据权利要求19所述的方法,其中,图案化所述第二栅极介电层还在所述存储区域上形成存储栅极介电层,其中,所述存储栅极介电层位于所述第二存储栅电极之下。
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