WO2020019282A1 - 存储器结构及其形成方法 - Google Patents

存储器结构及其形成方法 Download PDF

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Publication number
WO2020019282A1
WO2020019282A1 PCT/CN2018/097349 CN2018097349W WO2020019282A1 WO 2020019282 A1 WO2020019282 A1 WO 2020019282A1 CN 2018097349 W CN2018097349 W CN 2018097349W WO 2020019282 A1 WO2020019282 A1 WO 2020019282A1
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Prior art keywords
layer
doped well
substrate
substrate layer
memory
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PCT/CN2018/097349
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English (en)
French (fr)
Inventor
董金文
陈俊
夏志良
华子群
朱继锋
陈赫
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长江存储科技有限责任公司
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Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to PCT/CN2018/097349 priority Critical patent/WO2020019282A1/zh
Priority to CN201880096618.9A priority patent/CN112567515B/zh
Priority to PCT/CN2018/102504 priority patent/WO2019042250A1/zh
Priority to TW107131271A priority patent/TWI670857B/zh
Priority to US16/127,141 priority patent/US10840125B2/en
Publication of WO2020019282A1 publication Critical patent/WO2020019282A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a memory structure and a method for forming the same.
  • flash memory has been particularly rapid.
  • the main feature of flash memory is that it can keep stored information for a long time without powering on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used.
  • the technology of three-dimensional flash memory (3D NAND) has been rapidly developed.
  • the 3D NAND flash memory structure includes a memory array structure and a CMOS circuit structure located above the memory array structure.
  • the memory array structure and the CMOS circuit structure are usually formed on two different wafers respectively, and then by bonding, the The CMOS circuit wafer is bonded to the entire memory array structure to connect the CMOS circuit and the memory array circuit together. Then, the back of the wafer on which the memory array structure is located is thinned, and the entire circuit is connected through the contact portion penetrating the back. During the backside thinning process, the thickness of the deep doped well or the substrate remaining under the deep doped well in the wafer is too small, which will cause serious leakage between the deeply doped well and the substrate.
  • the leakage current is generally reduced by strictly controlling the depth of the doped well and retaining a sufficient substrate thickness under the deeply doped well.
  • the prior art method for preventing leakage current requires strict control of the process, which results in a smaller effective window of the process, and process deviations may lead to bulk scrapping of wafers.
  • the back silicon since the circuit is connected, the back silicon needs to be penetrated to form a through contact. Increasing the thickness remaining under the doped well will increase the aspect ratio of the through contact and increase the difficulty of the process. Furthermore, the increase in the thickness of the substrate remaining under the doped well will cause the parasitic capacitance of the pads connected to the circuit to increase, affecting the performance of the product.
  • the technical problem to be solved by the present invention is to provide a memory structure and a method for forming the memory structure, so as to avoid leakage between the doped well and the substrate.
  • the technical solution of the present invention provides a memory structure including a first substrate including a substrate layer and a storage layer.
  • the substrate layer has a first surface and a second surface opposite to each other, and the storage layer is located on the substrate layer.
  • the substrate layer On the first surface, the substrate layer has a doped well; an isolation structure penetrates the substrate layer and is located at the edge of the doped well and surrounds the doped well, and is used to isolate the doped well from the doped well.
  • a substrate layer surrounding the isolation structure is used to isolate the doped well from the doped well.
  • At least one side wall of the isolation structure is connected to the doped well.
  • a first contact portion is formed in the memory layer for connecting to the first type doped well, and the first contact portion is located on a surface of the first type doped well surrounded by the isolation structure.
  • the isolation structure includes an isolation trench penetrating the substrate layer and an isolation material filling the isolation trench.
  • the first substrate further includes a dielectric layer on the second surface of the substrate layer, and the isolation structure further penetrates the dielectric layer.
  • the method further includes: a second contact portion penetrating the dielectric layer and the substrate layer.
  • the second contact portion includes a metal pillar and an insulating side wall located on a side wall surface of the metal pillar.
  • the bottom of the doped well is located in the substrate layer and has a distance from the second surface of the substrate layer.
  • the second surface of the substrate layer exposes a bottom surface of the doped well.
  • the doped well includes a first type doped well and a second type doped well located within the first type doped well.
  • the method further includes: a second substrate on which a peripheral circuit is formed; the second substrate is located on a surface of the storage layer, and a storage unit is formed in the storage layer; A memory circuit structure in which an electrical connection is formed between a peripheral circuit in the second substrate and a memory circuit structure in the memory layer.
  • a specific embodiment of the present invention further provides a method for forming a memory structure, including: providing a first substrate including a substrate layer and a storage layer, the substrate layer having a first surface and a second surface opposite to each other, The storage layer is located on the first surface of the substrate layer, and the substrate layer has a doped well therein; forming an isolation structure penetrating the substrate layer, surrounding the doped well, and configured to isolate the doping A well and a substrate layer surrounding the isolation structure.
  • At least one side wall of the isolation structure is connected to the doped well.
  • a first contact portion is formed in the memory layer for connecting to the first type doped well, and the first contact portion is located on a surface of the first type doped well surrounded by the isolation structure.
  • the step of forming an isolation structure penetrating the substrate layer further includes: forming an isolation trench penetrating the substrate layer, the isolation trench being located at an edge of the doped well and disposed around the doped well; An isolation material is formed to fill the isolation trench.
  • the method further includes: forming a dielectric layer on the second surface of the substrate layer, and the isolation structure further penetrates the dielectric layer.
  • the method further includes: forming a second contact portion penetrating the dielectric layer and the substrate layer.
  • the method for forming the second contact portion and the isolation structure includes: etching the dielectric layer to the substrate layer, and forming a first opening and a second opening in the dielectric layer; along the first The opening and the second opening simultaneously etch the substrate layer to form isolation trenches and contact holes penetrating through the substrate layer, respectively; and form the first trenches and fill the isolation trenches and cover the contact holes and the first holes.
  • the bottom of the doped well is located in the substrate layer with a gap from the second surface of the substrate layer, or the second surface of the substrate layer exposes the bottom of the doped well surface.
  • the doped well includes a first type doped well and a second type doped well located within the first type doped well.
  • the surface of the storage layer further has a second substrate, and peripheral circuits are formed in the second substrate; the second substrate is located on the surface of the storage layer, and a storage unit and a connection unit are formed in the storage layer In the memory circuit structure of the memory unit, an electrical connection is formed between a peripheral circuit in the second substrate and a memory circuit structure in the memory layer.
  • An isolation structure is formed in the substrate layer of the memory structure of the present invention as a physical isolation structure between the doped well and the surrounding substrate, which can avoid the leakage problem between the doped well and the substrate layer around the isolation structure, thereby improving the Memory performance.
  • the method for forming a memory structure of the present invention forms an isolation structure between the doped well and the surrounding substrate while forming a contact portion connected to the memory layer through the substrate layer, without adding additional process steps, without increasing Under the premise of process cost, the leakage problem between the doped well and the surrounding substrate can be avoided, which is beneficial to improving the performance of the memory structure.
  • FIGS. 1 to 6 are schematic structural diagrams of a memory structure forming process according to a specific embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a memory structure according to a specific embodiment of the present invention.
  • FIGS. 1 to 6 are schematic structural diagrams of a memory structure formation process according to a specific embodiment of the present invention.
  • a first substrate 100 which includes a substrate layer 101 and a storage layer 102.
  • the substrate layer 101 has a first surface 11 and a second surface 12 opposite to each other.
  • the storage layer 102 is located on the substrate layer 101.
  • the substrate layer 101 has a doped well therein.
  • the first substrate 100 is in an inverted state.
  • the first surface 11 of the substrate layer 101 is a lower surface of the substrate layer 101
  • the second surface 12 is an upper surface of the substrate layer 101.
  • the storage layer 102 covers the first surface 11 of the substrate layer 101.
  • the corresponding storage layer 102 is also located below the substrate layer 101.
  • the relative position descriptions of the top, bottom, top, and bottom are all relative to the first substrate 100 in an upright state.
  • the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
  • the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate.
  • the surface of the single crystal silicon epitaxial layer is a first surface 11.
  • the other surface of the single crystal silicon wafer is the second surface 12.
  • the doped well is formed by ion doping the first surface 11 of the substrate layer 101. According to the ion doping direction, the top of the doped well near the first surface 11 and the second surface 12 near the first surface 11 Is the bottom of the doped well. The top surface of the doped well is coplanar with the first surface 11 of the substrate layer 101.
  • the doped well includes a first type doped well 111 and a second type doped well 112 located within the first type doped well 111.
  • the first-type doped well 111 is an N-type doped well
  • the second-type doped well 112 is a P-type doped well.
  • the second-type doped well 112 is a P-type doped well
  • the first-type doped well 111 includes N-type doped wells located on both sides of the P-type doped well, and N-type doped wells and N-type deeply doped wells below the P-type doped well.
  • a plurality of doped wells may be formed in the substrate layer 101, and there is a certain distance between adjacent doped wells.
  • the substrate layer 101 can be formed by thinning the back surface of the wafer on which the doped well is formed. According to the degree of thinning, the distance between the bottom of the doped well and the second surface 12 of the substrate layer 101 can be adjusted. .
  • the second surface 12 of the substrate layer 101 exposes the bottom surface of the first type doped well 111.
  • the thickness is reduced to expose the The first type doped well 111.
  • the first type doped well 111 is located in the substrate layer 101, and a bottom surface of the first type doped well 111 and a second surface 12 of the substrate layer 101 have a spacing.
  • the memory layer 102 includes an insulating layer, a memory cell formed in the insulating layer, and a memory circuit connected to the memory cell.
  • a 3D NAND memory cell is formed in the memory layer 102, and the memory cells are all formed on the top surface of the second type doped well 112.
  • the memory layer 102 further includes a through-array contact portion 121 penetrating the memory cell and an interconnection layer 122 connected to the array contact portion 121.
  • FIG. 1 only one through-array contact 121 and a part of the interconnection layer 122 are shown, as a schematic illustration. In an actual memory structure, a plurality of the through-array contact portions 121 may be formed in each memory cell.
  • the first substrate 100 further includes a dielectric layer 103 on the second surface 12 of the substrate layer 101.
  • the dielectric layer 103 serves as a passivation layer covering the second surface 12 of the substrate layer 101 and is used to protect the second surface 12 of the substrate layer 101.
  • the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
  • the dielectric layer 103 may be a single-layer structure or a multilayer stack structure.
  • the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, and an atomic layer deposition process.
  • the other surface of the storage layer 102 opposite to the substrate layer 101 is also bonded to a second substrate 200, and peripheral circuits are formed in the second substrate 200.
  • the second substrate 200 is located in the storage.
  • an electrical connection is formed between the peripheral circuits in the second substrate 200 and the memory circuits in the memory layer 102.
  • the surface of the second substrate 200 facing the storage layer 102 exposes the surface of the connection portion of the peripheral circuit
  • the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit.
  • the two are bonded to form Electrical connection.
  • the dielectric layer 103 is etched to the second surface 12 of the substrate layer 101, and a first opening 131 and a second opening 132 are formed in the dielectric layer 103.
  • the method for forming the first opening 131 and the second opening 132 includes forming a photoresist layer on the surface of the dielectric layer 103, and exposing and developing the photoresist layer with a photomask to form a pattern.
  • the first opening 131 is used to define the position and size of the isolation structure to be formed later, and the second opening 132 is used to define the position and size of the contact portion to be formed through the substrate layer 101.
  • the same photomask is used for the photolithography process to form a patterned photoresist layer on the dielectric layer 103, and then the dielectric layer 103 is etched to form the second opening 132 and the first opening 131 at the same time. No additional process steps are required for the isolation structure. .
  • the first opening 131 is in the shape of an annular groove; the second opening 132 is in the shape of a hole, and the cross section may be circular, rectangular, or polygonal.
  • the substrate layer 101 is simultaneously etched along the first opening 131 and the second opening 132 to form isolation trenches 113 and contact holes 114 penetrating through the substrate layer 101, respectively.
  • the bottom of the contact hole 114 exposes the electrical connection structure in the storage layer 102, and a second contact portion penetrating the substrate layer 101 is subsequently formed in the contact hole 114 to connect with the electrical connection structure in the storage layer 102. .
  • only one contact hole 114 is formed.
  • the contact hole 114 passes through the doped well, and the bottom portion exposes the through-array contact portion 121 in the storage layer 102.
  • a plurality of contact holes 114 may be formed, and a part of the contact holes 114 may be located at the periphery of the doped well, exposing the electrical connection structure outside the memory cell.
  • At least one side wall of the isolation trench 113 is connected to the doped well.
  • the isolation trench 113 is located at the edge of the doped well and is disposed around the doped well.
  • the isolation trench 113 is located in the first-type doped well 111, and the sidewalls on both sides of the isolation trench 113 expose the first-type doped well 111.
  • only one side wall of the isolation trench 113 exposes the first type doped well 111, and the other side wall exposes the substrate layer 101.
  • the isolation trench 113 and the edge of the first-type doped well 111 there may be a certain distance between the isolation trench 113 and the edge of the first-type doped well 111, and the first-type doped well 111 and subsequent Part of the thickness of the silicon is formed between the isolation structures formed in 113.
  • the substrate layer 101 around the isolation trench 113 is grounded during the operation of the memory. Therefore, a part of the substrate layer 101 between the isolation structure and the first-type doped well 111 does not form a conductive path, and therefore does not cause leakage.
  • a width of the isolation trench 113 is smaller than a width of the contact hole 114.
  • the width of the isolation trench 113 is less than half of the aperture width of the contact hole 114 and greater than 20 nm, and the maximum width of the aperture of the contact hole 114 is 1500 nm.
  • an insulating material layer 400 is formed to fill the isolation trench 113, the first opening 131, and an inner wall surface of the contact hole 114 and the second opening 132.
  • the material of the insulating material layer 400 may be an insulating dielectric material such as silicon oxide, silicon oxynitride, or silicon nitride.
  • the insulating material layer 400 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and the like. Since the width of the isolation trench 113 is smaller than the diameter of the contact hole 114, when the insulation material layer 400 fills the isolation trench 113 and the first opening 131, the insulation material layer 400 only covers the contact The inner wall surface of the hole 114 and the second opening 132.
  • the insulating material layer 400 also covers the surface of the dielectric layer 103.
  • the insulating material layer 400 at the bottom of the contact hole 114 is removed to form an insulating sidewall 402 covering the sidewall of the contact hole 114 and the second opening 132, and filled in the isolation trench 113 and the first
  • the insulating material layer in the opening 131 serves as the isolation structure 401.
  • An anisotropic etching process is used to remove the insulating material layer 400 located at the bottom of the contact hole 114.
  • the insulating material layer 400 at the bottom of the contact hole 114 is removed, the insulating material layer 400 on the surface of the dielectric layer 103 is also removed.
  • a portion of the thickness of the insulating material layer 400 remains on the surface of the dielectric layer 103.
  • At least one sidewall of the isolation structure 401 is connected to the doped well.
  • the isolation structure 401 is completely located in the first type doped well 111 and is close to an edge of the first type doped well 111. Therefore, both sidewalls of the isolation structure 401 are Is connected to the first type doped well 111, most of the first type doped well 111 and the second type doped well 112 are surrounded by the isolation structure 401, and the doped well region surrounded by the isolation structure 401 is Physical isolation is achieved between the surrounding substrate layers 101 through the isolation structure 401.
  • one side wall of the isolation structure 401 is connected to the first type doped well 111, and the other side is connected to the substrate layer 101 around the first type doped well 111.
  • the isolation structure 401 there may be a certain distance between the isolation structure 401 and the edge of the first type doped well 111, and the distance between the first type doped well 111 and the isolation structure 401 may also be a certain distance.
  • Substrate material with partial thickness. The isolation structure 401 is used to achieve isolation between a region surrounded by the isolation structure 401 and a substrate material around the isolation structure 401.
  • the isolation structure 401 is used as a physical isolation structure, which can avoid leakage problems between the first doped well 111 and the substrate layer 101 around the isolation structure 401, and Improve memory performance.
  • the first type doped well 111 is in direct contact with the surrounding substrate layer 101, a depletion layer is formed, which can reduce the leakage, but the depletion layer needs to have a sufficient thickness to completely avoid the occurrence of leakage. In this case, a larger thickness of an undoped substrate is required at the periphery of the first type doped well 111, and therefore, a larger thickness of the substrate layer is required.
  • the first type doped well 111 is physically isolated from the peripheral substrate layer 101 through the isolation structure 401, there is no need to isolate it through a depletion layer. Therefore, the second surface 12 of the substrate layer 101 can be thinned to expose the bottom surface of the first type doped well 111.
  • a substrate material with a partial thickness is further provided between the bottom surface of the first type doped well 111 and the second surface 12, and the bottom surface of the first type doped well 111
  • the distance from the second surface 12 is small, for example, it can be less than 1 ⁇ m, so the thickness of the substrate layer 101 is low.
  • the isolation structure 401 is formed without adding additional process steps.
  • the storage layer 102 may further include a first contact portion 123 connected to the first type doped well 111, and the first contact portion 123 is located in the first type doped well 111 surrounded by the isolation structure 401. Top surface.
  • a metal material layer filled with the contact hole 114 and the second opening 132 is formed, and the dielectric layer 102 is used as a stop layer for planarization, and is formed in the contact hole 114 and the second opening 132.
  • the insulating side wall 402 and the metal pillar 403 constitute a second contact portion.
  • the material of the metal material layer may be a metal material such as W, Cu, Al, or Au.
  • the metal material layer may be formed by a physical vapor deposition process, such as a sputtering process.
  • Planarize the metal material layer remove the metal material layer located on the surface of the dielectric layer 103 to form a metal pillar 403, and the metal pillar 403 is connected to the through-array contact portion 121 in the storage layer 102 to realize the connection with the Connection of storage circuits in the storage layer 102.
  • Subsequent steps also include forming solder pads or other electrical connection structures on the surface of the dielectric layer 103 and connected to the metal pillars 403. Because in this specific implementation manner, an isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the doped well and the surrounding substrate, therefore, the bottom of the doped well does not need to have a thick substrate, so that The overall thickness of the substrate layer 101 is relatively low, so that the parasitic capacitance between the pads or other electrical connection structures formed on the dielectric layer 103 and the device layer 102 can be reduced, and the performance of the memory structure can be improved.
  • the substrate layer 101 is etched to form an isolation trench, and the isolation trench is filled with an isolation material as an isolation structure.
  • a dielectric layer 103 is formed on the second surface 12 of the substrate layer 101, the dielectric layer 103 and the substrate layer 101 are etched to form a contact hole penetrating the dielectric layer 103 and the substrate layer 101, and an inner wall surface of the contact hole is formed.
  • a specific embodiment of the present invention also provides a storage structure formed by the above method.
  • FIG. 6 is a schematic structural diagram of a storage structure according to a specific embodiment of the present invention.
  • the storage structure includes a first substrate 100, which includes a substrate layer 101 and a storage layer 102.
  • the substrate layer 101 has a first surface 11 and a second surface 12, and the storage layer 102 is opposite. It is located on the first surface 11 of the substrate layer 101, and the substrate layer 101 has a doped well therein; an isolation structure 401 runs through the substrate layer 101 and is located at the edge of the doped well to isolate the doped well.
  • the well and the surrounding substrate layer 101 is a doped well therein
  • the substrate layer 101 is a semiconductor material layer, and may be a single crystal silicon wafer, a semiconductor epitaxial layer including a single crystal silicon wafer and a wafer surface, or a silicon-on-insulator substrate.
  • the substrate layer 101 includes a single crystal silicon wafer and a single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate.
  • the surface of the single crystal silicon epitaxial layer is a first surface 11.
  • the other surface of the single crystal silicon wafer is the second surface 12.
  • the first substrate 100 is in an inverted state.
  • the first surface 11 of the substrate layer 101 is a lower surface of the substrate layer 101
  • the second surface 12 is an upper surface of the substrate layer 101.
  • the storage layer 102 covers the first surface 11 of the substrate layer 101.
  • the corresponding storage layer 102 is also located below the substrate layer 101.
  • the doped well is formed by ion doping the first surface 11 of the substrate layer 101. According to the ion doping direction, the top of the doped well near the first surface 11 and the second surface 12 near the first surface 11 Is the bottom of the doped well. The top surface of the doped well is coplanar with the first surface 11 of the substrate layer 101.
  • the doped well includes a first type doped well 111 and a second type doped well 112 located within the first type doped well 111.
  • the first-type doped well 111 is an N-type doped well
  • the second-type doped well 112 is a P-type doped well.
  • the second-type doped well 112 is a P-type doped well
  • the first-type doped well 111 includes N-type doped wells located on both sides of the P-type doped well and the second type doped well 111. N-type doped wells and N-type deeply doped wells below the P-type doped well.
  • a plurality of doped wells may be formed in the substrate layer 101, and there is a certain distance between adjacent doped wells.
  • the substrate layer 101 may be formed by thinning the back surface of the wafer on which the doped well is formed. Depending on the degree of thinning, the distance between the bottom of the doped well and the second surface of the substrate layer 101 may be adjusted.
  • the second surface 12 of the substrate layer 101 exposes a bottom surface of the first type doped well 111.
  • the thinning is performed until the first type doped well 111 is exposed.
  • the first type doped well 111 is located in the substrate layer 101, and a bottom surface of the first type doped well 111 and a second surface 12 of the substrate layer 101 have a spacing.
  • the memory layer 102 includes an insulating layer, a memory cell formed in the insulating layer, and a memory circuit connected to the memory cell.
  • a 3D NAND memory cell is formed in the memory layer 102, and the memory cells are all formed on the surface of the second type doped well 112.
  • the memory layer 102 further includes a through-array contact portion 121 penetrating the memory cell and an interconnection layer 122 through the array contact portion 121.
  • FIG. 1 only one through-array contact 121 and a part of the interconnection layer 122 are shown as a schematic diagram. In an actual memory structure, a plurality of the through-array contact portions 121 may be formed in each memory cell.
  • the first substrate 100 further includes a dielectric layer 103 on the second surface 12 of the substrate layer 101.
  • the dielectric layer 103 serves as a passivation layer on the second surface 12 of the substrate layer 101 and is used to protect the second surface 12 of the substrate layer 101.
  • the material of the dielectric layer 103 may be an insulating dielectric material such as TEOS, silicon nitride, silicon oxynitride, or silicon oxide.
  • the dielectric layer 103 may be a single-layer structure or a multilayer stack structure.
  • the dielectric layer 103 may be formed by various deposition processes such as a chemical vapor deposition process, a spin coating process, and an atomic layer deposition process.
  • the isolation structure 401 includes an isolation trench penetrating the substrate layer 101 and an isolation material filling the isolation trench. In this specific implementation manner, the isolation structure 401 further penetrates the dielectric layer 103. In another specific implementation manner, the isolation structure 401 may also be located only in the substrate layer 101.
  • At least one side wall of the isolation structure 401 is connected to the doped well.
  • the isolation structure 401 is completely located in the first type doped well 111 and is close to an edge of the first type doped well 111. Therefore, both sidewalls of the isolation structure 401 are Is connected to the first type doped well 111, most of the first type doped well 111 and the second type doped well 112 are surrounded by the isolation structure 401, and the doped well region surrounded by the isolation structure 401 is Physical isolation is achieved between the surrounding substrate layers 101 through the isolation structure 401.
  • one side wall of the isolation structure 401 is connected to the first type doped well 111, and the other side is connected to the substrate layer 101 around the first type doped well 111.
  • the isolation structure 401 there may be a certain distance between the isolation structure 401 and the edge of the first type doped well 111, and the distance between the first type doped well 111 and the isolation structure 401 may also be a certain distance.
  • Substrate material with partial thickness. The isolation structure 401 is used to achieve isolation between a region surrounded by the isolation structure 401 and a substrate material around the isolation structure 401.
  • the isolation structure 401 is used as a physical isolation structure, which can avoid leakage problems between the first doped well 111 and the substrate layer 101 around the isolation structure 401, and further Improve memory performance. Because the first-type doped well 111 is physically isolated from the peripheral substrate layer 101 through the isolation structure 401, there is no need for isolation through a depletion layer. Therefore, the second surface 12 of the substrate layer 101 can be thinned to expose the bottom surface of the first type doped well 111.
  • a substrate material with a partial thickness is further provided between the bottom surface of the first type doped well 111 and the second surface 12, and the bottom surface of the first type doped well 111
  • the distance from the second surface 12 is small, for example, it can be less than 1 ⁇ m, so the thickness of the substrate layer 101 is low.
  • a first contact portion 123 is formed in the storage layer 102 for connecting to the first type doped well 111, and the first contact 123 portion is located in the first type doped well surrounded by the isolation structure 401.
  • the top surface of 111 is formed in the storage layer 102 for connecting to the first type doped well 111, and the first contact 123 portion is located in the first type doped well surrounded by the isolation structure 401. The top surface of 111.
  • the storage structure further includes a second contact portion penetrating the dielectric layer 103 and the substrate layer 101.
  • the second contact portion includes a metal pillar 403 and an insulating sidewall 402 located on a sidewall surface of the metal pillar 403.
  • the material of the metal pillar 403 may be a metal material such as W, Cu, Al, or Au.
  • the metal pillar 403 is connected to the through-array contact portion 121 to achieve connection with a memory circuit in the memory layer 102.
  • the isolation structure 401 and the second contact portion penetrate the dielectric layer 103 and the substrate layer 101, the dielectric layer 103 and the substrate layer 101 can be etched to form an isolation trench and a contact hole at the same time, and then the At the same time when the side wall 402 is insulated, an isolation structure 401 filling the isolation trench is formed without adding additional process steps.
  • the surface of the dielectric layer 103 may further have solder pads or other electrical connection structures connected to the metal pillars 403. Because in this specific implementation manner, an isolation structure 401 is formed in the substrate layer 101 as a physical isolation structure between the doped well and the surrounding substrate, therefore, the bottom of the doped well does not need to have a thick substrate, so that The overall thickness of the substrate layer 101 is relatively low, so that the parasitic capacitance between the pads or other electrical connection structures formed on the dielectric layer 103 and the device layer 102 can be reduced, and the performance of the memory structure can be improved.
  • the storage layer 102 also has a second substrate 200 on the surface, and peripheral circuits are formed in the second substrate 200.
  • the second substrate 200 is located on the surface of the storage layer 102.
  • the peripheral circuits in the second substrate 200 and Electrical connections are formed between the memory circuits in the memory layer 102.
  • the surface of the second substrate 200 facing the storage layer 102 exposes the surface of the connection portion of the peripheral circuit
  • the surface of the storage layer 102 exposes the surface of the connection portion of the storage circuit. The two are bonded to form Electrical connection.
  • FIG. 7 is a schematic structural diagram of a storage structure according to another embodiment of the present invention.
  • the storage structure includes: a first substrate 700.
  • the first substrate 700 includes a substrate layer 701 and a storage layer 702.
  • the substrate layer 701 has a first surface and a second surface opposite to each other.
  • the storage layer 702 is located on the first surface of the substrate layer 701, and the substrate layer 701 has a doped well therein; an isolation structure 710 penetrates the substrate layer 701 and is located at an edge of the doped well, and is used for isolation.
  • the doped well and the surrounding substrate layer 701. In FIG. 7, the first substrate 700 is in an upright state.
  • a plurality of doped wells are formed in the substrate layer 701.
  • the doped wells include a first type doped well 711 and a second type doped well 712 located in the first type doped well 711.
  • the surface of the doped well is coplanar with the first surface of the substrate layer 701.
  • the doped well bottom has a substrate layer 701 with a certain thickness.
  • the memory layer 702 includes an insulating layer, a memory cell formed in the insulating layer, and a memory circuit connected to the memory cell.
  • a 3D NAND memory cell is formed in the memory layer 702, and the memory cells are all formed on the surface of the second type doped well 712.
  • a through-array contact portion 721 penetrating the memory cell is also formed in the storage layer 702, and the through-array contact portion 721 is connected to the second type doped well 712; a first layer is also formed in the storage layer 702. A contact portion 722 is connected to the first type doped well 711. A substrate contact portion 723 is also formed in the memory layer 702, and is used to connect to the substrate layer 701. A circuit connection portion 724 is also formed in the storage layer 702, and is configured to lead out a storage circuit in the storage layer 702.
  • the first substrate 700 further includes a dielectric layer 703 on the second surface of the substrate layer 701.
  • the dielectric layer 703 serves as a passivation layer on the second surface of the substrate layer 701 and is used to protect the second surface of the substrate layer 701.
  • the isolation structure 710 penetrates the dielectric layer 703 and the substrate layer 701.
  • One side of the isolation structure 710 is connected to the first type doped well 711, surrounds the first type doped well 711 and the second type doped well 712, and is isolated from the substrate layer 701 around the isolation structure 710.
  • a first contact portion 722 connected to the first-type doped well 711 is located on a surface of the first-type doped well 111 surrounded by the isolation structure 401.
  • the storage structure further includes a second contact portion penetrating the dielectric layer 703 and the substrate layer 701.
  • the second contact portion includes a metal pillar 731 and an insulating side wall 732 located on a sidewall surface of the metal pillar 731.
  • the metal pillar 731 is connected to the circuit connection portion 724 in the storage layer 702 to implement connection with a storage circuit in the storage layer 702.
  • the storage structure further includes a second contact portion connected to the through-array contact portion 721, the first contact portion 722, and the substrate contact portion 723.
  • the storage layer 702 also has a second substrate 800 on the surface, and peripheral circuits are formed in the second substrate 800.
  • the second substrate 800 is located on the surface of the storage layer 702, and the peripheral circuits in the second substrate 800 and Electrical connections are formed between the memory circuits in the memory layer 702.
  • the surface of the second substrate 800 facing the storage layer 702 exposes the surface of the connection portion of the peripheral circuit
  • the surface of the storage layer 702 exposes the surface of the connection portion of the storage circuit. The two are bonded to form Electrical connection.

Abstract

本发明涉及一种存储器结构及其形成方法，所述存储器结构包括：第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述衬底层内具有掺杂阱；隔离结构，贯穿所述衬底层，且位于所述掺杂阱边缘，用于隔离所述掺杂阱与周围的衬底层。所述存储器结构能够避免掺杂阱与衬底层之间的漏电，提高性能。

Description

存储器结构及其形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种存储器结构及其形成方法。
背景技术
近年来，闪存(Flash Memory)存储器的发展尤为迅速。闪存存储器的主要特点是在不加电的情况下能长期保持存储的信息，且具有集成度高、存取速度快、易于擦除和重写等优点，因而在微机、自动化控制等多项领域得到了广泛的应用。为了进一步提高闪存存储器的位密度(Bit Density)，同时减少位成本(Bit Cost)，三维的闪存存储器(3D NAND)技术得到了迅速发展。
在3D NAND闪存结构中，包括存储阵列结构以及位于存储阵列结构上方的CMOS电路结构，所述存储阵列结构和CMOS电路结构通常分别形成于两个不同的晶圆上，然后通过键合方式，将CMOS电路晶圆键合到存储整列结构上方，将CMOS电路和存储阵列电路连接在一起；然后再将存储阵列结构所在晶圆的背面减薄，通过贯穿背面的接触部将整个电路接出。当背面减薄过程中，碰到晶圆内的深掺杂阱或者深掺杂阱下方保留的衬底厚度过小，会导致深掺杂阱与衬底之间产生严重的漏电。
现有技术中，一般通过严格控制掺杂阱的深度以及在深掺杂阱下方保留足够的衬底厚度来减小漏电流。但是，现有技术防止漏电流的方法需要严格控制工艺过程，导致工艺的有效窗口较小，工艺的偏差可能导致晶圆的大宗报废。而且，由于电路的接出，需要打通背面的硅形成穿通接触部，增加掺杂阱下方保留的厚度会导致穿通接触部的深宽比增加，增加工艺的难度。更进一步的，掺杂阱下方保留的衬底厚度增大，会导致接出电路的焊垫的寄生电容增大，影响产品的性能。
发明内容
本发明所要解决的技术问题是，提供一种存储器结构及其形成方法，避免掺杂阱与衬底之间产生漏电。
本发明的技术方案提供一种存储器结构，包括：第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述衬底层内具有掺杂阱；隔离结构，贯穿所述衬底层，且位于所述掺杂阱边缘，包围所述掺杂阱设置，用于隔离所述掺杂阱与所述隔离结构外围的衬底层。
可选的，所述隔离结构的至少一侧侧壁与所述掺杂阱连接。
可选的，所述存储层内形成有第一接触部，用于连接至所述第一类型掺杂阱，所述第一接触部位于被所述隔离结构包围的第一类型掺杂阱表面。
可选的，所述隔离结构包括贯穿所述衬底层的隔离沟槽和填充满所述隔离沟槽的隔离材料。
可选的，所述第一基底还包括位于所述衬底层的第二表面上的介质层，所述隔离结构还贯穿所述介质层。
可选的，还包括：贯穿所述介质层和衬底层的第二接触部，所述第二接触部包括金属柱以及位于所述金属柱侧壁表面的绝缘侧墙。
可选的，所述掺杂阱底部位于所述衬底层内，与所述衬底层的第二表面之间具有一间距。
可选的，所述衬底层的第二表面暴露出所述掺杂阱的底部表面。
可选的，所述掺杂阱包括第一类型掺杂阱以及位于所述第一类型掺杂阱内的第二类型掺杂阱。
可选的，还包括：第二基底，所述第二基底内形成有外围电路；所述第二基底位于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
为解决上述问题，本发明的具体实施方式还提供一种存储器结构的形成方法，包括：提供第一基底，包括衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述衬底层内具有掺杂阱；形成贯穿所述衬底层的隔离结构，包围所述掺杂阱设置，用于隔离所述掺杂阱与所述隔离结构外围的衬底层。
可选的所述隔离结构的至少一侧侧壁与所述掺杂阱连接。
可选的，所述存储层内形成有第一接触部，用于连接至所述第一类型掺杂阱，所述第一接触部位于被所述隔离结构包围的第一类型掺杂阱表面。
可选的，形成贯穿所述衬底层的隔离结构的步骤进一步包括：形成贯穿所述衬底层的隔离沟槽，所述隔离沟槽位于所述掺杂阱边缘，围绕所述掺杂阱设置；形成填充满所述隔离沟槽的隔离材料。
可选的，还包括：在所述衬底层的第二表面上形成介质层，所述隔离结构还贯穿所述介质层。
可选的，还包括：形成贯穿所述介质层和衬底层的第二接触部。
可选的，所述第二接触部和隔离结构的形成方法包括：刻蚀所述介质层至所述衬底层，在所述介质层内形成第一开口和第二开口；沿所述第一开口和所述第二开口同时刻蚀所述衬底层，分别形成贯穿所述衬底层的隔离沟槽和接触孔；形成填充满所述隔离沟槽、第一开口以及覆盖所述接触孔和第二开口内壁表面的绝缘材料层；去除位于所述接触孔底部的绝缘材料层；形成填充满所述接触孔和第二开口的金属材料层，并以所述介质层为停止层对所述金属材料层进行平坦化。
可选的，所述掺杂阱底部位于所述衬底层内，与所述衬底层的第二表面之间具有一间距，或者所述衬底层的第二表面暴露出所述掺杂阱的底部表面。
可选的，所述掺杂阱包括第一类型掺杂阱以及位于所述第一类型掺杂阱内的第二类型掺杂阱。
可选的，所述存储层表面还具有第二基底，所述第二基底内形成有外围电路；所述第二基底位于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
本发明的存储器结构的衬底层内形成有隔离结构作为掺杂阱与周围衬底之间的物理隔离结构，可以避免所述掺杂阱与隔离结构外围的衬底层之间发生漏电问题，进而提高存储器的性能。所述掺杂阱底部无需具有较厚的衬底，使得所述衬底层整体厚度较低，从而可以降低介质层上形成的焊垫或其他电连接 结构与器件层之间的寄生电容，从而可以提高存储器结构的性能。
本发明的存储器结构的形成方法在形成贯穿衬底层连接至存储层的接触部的同时，形成位于所述掺杂阱与周围衬底之间的隔离结构，无需增加额外的工艺步骤，在不增加工艺成本的前提下，可以避免掺杂阱与周围衬底之间的漏电问题，有利于提高存储器结构的性能。
附图说明
图1至图6为本发明一具体实施方式的存储器结构的形成过程的结构示意图；
图7为本发明一具体实施方式的存储器结构的结构示意图。
具体实施方式
下面结合附图对本发明提供的存储器结构及其形成方法的具体实施方式做详细说明。
请参考图1至图6，为本发明一具体实施方式的存储器结构的形成过程的结构示意图。
请参考图1，提供第一基底100，包括：衬底层101和存储层102，所述衬底层101具有相对的第一表面11和第二表面12，所述存储层102位于所述衬底层101的第一表面11上，所述衬底层101内具有掺杂阱。
图1中，所述第一基底100处于倒置状态，此时，所述衬底层101的第一表面11为衬底层101的下表面，而第二表面12为衬底层101的上表面。所述存储层102覆盖所述衬底层101的第一表面11，在倒置状态下，相应的所述存储层102也位于所述衬底层101的下方。本发明的具体实施方式中，上、下、顶部、底部的相对位置描述均是相对第一基底100处于正置状态而言。
所述衬底层101为半导体材料层，可以为单晶硅晶圆、包括单晶硅晶圆以及晶圆表面的半导体外延层、或者绝缘体上硅衬底等。本具体实施方式中，所述衬底层101包括单晶硅晶圆以及位于所述单晶硅衬底表面的单晶硅外延层，所述单晶硅外延层表面为第一表面11，所述单晶硅晶圆另一侧表面为第二表面 12。
所述掺杂阱为对所述衬底层101的第一表面11进行离子掺杂而形成，根据离子掺杂的方向，靠近第一表面11处为掺杂阱的顶部，靠近第二表面12处为掺杂阱的底部。所述掺杂阱的顶部表面与所述衬底层101的第一表面11共面。在一个具体实施方式中，所述掺杂阱包括第一类型掺杂阱111以及位于所述第一类型掺杂阱111内的第二类型掺杂阱112。在一个具体实施方式中，所述第一类型掺杂阱111为N型掺杂阱，所述第二类型掺杂阱112为P型掺杂阱。更进一步的，所述第二类型掺杂阱112为P型掺杂阱，所述第一类型掺杂阱111包括位于所述P型掺杂阱两侧的N型掺杂阱以及位于所述N型掺杂阱和P型掺杂阱下方的N型深掺杂阱。
所述衬底层101内可以形成有多个掺杂阱，相邻掺杂阱之间具有一定间距。所述衬底层101可以为形成有掺杂阱的晶圆背面进行减薄而形成，根据减薄程度的不同，可以对掺杂阱底部与衬底层101的第二表面12之间的距离进行调整。
该具体实施方式中，所述衬底层101的第二表面12暴露出所述第一类型掺杂阱111的底部表面，在对晶圆背面进行减薄的过程中，减薄至暴露出所述第一类型掺杂阱111。
在另一具体实施方式中，所述第一类型掺杂阱111位于所述衬底层101内，第一类型掺杂阱111的底部表面与所述衬底层101的第二表面12之间具有一间距。所述第一类型掺杂阱111底部与所述衬底层101的第二表面12之间具有一定厚度的衬底。
所述存储层102包括绝缘层以及形成与所述绝缘层内的存储单元以及连接所述存储单元的存储电路。在一个具体实施方式中，所述存储层102内形成有3D NAND存储单元，且所述存储单元均形成于所述第二类型掺杂阱112的顶部表面。所述存储层102还包括贯穿所述存储单元的贯穿阵列接触部121以及连接所述阵列接触部121的互连层122。图1中，仅示出一个贯穿阵列接触部121以及部分互连层122，仅作为示意。在实际的存储器结构中，每个存储单元内可形成有多个所述贯穿阵列接触部121。
该具体实施方式中，所述第一基底100还包括位于所述衬底层101第二表面12上的介质层103。所述介质层103作为覆盖所述衬底层101第二表面12的钝化层，用于保护所述衬底层101的第二表面12。所述介质层103的材料可以为TEOS、氮化硅、氮氧化硅、氧化硅等绝缘介质材料。所述介质层103可以为单层结构可以为多层堆叠结构。可以通过化学气相沉积工艺、旋涂工艺、原子层沉积工艺等各种沉积工艺形成所述介质层103。
所述存储层102与所述衬底层101相对的另一侧表面还与一第二基底200键合连接，所述第二基底200内形成有外围电路；所述第二基底200位于所述存储层102表面，所述第二基底200内的外围电路与所述存储层102内的存储电路之间形成电连接。具体的，所述第二基底200朝向所述存储层102的表面暴露出外围电路的连接部的表面，而所述存储层102的表面暴露出存储电路的连接部表面，两者键合，形成电连接。
请参考图2，刻蚀所述介质层103至所述衬底层101的第二表面12，在所述介质层103内形成第一开口131和第二开口132。
具体的，所述第一开口131和第二开口132的形成方法包括：在所述介质层103表面形成光刻胶层，采用一光罩对所述光刻胶层进行曝光显影，形成图形化的光刻胶层；以所述图形化光刻胶层为掩膜层，刻蚀所述介质层103，形成所述第一开口131和第二开口132。所述第一开口131用来定义后续待形成的隔离结构的位置和尺寸，所述第二开口132用于定义后续待形成的贯穿所述衬底层101的接触部的位置和尺寸。采用同一光罩进行光刻工艺在介质层103上形成图形化光刻胶层，再刻蚀介质层103，同时形成所述第二开口132和第一开口131，无需针对隔离结构额外增加工艺步骤。
所述第一开口131为一环形沟槽状；所述第二开口132为孔状，横截面可以为圆形、矩形或多边形等。
请参考图3，沿所述第一开口131和所述第二开口132同时刻蚀所述衬底层101，分别形成贯穿所述衬底层101的隔离沟槽113和接触孔114。
所述接触孔114底部暴露出所述存储层102内的电连接结构，后续在所述接触孔114内形成贯穿衬底层101的第二接触部，与所述存储层102内的电连 接结构连接。该具体实施方式中，仅示出了形成一个接触孔114，所述接触孔114穿过所述掺杂阱，底部暴露出所述存储层102内的贯穿阵列接触部121。在其他具体实施方式中，可以形成多个接触孔114，部分接触孔114可以位于所述掺杂阱外围，暴露出存储单元外部的电连接结构。
所述隔离沟槽113的至少一侧侧壁与所述掺杂阱连接。所述隔离沟槽113位于所述掺杂阱边缘，围绕所述掺杂阱设置。该具体实施方式中，所述隔离沟槽113位于所述第一类型掺杂阱111内，所述隔离沟槽113的两侧侧壁均暴露出所述第一类型掺杂阱111。在另一具体实施方式中，所述隔离沟槽113仅一侧侧壁暴露出所述第一类型掺杂阱111，而另一侧侧壁暴露出衬底层101。
在另一具体实施方式中，所述隔离沟槽113与所述第一类型掺杂阱111边缘之间还可以具有一定间距，所述第一类型掺杂阱111与后续在所述隔离沟槽113内形成的隔离结构之间具有部分厚度的硅。虽然后续在隔离沟槽113内形成的隔离结构与所述第一类型掺杂阱111之间具有部分衬底材料，但是由于存储器在工作过程中，将隔离沟槽113外围的衬底层101接地，因此，所述隔离结构与所述第一类型掺杂阱111之间部分衬底层101不会形成导电通路，因此也不会造成漏电。
所述隔离沟槽113的宽度小于所述接触孔114的宽度。在本发明的一个具体实施方式中，所述隔离沟槽113的宽度为小于接触孔114的孔径宽度的一半，且大于20nm，所述接触孔114的孔径最大宽度为1500nm。
请参考图4，形成填充满所述隔离沟槽113、第一开口131以及覆盖所述接触孔114和第二开口132内壁表面的绝缘材料层400。
所述绝缘材料层400的材料可以为氧化硅、氮氧化硅或氮化硅等绝缘介质材料。可以采用化学气相沉积工艺、原子层沉积工艺、等离子体增强化学气相沉积工艺等形成所述绝缘材料层400。由于所述隔离沟槽113的宽度小于所述接触孔114的直径，所述绝缘材料层400填充满所述隔离沟槽113和第一开口131时，所述绝缘材料层400仅覆盖所述接触孔114和第二开口132的内壁表面。
所述绝缘材料层400还覆盖所述介质层103的表面。
请参考图5，去除位于所述接触孔114底部的绝缘材料层400，形成覆盖所述接触孔114和第二开口132侧壁的绝缘侧墙402，填充于所述隔离沟槽113和第一开口131内的绝缘材料层作为隔离结构401。
采用各向异性刻蚀工艺去除位于所述接触孔114底部的绝缘材料层400。在去除所述接触孔114底部的绝缘材料层400的同时，还将位于所述介质层103表面的绝缘材料层400去除。在其他具体实施方式中，去除位于所述接触孔114底部的绝缘材料层400之后，所述介质层103表面还剩余部分厚度的绝缘材料层400。
所述隔离结构401的至少一个侧壁与所述掺杂阱连接。该具体实施方式中，所述隔离结构401完全位于所述第一类型掺杂阱111内，靠近所述第一类型掺杂阱111的边缘，因此，所述隔离结构401的两个侧壁均与所述第一类型掺杂阱111连接，大部分第一类型掺杂阱111以及第二类型掺杂阱112被所述隔离结构401包围，被所述隔离结构401包围的掺杂阱区域与周围的衬底层101之间通过所述隔离结构401实现物理隔离。
在另一具体实施方式中，所述隔离结构401的一侧侧壁与所述第一类型掺杂阱111连接，另一侧连接至所述第一类型掺杂阱111外围的衬底层101。
在另一具体实施方式中，所述隔离结构401与所述第一类型掺杂阱111边缘之间还可以具有一定间距，所述第一类型掺杂阱111与所述隔离结构401之间还具有部分厚度的衬底材料。所述隔离结构401用于实现被所述隔离结构401包围的区域与隔离结构401外围的衬底材料之间的隔离。
由于存储器在工作状态时，所述衬底层101接地，所述隔离结构401作为物理隔离结构，可以避免所述第一掺杂阱111与隔离结构401外围的衬底层101之间发生漏电问题，进而提高存储器的性能。
虽然所述第一类型掺杂阱111与周围的衬底层101直接接触会形成耗尽层，可以减少漏电，但是所述耗尽层需要有足够的厚度才能够完全避免漏电的产生。这种情况下，需要所述第一类型掺杂阱111外围需要有较大厚度的未掺杂衬底，因此，要求衬底层的厚度较大。而本发明的具体实施方式中，由于所述第一类型掺杂阱111通过隔离结构401与外围的衬底层101之间进行物理隔 离，无需再通过耗尽层进行隔离。因此，所述衬底层101的第二表面12可以被减薄至暴露出所述第一类型掺杂阱111的底部表面。在其他具体实施方式中，所述第一类型掺杂阱111的底部表面与所述第二表面12之间还具有部分厚度的衬底材料，且所述第一类型掺杂阱111的底部表面与所述第二表面12之间的距离较小，例如可以小于1μm，因此所述衬底层101的厚度较低。
该具体实施方式中，在形成所述绝缘侧墙402的过程中，形成所述隔离结构401，无需增加额外的工艺步骤。
所述存储层102内还可以形成有连接所述第一类型掺杂阱111的第一接触部123，所述第一接触部123位于被所述隔离结构401包围的第一类型掺杂阱111的顶部表面。
请参考图6，形成填充满所述接触孔114和第二开口132的金属材料层，并以所述介质层102为停止层进行平坦化，形成位于所述接触孔114和第二开口132内的金属柱403。所述绝缘侧墙402和金属柱403构成第二接触部。
所述金属材料层的材料可以为W、Cu、Al、Au等金属材料。可以采用物理气相沉积工艺，例如溅射工艺，形成所述金属材料层。
对所述金属材料层进行平坦化，去除位于介质层103表面的金属材料层，形成金属柱403，所述金属柱403连接至所述存储层102内的贯穿阵列接触部121，实现与所述存储层102内的存储电路的连接。
后续还包括在所述介质层103表面形成连接至所述金属柱403的焊垫或其他电连接结构。由于该具体实施方式中，所述衬底层101内形成有隔离结构401作为掺杂阱与周围衬底之间的物理隔离结构，因此，所述掺杂阱底部无需具有较厚的衬底，使得所述衬底层101整体厚度较低，从而可以降低介质层103上形成的焊垫或其他电连接结构与器件层102之间的寄生电容，从而可以提高存储器结构的性能。
在另一具体实施方式中，还可以在形成所述介质层103之前，先刻蚀所述衬底层101形成隔离沟槽，在所述隔离沟槽内填充满隔离材料，作为隔离结构；然后再在所述衬底层101第二表面12上形成介质层103，刻蚀所述介质层103和衬底层101，形成贯穿所述介质层103和衬底层101的接触孔，在所述接触 孔内壁表面形成绝缘侧墙402以及填充满所述接触孔的金属柱403。
本发明的具体实施方式还提供一种上述方法形成的存储结构。
请参考图6，为本发明一具体实施方式的存储结构的结构示意图。
所述存储结构包括：第一基底100，所述第一基底100包括：衬底层101和存储层102，所述衬底层101具有相对的第一表面11和第二表面12，所述存储层102位于所述衬底层101的第一表面11上，所述衬底层101内具有掺杂阱；隔离结构401，贯穿所述衬底层101，且位于所述掺杂阱边缘，用于隔离所述掺杂阱与周围的衬底层101。
所述衬底层101为半导体材料层，可以为单晶硅晶圆、包括单晶硅晶圆以及晶圆表面的半导体外延层、或者绝缘体上硅衬底等。本具体实施方式中，所述衬底层101包括单晶硅晶圆以及位于所述单晶硅衬底表面的单晶硅外延层，所述单晶硅外延层表面为第一表面11，所述单晶硅晶圆另一侧表面为第二表面12。
图1中，所述第一基底100处于倒置状态，此时，所述衬底层101的第一表面11为衬底层101的下表面，而第二表面12为衬底层101的上表面。所述存储层102覆盖所述衬底层101的第一表面11，在倒置状态下，相应的所述存储层102也位于所述衬底层101的下方。
所述掺杂阱为对所述衬底层101的第一表面11进行离子掺杂而形成，根据离子掺杂的方向，靠近第一表面11处为掺杂阱的顶部，靠近第二表面12处为掺杂阱的底部。所述掺杂阱的顶部表面与所述衬底层101的第一表面11共面。在一个具体实施方式中，所述掺杂阱包括第一类型掺杂阱111以及位于所述第一类型掺杂阱111内的第二类型掺杂阱112。在一个具体实施方式中，所述第一类型掺杂阱111为N型掺杂阱，所述第二类型掺杂阱112为P型掺杂阱。更进一步的，所述第二类型掺杂阱112为P型掺杂阱，所述第一类型掺杂阱111包括位于所述P型掺杂阱两侧的N型掺杂阱以及位于所述N型掺杂阱和P型掺杂阱下方的N型深掺杂阱。
所述衬底层101内可以形成有多个掺杂阱，相邻掺杂阱之间具有一定间距。所述衬底层101可以为形成有掺杂阱的晶圆背面进行减薄而形成，根据减薄程 度的不同，可以对掺杂阱底部与衬底层101的第二表面之间的距离进行调整。
该具体实施方式中，所述衬底层101的第二表面12暴露出所述第一类型掺杂阱111的底部表面。在对晶圆背面进行减薄的过程中，减薄至暴露出所述第一类型掺杂阱111。
在另一具体实施方式中，所述第一类型掺杂阱111位于所述衬底层101内，第一类型掺杂阱111的底部表面与所述衬底层101的第二表面12之间具有一间距。所述第一类型掺杂阱111底部与所述衬底层101的第二表面12之间具有一定厚度的衬底材料。
所述存储层102包括绝缘层以及形成与所述绝缘层内的存储单元以及连接所述存储单元的存储电路。在一个具体实施方式中，所述存储层102内形成有3D NAND存储单元，且所述存储单元均形成于所述第二类型掺杂阱112表面。所述存储层102还包括贯穿所述存储单元的贯穿阵列接触部121以及贯穿所述阵列接触部121的互连层122。图1中，仅示出一个贯穿阵列接触部121以及部分互连层122作为示意。在实际的存储器结构中，每个存储单元内可形成有多个所述贯穿阵列接触部121。
该具体实施方式中，所述第一基底100还包括位于所述衬底层101第二表面12上的介质层103。所述介质层103作为所述衬底层101第二表面12上的钝化层，用于保护所述衬底层101的第二表面12。所述介质层103的材料可以为TEOS、氮化硅、氮氧化硅、氧化硅等绝缘介质材料。所述介质层103可以为单层结构可以为多层堆叠结构。可以通过化学气相沉积工艺、旋涂工艺、原子层沉积工艺等各种沉积工艺形成所述介质层103。
所述隔离结构401包括贯穿所述衬底层101的隔离沟槽和填充满所述隔离沟槽的隔离材料。该具体实施方式中，所述隔离结构401还贯穿所述介质层103。在另一具体实施方式中，所述隔离结构401还可以仅位于所述衬底层101内。
所述隔离结构401的至少一侧侧壁与所述掺杂阱连接。该具体实施方式中，所述隔离结构401完全位于所述第一类型掺杂阱111内，靠近所述第一类型掺杂阱111的边缘，因此，所述隔离结构401的两个侧壁均与所述第一类型掺杂 阱111连接，大部分第一类型掺杂阱111以及第二类型掺杂阱112被所述隔离结构401包围，被所述隔离结构401包围的掺杂阱区域与周围的衬底层101之间通过所述隔离结构401实现物理隔离。
在另一具体实施方式中，所述隔离结构401的一侧侧壁与所述第一类型掺杂阱111连接，另一侧连接至所述第一类型掺杂阱111外围的衬底层101。
在另一具体实施方式中，所述隔离结构401与所述第一类型掺杂阱111边缘之间还可以具有一定间距，所述第一类型掺杂阱111与所述隔离结构401之间还具有部分厚度的衬底材料。所述隔离结构401用于实现被所述隔离结构401包围的区域与隔离结构401外围的衬底材料之间的隔离。
由于存储器在工作状态时，所述衬底层101接地，所述隔离结构401作为物理隔离结构，可以避免所述第一掺杂阱111与隔离结构401外围的衬底层101之间发生漏电问题，进而提高存储器的性能。由于所述第一类型掺杂阱111通过隔离结构401与外围的衬底层101之间进行物理隔离，无需再通过耗尽层进行隔离。因此，所述衬底层101的第二表面12可以被减薄至暴露出所述第一类型掺杂阱111的底部表面。在其他具体实施方式中，所述第一类型掺杂阱111的底部表面与所述第二表面12之间还具有部分厚度的衬底材料，且所述第一类型掺杂阱111的底部表面与所述第二表面12之间的距离较小，例如可以小于1μm，因此所述衬底层101的厚度较低。
所述存储层102内形成有第一接触部123，用于连接至所述第一类型掺杂阱111，所述第一接触123部位于被所述隔离结构401包围的第一类型掺杂阱111的顶部表面。
所述存储结构还包括：贯穿所述介质层103和衬底层101的第二接触部，所述第二接触部包括金属柱403以及位于所述金属柱403侧壁表面的绝缘侧墙402。所述金属柱403的材料可以为W、Cu、Al、Au等金属材料。所述金属柱403连接至所述贯穿阵列接触部121，实现与所述存储层102内的存储电路的连接。
由于所述隔离结构401和第二接触部贯穿所述介质层103和衬底层101，因此，可以通过刻蚀介质层103和衬底层101，同时形成隔离沟槽和接触孔， 然后在形成所述绝缘侧墙402的同时，形成填充所述隔离沟槽的隔离结构401，无需增加额外工艺步骤。
所述介质层103表面还可以具有连接至所述金属柱403的焊垫或其他电连接结构。由于该具体实施方式中，所述衬底层101内形成有隔离结构401作为掺杂阱与周围衬底之间的物理隔离结构，因此，所述掺杂阱底部无需具有较厚的衬底，使得所述衬底层101整体厚度较低，从而可以降低介质层103上形成的焊垫或其他电连接结构与器件层102之间的寄生电容，从而可以提高存储器结构的性能。
所述存储层102表面还具有第二基底200，所述第二基底200内形成有外围电路；所述第二基底200位于所述存储层102表面，所述第二基底200内的外围电路与所述存储层102内的存储电路之间形成电连接。具体的，所述第二基底200朝向所述存储层102的表面暴露出外围电路的连接部的表面，而所述存储层102的表面暴露出存储电路的连接部表面，两者键合，形成电连接。
请参考图7，为本发明另一具体实施方式的存储结构的结构示意图。
该具体实施方式中，所述存储结构包括：第一基底700，所述第一基底700包括：衬底层701和存储层702，所述衬底层701具有相对的第一表面和第二表面，所述存储层702位于所述衬底层701的第一表面上，所述衬底层701内具有掺杂阱；隔离结构710，贯穿所述衬底层701，且位于所述掺杂阱边缘，用于隔离所述掺杂阱与周围的衬底层701。图7中，所述第一基底700处于正置状态。
所述衬底层701内形成有多个掺杂阱，所述掺杂阱包括第一类型掺杂阱711以及位于所述第一类型掺杂阱711内的第二类型掺杂阱712。所述掺杂阱表面与所述衬底层701的第一表面共面。所述掺杂阱底部具有一定厚度的衬底层701。
所述存储层702包括绝缘层以及形成与所述绝缘层内的存储单元以及连接所述存储单元的存储电路。所述存储层702内形成有3D NAND存储单元，且所述存储单元均形成于所述第二类型掺杂阱712表面。
所述存储层702内还形成有贯穿所述存储单元的贯穿阵列接触部721，所 述贯穿阵列接触部721连接至所述第二类型掺杂阱712；所述存储层702内还形成有第一接触部722，连接至所述第一类型掺杂阱711；所述存储层702内还形成有衬底接触部723，用于连接至所述衬底层701。所述存储层702内还形成有电路连接部724，用于将所述存储层702内的存储电路引出。
所述第一基底700还包括位于所述衬底层701第二表面上的介质层703。所述介质层703作为所述衬底层701第二表面上的钝化层，用于保护所述衬底层701的第二表面。
所述隔离结构710贯穿所述介质层703和衬底层701。所述隔离结构710的一侧与第一类型掺杂阱711连接，将所述第一类型掺杂阱711和第二类型掺杂阱712包围，与所述隔离结构710外围的衬底层701隔离。连接所述第一类型掺杂阱711的第一接触部722位于被所述隔离结构401包围的第一类型掺杂阱111表面。
所述存储结构还包括：贯穿所述介质层703和衬底层701的第二接触部，所述第二接触部包括金属柱731以及位于所述金属柱731侧壁表面的绝缘侧墙732。所述金属柱731连接至所述存储层702内的电路连接部724，实现与所述存储层702内的存储电路的连接。在其他具体实施方式中，所述存储结构还包括连接至所述贯穿阵列接触部721、第一接触部722、衬底接触部723的第二接触部。
所述存储层702表面还具有第二基底800，所述第二基底800内形成有外围电路；所述第二基底800位于所述存储层702表面，所述第二基底800内的外围电路与所述存储层702内的存储电路之间形成电连接。具体的，所述第二基底800朝向所述存储层702的表面暴露出外围电路的连接部的表面，而所述存储层702的表面暴露出存储电路的连接部表面，两者键合，形成电连接。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种存储器结构，其特征在于，包括：
    第一基底，包括：衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述衬底层内具有掺杂阱；
    隔离结构，贯穿所述衬底层，且位于所述掺杂阱边缘，包围所述掺杂阱设置，用于隔离所述掺杂阱与所述隔离结构外围的衬底层。
  2. 根据权利要求1所述的存储器结构，其特征在于，所述隔离结构的至少一侧侧壁与所述掺杂阱连接。
  3. 根据权利要求1所述的存储器结构，其特征在于，所述存储层内形成有第一接触部，用于连接至所述第一类型掺杂阱，所述第一接触部位于被所述隔离结构包围的第一类型掺杂阱表面。
  4. 根据权利要求1所述的存储器结构，其特征在于，所述隔离结构包括贯穿所述衬底层的隔离沟槽和填充满所述隔离沟槽的隔离材料。
  5. 根据权利要求1所述的存储器结构，其特征在于，所述第一基底还包括位于所述衬底层的第二表面上的介质层，所述隔离结构还贯穿所述介质层。
  6. 根据权利要求5所述的存储器结构，其特征在于，还包括：贯穿所述介质层和衬底层的第二接触部，所述第二接触部包括金属柱以及位于所述金属柱侧壁表面的绝缘侧墙。
  7. 根据权利要求1所述的存储器结构，其特征在于，所述掺杂阱底部位于所述衬底层内，与所述衬底层的第二表面之间具有一间距。
  8. 根据权利要求1所述的存储器结构，其特征在于，所述衬底层的第二表面暴露出所述掺杂阱的底部表面。
  9. 根据权利要求1所述的存储器结构，其特征在于，所述掺杂阱包括第一类型掺杂阱以及位于所述第一类型掺杂阱内的第二类型掺杂阱。
  10. 根据权利要求1所述的存储器结构，其特征在于，还包括：第二基底，所述第二基底内形成有外围电路；所述第二基底位于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二 基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
  11. 一种存储器结构的形成方法，其特征在于，包括：
    提供第一基底，包括衬底层和存储层，所述衬底层具有相对的第一表面和第二表面，所述存储层位于所述衬底层的第一表面上，所述衬底层内具有掺杂阱；
    形成贯穿所述衬底层的隔离结构，所述隔离结构位于所述掺杂阱边缘，包围所述掺杂阱设置，用于隔离所述掺杂阱与所述隔离结构外围的衬底层。
  12. 根据权利要求11所述的存储器结构的形成方法，其特征在于，所述隔离结构的至少一侧侧壁与所述掺杂阱连接。
  13. 根据权利要求11所述的存储器结构的形成方法，其特征在于，所述存储层内形成有第一接触部，用于连接至所述第一类型掺杂阱，所述第一接触部位于被所述隔离结构包围的第一类型掺杂阱表面。
  14. 根据权利要求11所述的存储器结构的形成方法，其特征在于，形成贯穿所述衬底层的隔离结构的步骤进一步包括：形成贯穿所述衬底层的隔离沟槽，所述隔离沟槽位于所述掺杂阱边缘，围绕所述掺杂阱设置；形成填充满所述隔离沟槽的隔离材料。
  15. 根据权利要求11所述的存储器结构的形成方法，其特征在于，还包括：在所述衬底层的第二表面上形成介质层，所述隔离结构还贯穿所述介质层。
  16. 根据权利要求15所述的存储器结构的形成方法，其特征在于，还包括：形成贯穿所述介质层和衬底层的第二接触部。
  17. 根据权利要求16所述的存储器结构的形成方法，其特征在于，所述第二接触部和隔离结构的形成方法包括：刻蚀所述介质层至所述衬底层，在所述介质层内形成第一开口和第二开口；沿所述第一开口和所述第二开口同时刻蚀所述衬底层，分别形成贯穿所述衬底层的隔离沟槽和接触孔；形成填充满所述隔离沟槽、第一开口以及覆盖所述接触孔和第二开口内壁表面的绝缘材料层；去除位于所述接触孔底部的绝缘材料层；形成填充满所述接触孔和第二开口的金属材料层，并以所述介质层为停止层对所述金属材料 层进行平坦化。
  18. 根据权利要求11所述的存储器结构的形成方法，其特征在于，所述掺杂阱底部位于所述衬底层内，与所述衬底层的第二表面之间具有一间距，或者所述衬底层的第二表面暴露出所述掺杂阱的底部表面。
  19. 根据权利要求11所述的存储器结构的形成方法，其特征在于，所述掺杂阱包括第一类型掺杂阱以及位于所述第一类型掺杂阱内的第二类型掺杂阱。
  20. 根据权利要求11所述的存储器结构的形成方法，其特征在于，所述存储层表面还具有第二基底，所述第二基底内形成有外围电路；所述第二基底位于所述存储层表面，所述存储层内形成有存储单元和连接所述存储单元的存储电路结构，所述第二基底内的外围电路与所述存储层内的存储电路结构之间形成电连接。
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