CN109300846A - 用于产生表面电荷的包括压电衬垫的finfet装置及其制造方法 - Google Patents

用于产生表面电荷的包括压电衬垫的finfet装置及其制造方法 Download PDF

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CN109300846A
CN109300846A CN201810815983.2A CN201810815983A CN109300846A CN 109300846 A CN109300846 A CN 109300846A CN 201810815983 A CN201810815983 A CN 201810815983A CN 109300846 A CN109300846 A CN 109300846A
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fin
conformal
layer
material laying
piezoelectric material
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CN109300846B (zh
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高群
N·西迪基
安东尼·I·邱
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GlobalFoundries US Inc
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Abstract

本发明涉及用于产生表面电荷的包括压电衬垫的FINFET装置及其制造方法，揭示于本文的一例示方法包括，但不限于：形成共形压电材料衬垫层于鳍片的至少相对横向侧壁上，形成绝缘材料凹陷层于该鳍片的相对两边上以及于该共形压电材料衬垫层上，移除该共形压电材料衬垫层在该绝缘材料凹陷层之上的数个部分以藉此暴露该鳍片在该凹陷上表面之上的一部分，以及形成栅极结构于该绝缘材料凹陷层之上以及于该鳍片位在该凹陷上表面之上的一部分四周。

Description

用于产生表面电荷的包括压电衬垫的FINFET装置及其制造 方法
技术领域
本揭示内容大体有关于集成电路的制造，且更特别的是，有关于一种用于产生表面电荷的包括压电衬垫(liner)的FinFET装置及制造该装置的方法。
背景技术
在例如微处理器、储存装置及其类似者的现代集成电路中，有大量的电路组件，特别是场效应晶体管(FET)，装设并操作在有限的芯片区上。FET有各种不同组态，例如平面装置、FinFET装置、纳米线状装置等等。这些FET装置通常以切换模式操作，亦即，这些装置展现高度导电状态(导通状态)与高阻抗状态(关闭状态)。场效应晶体管的状态用栅极电极控制，栅极电极在施加适当的控制电压后控制形成在漏极区与源极区间的沟道区的导电系数。
与平面FET(如名称所意谓的，它是大体为平面的结构)相反，所谓FinFET装置有三维(3D)结构。图1的透视图图示形成于半导体衬底12之上的例示现有技术FinFET半导体装置10，以下会参考它以便以极高的水平来解释FinFET装置的一些基本特征。在此实施例中，FinFET装置10包括三个例示鳍片14、栅极结构16、侧壁间隔件18与栅极帽盖20。鳍片形成沟槽(fin-formation trench)22在衬底12中形成以界定鳍片14。绝缘材料凹陷层17位在栅极结构16下面以及在栅极结构外的区域中(亦即，在装置10的源极/漏极区中)的鳍片14之间。栅极结构16通常由下列构成：一层栅极绝缘材料(未单独图示)，例如，一层高k绝缘材料(k值为10或更大)或二氧化硅；以及一或多个导电材料层(例如，金属及/或多晶硅)，用作装置10的栅极电极。鳍片14有三维组态：高度H、宽度W及轴向长度L。轴向长度L对应至在装置10运行时电流在其中行进的方向，亦即，装置的栅极长度方向。鳍片14被栅极结构16覆盖的部分为FinFET装置10的沟道区。可使用所谓的“栅极优先”或“取代栅极”(栅极最后)制造技术来制造此类FinFET装置10的栅极结构16。FinFET装置可为三栅极或者是双栅极沟道区。对于既定的标地空间(plot space)(或占板面积(foot-print))，相比于平面晶体管装置，FinFET倾向于能够产生显著较大的驱动电流密度。
在块状半导体衬底上形成FinFET装置会遭遇的问题的一系列有关于在装置关闭时防止源极及漏极区之间的泄露电流，这被称为所谓的次临界(subthreshold)电压泄露电流。用以排除或减少此类不合意的次临界电压泄露电流的一现有技术努力成果是涉及执行离子布植工艺以形成反向掺杂(counter-doped)的击穿制止器(punch through stopper，PTS)区25。在形成栅极结构16前，沿着鳍片14的整个轴向长度形成此类PTS区25。就垂直位置来说，PTS区25通常刚好位在源极/漏极区(未图示)的接面深度下面，源极/漏极区形成于鳍片14在装置的源极/漏极区中露出绝缘材料凹陷层17的上表面之上的部分中。
就N型装置10而言，PTS区25通过植入P型掺杂物而建立，而就P型装置10而言，PTS区25通过植入N型掺杂物而建立。通常在形成鳍片14后且在形成栅极结构16前，立刻执行被执行用以建立PTS区25的植入工艺。不过，在通过执行离子布植工艺来形成PTS区25时，于主动鳍片14中形成在源极/漏极区下面定位准确的掺杂PTS区25极为困难。具体而言，在通过执行离子布植工艺来形成PTS区25时，不必要的掺杂物材料几乎总是会被引进鳍片14的主动区中。此外，，在形成PTS区25后将对装置执行的附加加热工艺会易于迫使掺杂物扩散且改变PTS掺杂区25的位置以及降低PTS区25相对于原始设计工艺所预期的掺杂物浓度。在此类情形下，需要微调用来形成PTS区25的离子布植工艺，而此种微调难以实现。如果来自反向掺杂的PTS区25的掺杂物在后续退火工艺期间扩散进入鳍片14，它会造成临界电压波动，因为反向掺杂物扩散进入不同装置的鳍片14的数量是随机的，这会严重危及电路效能。在理想的装置中，鳍片14中被栅极结构16覆盖的沟道部分中会有很少或几乎没有掺杂物材料。沟道中这种不必要的掺杂物材料会降低电荷载体在沟道区中的移动率且会在不同装置之间造成不必要的临界电压失配。
用于形成此类PTS区25的另一现有技术涉及沉积二氧化硅的固体硼(B)或磷(P)掺杂玻璃层或形成由邻近鳍片14的二氧化硅制成的掺杂间隔件，然后执行加热工艺以驱动玻璃材料层或间隔件中的掺杂物迁移至鳍片14中想要的位置。在执行掺杂物驱入工艺后，剥掉掺杂固体的玻璃层。此技术有良好的PTS位置控制且大致不会把有任何效能限制数量的被驱动掺杂物引进到主动鳍片14中。不过，执行此技术所需的精细掺杂浓度控制难以实现。此外，将被执行的后续热退火工艺也会不可避免地驱动掺杂物进入主动鳍片区，而造成临界电压失配与移动率劣化。
本揭示内容是针对用于产生表面电荷的包括压电衬垫的FinFET装置及制造该装置的方法，这可避免或至少减少上述问题中的一或多个影响。
发明内容
以下提出本发明的简化概要以提供本发明的一些方面的基本理解。此概要并非本发明的穷举式总览。它不是旨在确认本发明的关键或重要组件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细的说明的前言。
大体上，本揭示内容针对用于产生表面电荷的包括压电衬垫的FINFET装置及制造该装置的方法。揭示于本文的一例示方法包括，但不限于：形成包含相对横向侧壁的鳍片，形成共形压电材料衬垫层于该鳍片的至少相对横向侧壁上，以及在该鳍片的相对两边以及在该共形压电材料衬垫层上形成绝缘材料凹陷层于该鳍片形成沟槽中。在此实施例中，该方法进一步包括：移除共形压电材料衬垫层在绝缘材料凹陷层之上的部分以藉此暴露鳍片在凹陷上表面之上的一部分，以及形成栅极结构于绝缘材料凹陷层之上以及于鳍片在凹陷上表面之上的一部分四周。
揭示于本文的一例示FinFET装置包括，单不限于：鳍片，包含相对横向侧壁；绝缘材料凹陷层，位在邻近鳍片相对两边的沟槽中；以及非铁电压电材料衬垫层，位在鳍片的至少相对横向侧壁上且与鳍片的至少相对横向侧壁接触。在一例示实施例中，该非铁电压电材料衬垫层具有大约与绝缘材料凹陷层的高度齐平的上表面，而且该绝缘材料凹陷层位在该非铁电压电材料衬垫层与栅极结构上且与该非铁电压电材料衬垫层与栅极结构接触，该栅极结构位在鳍片的一部分四周且在绝缘材料凹陷层之上和在非铁电压电材料衬垫层的上表面之上。
附图说明
参考以下结合附图的说明可明白本揭示内容，其中类似的组件以相同的附图标记表示，且其中：
图1为例示现有技术FinFET装置的简图；以及
图2A至图2K图示揭示于本文用于产生表面电荷的包括压电衬垫的FINFET装置及制造该装置的方法的各种具体实施例。
尽管揭示于本文的专利目标容易做成各种修改及替代形式，然而本文仍以附图为例图示本发明的几个特定具体实施例且详述于本文。不过，应了解本文所描述的特定具体实施例并非旨在把本发明限定为本文所揭示的特定形式，反而是，本发明应涵盖落在如随附权利要求书所界定的本发明精神及范畴内的所有修改、等价及替代性陈述。
具体实施方式
以下描述本发明的各种例示具体实施例。为了清楚说明，本专利说明书没有描述实际具体实作的所有特征。当然，应了解，在开发任一此类的实际具体实施例时，必需做许多与具体实作有关的决策以达成开发人员的特定目标，例如遵循与系统相关及商务有关的限制，这些都会随着每一个具体实作而有所不同。此外，应了解，此类开发即复杂又花时间，但对本领域一般技术人员而言，在阅读本揭示内容后仍将如同例行工作一般。
此时以参照附图来描述本发明。例示图标于附图的各种结构、系统及装置仅供解释以及避免所属领域技术人员所现有的细节混淆本发明。尽管如此，仍纳入附图以描述及解释本揭示内容的例示实施例。应使用与相关领域技术人员所熟悉的意思一致的方式理解及解释用于本文的字汇及词组。本文没有特别定义的术语或词组(亦即，与所属领域技术人员所理解的普通惯用意思不同的定义)旨在用术语或词组的一致用法来说明。如果术语或词组旨在具有特定的意思时(亦即，不同于所属领域技术人员所理解的意思)，则会在本专利说明书中以直接明白地提供特定定义的方式清楚地陈述用于该术语或词组的特定定义。
本揭示内容针对包括压电衬垫的FINFET装置及制造该装置的方法。揭示于本文的方法及装置可使用各种技术来制造产品，例如NMOS、PMOS、CMOS等等，且可用来制造各种不同的不同装置，例如，内存产品、逻辑产品、ASIC等等。可使用“栅极优先”或者是“取代栅极”制造技术来形成用于该FinFET装置的栅极结构。因此，本发明不应被视为受限于晶体管装置的栅极结构的形成方式。当然，本发明不应被视为受限于图示及描述于本文的例示实施例。参考附图，此时会更详细地描述揭示于本文的方法及装置的各种例示具体实施例。可用任何各种不同的已知技术来形成描述于下文的各种材料层，例如化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺、热成长工艺、旋涂技术等等。此外，如本文及随附权利要求书中所使用者，用词“邻近”是要赋予宽广的解释且应被解释成可涵盖一特征与另一特征实际接触或与该另一特征靠得很近的情况。
图2A至图2K图示包括压电衬垫的FinFET装置100的各种实施例及制造该装置的方法。可形成有任何所欲个数的鳍片106的FinFET装置100。在图标于此的实施例中，FinFET装置100会被图标成由两个例示鳍片106构成。有些附图含有在图式中所截取的各种横截面图的简化平面图。参考图2A，视图X-X为穿过FinFET装置100的其中一个鳍片106与栅极结构110(在工艺此时，以虚线图标)(在对应至装置100的电流传送(栅极长度)方向的方向)所截取的横截面图。视图Y-Y为横过鳍片106穿过装置100的其中一个源极/漏极区(在对应至装置的栅极宽度方向的方向)所截取的横截面图。也应注意，在有些情形下，附图含有描绘以横截面图反映的加工的至少某些态样的简化平面图。不过，也应了解，无意用横截面图反映所有的加工步骤(及产生结构)以免使附图过于复杂。
参考图2A，会在块状半导体衬底102中及之上形成例示装置100。装置100可为N型装置或者是P型装置。另外，附图不描绘例如源极/漏极区、晕圈植入区、井区等等的各种掺杂区。衬底102可为块硅衬底或是它可由硅以外的材料制成。因此，应了解用语“衬底”或“半导体衬底”涵盖所有半导体材料。揭示于本文用于例示晶体管装置的栅极结构110可使用众所周知“栅极优先”或“取代栅极”制造技术形成。
图2A图示在执行数个工艺操作之后的装置100。首先，通过带图案鳍片形成蚀刻掩膜(patterned fin-formation etch mask)107执行一或多个蚀刻工艺，例如，各向异性蚀刻工艺，以在衬底102中形成多个鳍片形成沟槽104而藉此界定多个鳍片106。带图案鳍片形成蚀刻掩膜107可由一或多个材料层构成且可形成到任何所欲总厚度，例如，该带图案鳍片形成硬掩膜可由相对薄的二氧化硅层107A与相对较厚的氮化硅层107B构成。可通过沉积带图案鳍片形成蚀刻掩膜107的材料层(或数层)于衬底102的上表面之上，然后使用现有光刻及蚀刻技术图案化该(等)材料层，而形成带图案鳍片形成蚀刻掩膜107。
继续参考图2A，鳍片106的横向宽度及垂直高度106V(在沟槽104的底面之上)可随着特定应用而有所不同。另外，鳍片形成沟槽104及鳍片106的整体大小、形状及组态可随着特定应用而有所不同。在图示于附图的例示实施例中，鳍片形成沟槽104及鳍片106全都描绘成具有均匀的大小及形状。不过，沟槽104及鳍片106的大小及形状不需要有此均匀性才能实施揭示于本文的本发明的至少某些态样。在附图中，鳍片形成沟槽104描绘成已通过执行各向异性蚀刻工艺导致鳍片106的上半部有示意(且简化)图示的大体矩形组态，同时鳍片106的下半部向外变尖。鳍片106包含遍及其高度106V的相对横向侧壁106S与上表面106Z。因此，沟槽104及鳍片106的大小及组态与其制作方式不应被视为本发明的限制。
图2B图示在执行例如共形ALD或CVD工艺的共形沉积工艺以形成共形种子层111于鳍片106的侧壁106S上以及于沟槽104的底面104A上之后的装置100。在一例示实施例中，共形种子层111的形成可使用Huang等人描述于IEEE Electron Device Letters，33：516-18，2012的方法：“Effective Passivation of AlGaN/GaN HEMTs by ALD-Grown AlN ThinFilm,”(以下称为“Huang Publication”)，其全部内容并入本文作为参考资料。应注意，共形种子层111在形成装置100的任何栅极结构之前形成于鳍片106的整个轴向长度(在装置的栅极长度方向)上。共形种子层111的厚度可随着特定应用而有所不同(例如，0.5至5nm)且可由各种材料制成，例如氧化铝(Al2O3)、α-SiO2、蓝宝石等等。在金属兼容的情形下，可成长高度织构c轴AlN(highly textured c-axis AlN)于某些金属上，例如铂(111)、钛(0001)。用于形成该高度织构c轴AlN材料的例示技术描述于以下出版物，其全部内容并入本文作为参考资料：Martin等人在J.Vac.Sci.Technol.A，22(2)：361-64，2004出版的“Thickness dependence of the properties of highly c-axis textured AlN thinfilms”(以下称为“Martin Publication”)；Engelmark等人在J.Vac.Sci.Technol.A，19-2664-69，2001出版的“Structural and electroacoustic studies of A1N thin filmsduring low temperature radio frequency sputter deposition”(以下称为“EngelmarkPublication”)；以及Kirste等人在Applied Physics Letters，102：181913，2013出版的“Polarity control and growth of lateral polarity structures in AlN”(以下称为“Kirste Publication”)。
图2C图示在执行外延成长工艺以形成实质共形的压电材料衬垫层113于种子层111上之后的装置100。已报导有许多用于成长氮化铝的方法。最普遍的方法之一是脉冲直流磁控溅镀工艺(pulsed DC magnetron sputtering process，如在Martin Publication中所讨论及描述者)。此脉冲直流磁控溅镀工艺致能成长高度织构c轴定向膜于例如α-SiO2的衬底上。应注意，压电材料衬垫层113在形成装置100的任何栅极结构之前形成于鳍片106的整个轴向长度(在栅极长度方向)上。种子层111在图2C中简单地以虚线图示供参考用且后续的附图省略表示原始种子层111的虚线，因为它在形成压电材料衬垫层113期间可能会部分或全部被消耗掉。不论在形成压电材料衬垫层113后有没有原始种子层111，就本申请案及随附权利要求书的目的而言，压电材料衬垫层113应被理解为其形成于鳍片上并与鳍片接触。描述于本文的压电材料衬垫层113可由各种非铁电材料制成，例如氧化锌(ZnO)、氮化铝(AlN)、氮化镓(GaN)等等。在一特别实施例中，压电材料衬垫层113可由氧化锌构成且可使用蒸气-液体-固体(VLS)技术、水合化学成长(ACG)方法、或如Martin Publication所述通过执行脉冲直流磁控溅镀工艺来形成。压电材料衬垫层113的厚度可随着特定应用而有所不同(例如，2-3nm)。也应注意，可成长例如锆钛酸铅(lead zirconate titanate，PZT)、铌镁酸铅-钛酸铅(lead magnesium niobate-lead titanate，PMN-PT)的各种铁电材料于硅上。不过，使用该铁电材料会需要执行极化该铁电材料的额外步骤。
图2D图示在执行各向异性蚀刻工艺(RIE)以移除压电材料衬垫层113的所有实质水平部分之后的装置100。
图2E图示在执行数个工艺操作之后的装置100。首先，沉积一绝缘材料层115(例如，二氧化硅、HDP氧化物、氮化硅等等)以便过填鳍片形成沟槽104，使得它的刚沉积(as-deposited)上表面位在高于带图案蚀刻掩膜107的上表面之上的高度。之后，执行例如化学机械抛光(chemical mechanical polishing；CMP)工艺的至少一工艺操作以使用鳍片106的上表面106Z作为研磨终止来平坦化绝缘材料层115。此研磨工艺移除带图案鳍片形成蚀刻掩膜107。绝缘材料层115此时有研磨过的上表面115P。此工艺操作也从鳍片106此时被暴露的上表面106Z之上移除压电材料衬垫层113。
图2F图示在执行数个工艺操作之后的装置100。首先，在一具体实施例中，对绝缘材料层115执行定时凹陷蚀刻工艺以对于压电材料衬垫层113选择性地移除绝缘材料层115在沟槽内的部分。在凹陷蚀刻工艺完成时，绝缘材料层115有凹陷上表面115R。之后，对压电材料衬垫层113执行选择性凹陷蚀刻工艺以移除压电材料衬垫层113中在绝缘材料凹陷层115的凹陷上表面115R之上的部分。应注意，压电材料衬垫层113此时有大约与绝缘材料凹陷层115的凹陷上表面115R齐平的凹陷上表面113R。如图示，这些工艺操作导致有所欲数量119的鳍片106在绝缘材料凹陷层115的凹陷上表面115R之上暴露。鳍片106中被暴露的数量119可随着特定应用而有所不同。
图2G(视图X-X及Y-Y)及图2H(视图Z-Z)图示在具有栅极帽盖112的简化图标的栅极结构110形成于鳍片116之上之后以及在邻近栅极结构110的例示侧壁间隔件114形成之后的产品。视图Z-Z为在装置的栅极宽度(GW)方向穿过栅极结构110绘出的横截面图，如图2H的简化平面图所示。栅极结构110覆盖鳍片106中在操作期间会变成装置100的沟道区121的部分。也应注意，在大约与绝缘材料凹陷层115的凹陷上表面115R齐平的位置处，栅极结构110位在压电材料衬垫层113的凹陷上表面113R上且与其接触。
栅极结构110可为最终栅极结构(栅极优先工艺)或可为牺牲栅极结构(用于取代栅极工艺)。栅极结构110可由下列构成：栅极绝缘层(未单独图示)，例如二氧化硅或具有大于10的介电常数的高k材料；以与栅极电极，包含一或多个导电材料层(未单独图示)，例如，含金属材料。栅极帽盖112可由例如氮化硅的材料构成。为了形成侧壁间隔件114，执行例如共形ALD或CVD工艺的共形沉积工艺以形成遍及鳍片106与先前形成的栅极结构110与栅极帽盖112的间隔件材料共形层。然后，对该间隔件材料层执行各向异性蚀刻工艺。间隔件114可由各种材料制成，例如氮化硅等等。
在此时，通过执行传统制造技术可完成装置100，例如可执行各种离子布植工艺以至少在鳍片106位于装置100的源极/漏极区内的部分中形成各种掺杂区，可在装置的源极/漏极区中形成附加外延半导体材料(未图示)，可形成导电接触以建立通到源极/漏极区与栅极结构110等等的导电路径。
参考图2I，此时描述揭示于本文的新颖装置的各种操作方面。图2I为在装置的栅极宽度方向穿过栅极结构110所截取的横截面图(Z-Z)，其描绘装置100的沟道区。一般而言，绝缘材料层115具有刚沉积的内在拉伸应力(stress)，如双箭头115T所示。此拉伸应力115T的量值可随着绝缘材料层115的材料及其形成方式而有所不同。在绝缘材料层115为一层二氧化硅的例示实施例中，该层二氧化硅通过执行使用描述于Huang Publication的工艺的CVD工艺来形成，拉伸应力115T可约有300-500MPa的等级。
接着，绝缘材料层115中的拉伸应力115T对压电材料衬垫层113施加压缩应力，如箭头117所示。在暴露于充分的压缩应力时，压电材料衬垫层113会在鳍片106的外表面或其附近产生接口电荷或表面电荷层(未图示于图2I)，在此压电材料衬垫层113与鳍片106接触，亦即，在绝缘材料凹陷层115的凹陷上表面115R的高度之下延伸的鳍片106中。换言之，在绝缘材料层115的凹陷上表面115R的高度之上延伸的部分中，不会形成任何可察觉程度的接口电荷或表面电荷层。重要的是，会在鳍片106垂直地位于装置沟道区中的栅极结构110下方大约在凹陷上表面115R开始且向下伸入鳍片106至少到鳍片形成沟槽104的底部104A的部分中形成接口电荷层(接口电荷层)。同样，会在源极/漏极区下方且向下伸入鳍片106到鳍片形成沟槽104的底部104A的鳍片106中形成界面电荷层。由于通过对压电材料衬垫层113施加适当压缩应力来建立接口电荷层，所以接口电荷层是在绝缘材料凹陷层115形成于压电材料衬垫层113上时建立。需要施加至压电材料衬垫层113以达成在此所预测的结果的压缩应力量值可随着特定应用和使用于压电材料衬垫层113的材料而有所不同。在压电材料衬垫层113由AlN构成的一例示具体实施例中，施加至压电材料衬垫层113的压缩应力量值可至少约为200-500MPa以实现所需的表面电荷。
参考图2I，作为当今应用的一实施例，假设鳍片106的横向宽度106X(在栅极宽度方向)在大约与凹陷上表面115R齐平的位置处约有12纳米以及需要压电材料衬垫层113提供足以用作击穿制止区(punch-through stop)的电荷密度约为2e18cm-3，则源于压电材料衬垫层113的所需表面电荷密度需要约为0.00192C/m2(2e18*12e-7÷2)。在压电材料衬垫层113包含AlN或ZnO的情形下，在远低于200MPa的压缩应力程度可实现该表面电荷密度。
用来形成压电材料衬垫层113的外延成长工艺可用以下方式执行使得由压电材料衬垫层113产生的接口电荷层可以是带正电或者是带负电。为了在AlN中实现带正电或者是带负电的表面电荷，需要在铝极性(0001)或者是氮极性(000-1)方向的c轴取向。在AlN和GaN中的极性控制一直是活跃的研究领域。在一实施例中，如KirstePublication所述，AlN材料(和同一团队先前所研究的GaN材料)中的极性控制利用用以实现其中一种极性的低温缓冲层来实现，其中相反极性通过移除低温缓冲层来实现。同样地，铝极性层生长在仍有低温缓冲层处处，同时氮极性层生长在低温缓冲层被移除处。在另一实施例中，预沉积铝吸附原子(Al adatoms)以在Si(111)衬底上得到氮极性(000-1)AlN，同时用移除预沉积步骤来得到铝极性(0001)层，如Dasgupta等人描述于Applied Physics Letters，94：151906，2009的“Growth of high quality N-polar AlN(0001-)on Si(111)by plasma assistedmolecular beam epitaxy”(以下被称为“Dasgupta Publication”)，其全部内容并入本文作为参考资料。因此，需要结合c轴配向(c-axis aligned)的优先成长以得到压电响应。使用例如电浆辅助MOCVD或电浆增强直流磁控溅镀的方法得到高度织构膜。如上述，使用缓冲层，或吸附原子的预沉积，可反转此类膜的极性。
图2J图标FinFET装置100为P型装置且其中接口电荷层123经形成为施加以“+”符号表示的正接口电荷的例示实施例。图2K图标FinFET装置100为N型装置且其中接口电荷层123经形成为施加以“-”符号表示的负接口电荷的例示实施例。
所属领域技术人员在读完本申请后应了解，使用揭示于本文的装置及方法会让装置设计者在不形成掺杂击穿制止区于鳍片中的情况下有办法防止或减少不必要的击穿泄露电流，如本申请的【背景技术】中所描述者。如上述，因为压电材料衬垫层113是用沉积-蚀刻工艺的组合来形成，所以压电材料衬垫层113在鳍片106上可相对精确地定位在所欲位置，接着，相对于形成于在绝缘材料凹陷层115之上的鳍片中的掺杂源极/漏极区(未图示)的底部，此沉积-蚀刻工艺的组合应可更准确地安排界面电荷层123，此接口电荷层123的功能在于减少或排除次临界电流。所属领域技术人员在读完本申请后会明白使用揭示于本文的装置及方法的其他优点。
以基于CMOS的集成电路产品而言，各种加工操作有可能使用揭示于本文的方法及装置。在有些CMOS应用中，可能最好只在一种类型的装置上形成压电材料衬垫层113，例如，压电材料衬垫层113可以只形成于NFET装置上而不形成于PFET装置上。这可通过初始形成单一压电材料衬垫层113于N型及P型装置两者上然后形成覆盖N型装置且暴露P型装置的带图案掩膜层而实现。然后，可从P型装置移除压电材料衬垫层113的暴露部分。如果只想要在P型装置上而不是在N型装置上形成压电材料衬垫层113，工艺流程可反过来。
在希望形成合适的压电材料衬垫层113于P型及N型装置两者上的CMOS应用中，可使用以下工艺流程。可沉积第一压电材料衬垫层于两种类型的装置上，然后使用上述掩膜及蚀刻工艺从第一种装置上选择性地移除。之后，可沉积第二压电材料衬垫层于两种类型的装置上(包括第一压电材料衬垫层的剩余部分)。然后，可从第一压电材料衬垫层的剩余部分之上选择性地移除压电材料衬垫层的所欲部分，同时留下第二压电材料衬垫层位于第二种装置(与第一种装置相反)之上的部分。
以上所揭示的特定具体实施例均仅供图解说明，因为所属领域技术人员在受益于本文的教导后显然可以不同但等价的方式来修改及实施本发明。例如，可用不同的顺序完成以上所提出的工艺步骤。此外，除非在以下权利要求书有提及，不希望本发明受限于本文所示的构造或设计的细节。因此，显然可改变或修改以上所揭示的特定具体实施例而所有此类变体都被认为仍然是在本发明的范畴与精神内。应注意，在本申请说明书及随附权利要求书中为了描述各种工艺或结构而使用的例如“第一”、“第二”、“第三”或“第四”用语只是用来作为该步骤/结构的简写参考且不一定暗示该步骤/结构的进行/形成按照该有序序列。当然，取决于确切的权利要求语言，可能需要或不需要该工艺的有序序列。因此，本文提出以下的权利要求书寻求保护。

Claims (20)

1.一种形成FinFET装置的方法，包含：
在一半导体衬底中形成多个鳍片形成沟槽以藉此形成包含相对横向侧壁的鳍片；
至少在该鳍片的该相对横向侧壁上形成共形压电材料衬垫层；
形成绝缘材料凹陷层于该鳍片形成沟槽中以及于该共形压电材料衬垫层上，该绝缘材料凹陷层具有凹陷上表面；
移除该共形压电材料衬垫层在该凹陷上表面之上的数个部分以藉此暴露该鳍片在该凹陷上表面之上的一部分；以及
形成栅极结构于该凹陷上表面之上以及于该鳍片在该凹陷上表面之上的一部分四周。
2.如权利要求1所述的方法，其中，形成该共形压电材料衬垫层包含：
执行共形沉积工艺以形成共形种子层材料于该鳍片形成沟槽中以及至少于该鳍片的该相对侧壁上；以及
执行至少一外延成长工艺以形成该共形压电材料衬垫层于该共形种子层上，其中，该共形压电材料衬垫层包含非铁电材料。
3.如权利要求1所述的方法，其中，形成该共形压电材料衬垫层包含：形成该共形压电材料衬垫层于在该鳍片的上表面之上的带图案蚀刻掩膜的上表面之上。
4.如权利要求1所述的方法，其中，形成该栅极结构于该凹陷上表面之上包含：形成该栅极结构于该共形压电材料衬垫层的上表面上且与该共形压电材料衬垫层的该上表面接触，该共形压电材料衬垫层的该上表面位在大约与该绝缘材料凹陷层的该凹陷上表面的高度齐平的位置处。
5.如权利要求4所述的方法，其中，形成该栅极结构于该绝缘材料凹陷层的该凹陷上表面之上包含：形成该栅极结构于该鳍片的上表面上且与该鳍片的该上表面接触。
6.如权利要求1所述的方法，其中，该FinFET装置为N型装置，以及其中，形成该共形压电材料衬垫层包含：形成该共形压电材料衬垫层致使该共形压电材料衬垫层在经受压缩应力时产生带负电接口电荷层。
7.如权利要求1所述的方法，其中，该FinFET装置为P型装置，以及其中，形成该共形压电材料衬垫层包含：形成该共形压电材料衬垫层致使该共形压电材料衬垫层在经受压缩应力时产生带正电接口电荷层。
8.如权利要求2所述的方法，其中，该共形种子层材料包含氧化铝(Al2O3)、α-SiO2或蓝宝石中的一者，该共形压电材料衬垫包含氧化锌(ZnO)、氮化铝(AlN)或氮化镓(GaN)中的一者，以及该绝缘材料凹陷层包含二氧化硅或氮化硅中的一者。
9.如权利要求1所述的方法，其中，形成该绝缘材料凹陷层于该沟槽中包含：形成受拉伸应力的绝缘材料凹陷层。
10.如权利要求1所述的方法，其中，形成该共形压电材料衬垫层包含：形成该共形压电材料衬垫层至少于该鳍片的该相对横向侧壁上以及于该鳍片形成沟槽的底面上，且其中，该方法进一步包含：执行各向异性蚀刻工艺以实质移除在该鳍片形成沟槽的该底面上的所有该共形压电材料衬垫层，同时留下该共形压电材料衬垫层至少在该鳍片的该相对横向侧壁上的部分。
11.如权利要求3所述的方法，其中，形成该绝缘材料凹陷层于该沟槽中包含：
沉积一绝缘材料层以便过填该鳍片形成沟槽，所沉积的该绝缘材料层具有一刚沉积上表面，该刚沉积上表面的高度高于该带图案蚀刻掩膜的该上表面的高度；以及
执行至少一化学机械抛光工艺以移除位于该鳍片的该上表面之上的该带图案蚀刻掩膜以及移除该共形压电材料衬垫层高于该鳍片的该上表面的高度的部分。
12.如权利要求1所述的方法，其中，该共形压电材料衬垫层包含非铁电材料。
13.一种形成FinFET装置的方法，包含：
在半导体衬底中形成多个鳍片形成沟槽以藉此形成包含相对横向侧壁的鳍片，该鳍片形成沟槽具有底面；
执行共形沉积工艺以形成在该鳍片的该相对横向侧壁上与在该鳍片形成沟槽的该底面上的共形种子层；
执行至少一外延成长工艺以形成共形非铁电压电材料衬垫层于该共形种子层上；
执行各向异性蚀刻工艺以实质移除在该鳍片形成沟槽的该底面上的所有该共形非铁电压电材料衬垫层，同时留下该共形非铁电压电材料衬垫层至少在该鳍片的该相对横向侧壁上的部分；
形成受拉伸应力的绝缘材料凹陷层于该鳍片形成沟槽中以及于该共形非铁电压电材料衬垫层上，该绝缘材料凹陷层具有凹陷上表面；
移除该共形非铁电压电材料衬垫层在该凹陷上表面之上的部分以藉此暴露该鳍片在该凹陷上表面之上的一部分；以及
形成栅极结构于该凹陷上表面之上以及于该鳍片在该凹陷上表面之上的一部分四周。
14.如权利要求13所述的方法，其中，形成该共形种子层包含：形成该共形种子层于位在该鳍片的上表面之上的带图案蚀刻掩膜的上表面之上。
15.如权利要求13所述的方法，其中，形成该栅极结构于该凹陷上表面之上包含：形成该栅极结构于该共形非铁电压电材料衬垫层的上表面上且与该共形非铁电压电材料衬垫层的该上表面接触，该共形非铁电压电材料衬垫层的该上表面位在大约与该绝缘材料凹陷层的该凹陷上表面的高度齐平的位置处。
16.一种FinFET装置，包含：
鳍片，界定于半导体衬底中，该鳍片包含相对横向侧壁；
绝缘材料凹陷层，位在邻近该鳍片的相对两边的数个沟槽中，该绝缘材料凹陷层具有凹陷上表面；
非铁电压电材料衬垫层，位在该鳍片的至少该相对横向侧壁上且与该鳍片的至少该相对横向侧壁接触，该非铁电压电材料衬垫层具有大约与该凹陷上表面的高度齐平的上表面，其中，该绝缘材料凹陷层位在该非铁电压电材料衬垫层上且与该非铁电压电材料衬垫层接触；以及
栅极结构，位在该鳍片的一部分四周且在该绝缘材料层的该凹陷上表面之上以及在该非铁电压电材料衬垫层的该上表面之上。
17.如权利要求16所述的FinFET装置，其中，该栅极结构位在该非铁电压电材料衬垫层的该上表面上且与该非铁电压电材料衬垫层的该上表面接触。
18.如权利要求16所述的FinFET装置，其中，该绝缘材料凹陷层位在形成于该鳍片的相对两边上的两个沟槽中的每一者的底面上且与该底面接触。
19.如权利要求16所述的FinFET装置，其中，该绝缘材料凹陷层包含受拉伸应力的绝缘材料凹陷层。
20.如权利要求16所述的FinFET装置，其中，该非铁电压电材料衬垫层包含氧化锌(ZnO)、氮化铝(AlN)或氮化镓(GaN)中的一者，以及该绝缘材料凹陷层包含二氧化硅或氮化硅中的一者。
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