CN109273363A - 形成较厚栅极堆栈的纳米片状晶体管装置的方法及其装置 - Google Patents
形成较厚栅极堆栈的纳米片状晶体管装置的方法及其装置 Download PDFInfo
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Abstract
本发明涉及形成较厚栅极堆栈的纳米片状晶体管装置的方法及其装置,其中,一种方法包括:形成带图案材料堆栈,该带图案材料堆栈包含至少一沟道半导体材料层与各自在该至少一沟道半导体材料层之上及之下的第一及第二牺牲材料层,形成取代栅极空腔于该带图案材料堆栈之上,以及通过该栅极空腔执行蚀刻工艺以对于该至少一沟道半导体材料层选择性地移除该第一及第二牺牲材料层的至少一部分。该方法进一步包括:执行第二蚀刻工艺以形成该沟道半导体材料层的减少厚度部分,该减少厚度部分具有小于该初始厚度的最终厚度,以及形成取代栅极结构至少于该沟道半导体材料层的该减少厚度部分四周。
Description
技术领域
本揭示内容大体有关于集成电路的制造,且更特别的是,有关于形成具有较厚栅极堆栈的纳米片状晶体管装置的各种方法及产生装置。
背景技术
在例如微处理器、储存装置及其类似者的现代集成电路中,在有限的芯片区上装设大量的电路组件,特别是晶体管。晶体管有各种形状及形式,例如平面晶体管、FinFET晶体管、纳米片状装置、纳米线状装置等等。习知FET为平面装置,其中该装置的整个沟道区经形成平行且稍微低于半导体衬底的平面上表面。与平面FET相比,有为三维结构的所谓3D装置,例如finFET装置。
晶体管通常为NMOS(NFET)型或者是PMOS(PFET)型装置,其中“N”与“P”符号是基于用来建立装置的源极/漏极区的掺杂物的类型。所谓CMOS(互补金属氧化物半导体)技术或产品是指使用NMOS及PMOS晶体管装置两者制成的集成电路产品。不论晶体管装置的实体组态,各装置包含形成于半导体衬底中的横向隔开的漏极及源极区,位于衬底之上且在源极/漏极区之间的栅极电极结构,以及位在栅极电极与衬底之间的栅极绝缘层。在施加适当的控制电压至栅极电极之后,就会在漏极区与源极区之间形成导电沟道区而且电流从源极区流到漏极区。
有希望成为未来先进IC产品的一种装置一般被称为纳米片状装置。一般而言,纳米片状装置有由多个垂直隔开的半导体材料片构成的鳍型沟道结构。该装置的栅极结构环绕沟道半导体材料的隔开诸层中的每一者。此一纳米片状装置可形成为高速逻辑电路的一部分。通常,该纳米片状装置可以相对低的电压操作,例如,1V或更小(基于当今的技术),且专门针对高速操作及低耗电量(特别是,用于例如智能型手机的行动装置的IC产品)而设计。
对于改善IC产品的机能有持续不断的需求,这通常涉及形成更复杂的电路。为了生产此类先进IC产品,产品设计者需要被特别设计或订制成可展现不同操作特性的晶体管装置,例如临界电压、关闭状态泄露电流、操作期间的耗电量等等。此类装置让产品设计者在实际设计用于此类先进IC产品的电路时有更多弹性及选项。
如上述,晶体管装置包括栅极结构。该栅极结构通常包含至少一栅极绝缘层(例如,二氧化硅、高k材料(k值大于10)等等)与用作晶体管的导电栅极电极的一或多层的导电材料,例如金属或含金属层(例如,功函数调整层)。栅极结构的材料可取决于建构中装置的类型而不同(例如,N型或P型)。另外,共同界定栅极结构的材料层数对于不同类型的装置可不同。通过调整共同界定栅极结构或栅极堆栈的一或多个材料层中的个数、组合物及/或厚度,可控制晶体管装置的各种操作特性,例如临界电压、泄露电流等等。例如,为了生产展现低泄露电流的装置,最好形成具有相对厚的栅极绝缘层的晶体管。不过,随着装置尺寸持续缩减,用于纳米片状装置(及其他类型装置)的栅极结构的实体空间大小已变成极小,从而在指定实体空间中难以实体配合(physically fit)所有的栅极结构材料。另外,栅极结构在纳米片状装置上的相对小实体空间可能减少装置设计者用来制造具有所欲操作特性的装置的可用选项。
本揭示内容是针对形成具有较厚栅极堆栈的纳米片状晶体管装置的各种新颖方法及所产生的新颖装置,这可避免或至少减少上述问题中的一或多个的影响。
发明内容
以下提出本发明的简化概要以提供本发明的一些方面的基本理解。此概要并非本发明的穷举式总览。它不是旨在确认本发明的关键或重要组件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细的说明的前言。
本揭示内容大致针对形成具有较厚栅极堆栈的纳米片状晶体管装置的各种新颖方法及所产生的新颖装置。揭示于本文的一示意方法主要包括:形成带图案材料堆栈于半导体衬底之上,该带图案材料堆栈包含至少一沟道半导体材料层与各自在该至少一沟道半导体材料层之上及之下的第一及第二牺牲材料层,该至少一沟道半导体材料具有一初始厚度,形成取代栅极空腔于该带图案材料堆栈之上,以及通过该取代栅极空腔执行至少一第一蚀刻工艺以对于该至少一沟道半导体材料层选择性地移除该第一及第二牺牲材料层中通过形成该取代栅极空腔而被暴露的至少一部分。在此特别实施例中,该方法进一步包括:通过该取代栅极空腔执行至少一第二蚀刻工艺以减少该至少一沟道半导体材料层中通过移除该第一及第二牺牲材料层的该至少一部分而被暴露的一部分的该初始厚度,以藉此产生该至少一沟道半导体材料层的减少厚度部分,该减少厚度部分具有小于该初始厚度的最终厚度,以及形成取代栅极结构于该栅极空腔内且至少于该至少一沟道半导体材料层的该减少厚度部分四周。
揭示于本文的一示意纳米片状装置主要包括:栅极结构,邻近该栅极结构的侧壁间隔件,以及沟道半导体材料层。在此示意实施例中,该沟道半导体层包含第一及第二部分(具有一初始厚度)与横向位在该第一部分与该第二部分之间的减少厚度部分。在此具体实施例中,该减少厚度部分具有小于该初始厚度的最终厚度,以及该减少厚度部分的至少一部分垂直地位在该栅极结构下面,同时该第一部分与该第二部分中的每一者的至少一部分垂直地位在该侧壁间隔件下面。该栅极结构至少位于该沟道半导体材料层的该减少厚度部分的一部分四周。
附图说明
参考以下结合附图的说明可明白本揭示内容,其中类似的组件以相同的附图标记表示,且其中:
图1至16图示揭示于本文用于形成具有较厚栅极堆栈的纳米片状晶体管装置的各种新颖方法及所产生的新颖装置。
尽管揭示于本文的专利目标容易做成各种修改及替代形式,然而本文仍以附图为例图示本发明的几个特定具体实施例且详述于本文。不过,应了解本文所描述的特定具体实施例并非旨在把本发明限定为本文所揭示的特定形式,反而是,本发明应涵盖落在如随附权利要求书所界定的本发明精神及范畴内的所有修改、等价及替代性陈述。
具体实施方式
以下描述本发明的各种示意具体实施例。为了清楚说明,本专利说明书没有描述实际具体实作的所有特征。当然,应了解,在开发任一此类的实际具体实施例时,必需做许多与具体实作有关的决策以达成开发人员的特定目标,例如遵循与系统相关及商务有关的限制,这些都会随着每一个具体实作而有所不同。此外,应了解,此类开发即复杂又花时间,但对于阅读本揭示内容后的本技艺一般技术人员而言仍将如同例行工作一般。
此时以参照附图来描述本发明。示意图标于附图的各种结构、系统及装置仅供解释以及避免熟谙此艺者所习知的细节混淆本发明。尽管如此,仍纳入附图以描述及解释本揭示内容的示意实施例。应使用与相关技艺技术人员所熟悉的意思一致的方式理解及解释用于本文的字汇及词组。本文没有特别定义的术语或词组(亦即,与熟谙此艺者所理解的普通惯用意思不同的定义)旨在用术语或词组的一致用法来说明。如果术语或词组旨在具有特定的意思时(亦即,不同于熟谙此艺者所理解的意思),则会在本专利说明书中以直接明白地提供特定定义的方式清楚地陈述用于该术语或词组的特定定义。
揭示于本文的方法及装置可使用各种技术来制造IC产品,例如NMOS、PMOS、CMOS等等,且可用来制造各种各样不同的产品,例如内存产品、逻辑产品、ASIC等等。可使用“取代栅极”制造技术制成揭示于本文的纳米片状晶体管装置100的栅极结构。当然,揭示于本文的本发明不应被视为受限于图示及描述于本文的示意实施例。熟谙此艺者在读完本申请案后会明白,附图并未描绘各种掺杂区,例如源极/漏极区、晕圈植入区(halo implantregion)、井区及其类似者。使用各种不同材料和执行各种已知技术,例如化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺、热成长工艺、外延沉积、旋涂技术等等,可形成揭示于本文的集成电路装置100的各种组件及结构。此时参考附图更详细地描述揭示于本文的方法及装置的各种示意具体实施例。
图1至16图示揭示于本文用于形成具有较厚栅极堆栈的纳米片状晶体管装置100的新颖方法及所产生的新颖装置。在描绘于此的实施例中,纳米片状晶体管装置100会形成于半导体衬底102中及之上。衬底102可具有各种组态,例如图示的块硅组态。衬底102也可具有绝缘体上覆硅(SOI)组态,其包括块硅层、埋藏绝缘层及主动层,其中半导体装置均形成于主动层中及之上。衬底102可由硅制成或可由除硅以外的材料制成。因此,应了解用语“衬底”或“半导体衬底”涵盖所有半导体材料及此类材料的所有形式。
图1的简化平面图图标在早期制造阶段的装置100的一示意具体实施例。图1图示通过执行多个外延成长工艺以产生或界定材料堆栈101实质在整个衬底102上已顺序形成数层材料时的装置100。在此图标实施例中,装置100包含第一牺牲材料层104、多个第二牺牲材料层106A-D(共同用附图标记106表示)以及多个沟道半导体材料层108A-C(共同用附图标记108表示)。在此特定具体实施例中,为了以下更完整地描述起见,第一牺牲材料层104应由对于第二牺牲材料层106及沟道半导体材料层108两者可选择性地移除(通过蚀刻)的材料制成。同样,为了以下更完整地描述起见,第二牺牲材料层106应由对于沟道半导体材料层108可选择性地移除(通过蚀刻)的材料制成。在装置完成时,沟道半导体材料层108的数个部分会构成装置100的沟道结构。在一示意具体实施例中,第一牺牲材料层104与第二牺牲材料层106两者可包含硅锗,其中锗浓度在诸层中充分不同以便允许该层彼此可选择性地蚀刻。在一特定具体实施例中,第一牺牲材料层104可包含Six1Gey1且第二牺牲材料层106可包含Six2Gey2(在此x1+y1=1;x2+y2=1;x1>0;x2>0且y1>y2或y1<y2)。甚至在更特定的示意具体实施例中,第一牺牲材料层104可包含例如Si(0.40)Ge(0.60)的材料,第二牺牲材料层106可由例如Si(0.75)Ge(0.25)的材料制成,以及沟道半导体材料层108可由例如实质纯硅制成。
层104、106及108在材料堆栈101内的个数及厚度可随着特定应用而有所不同。在图标于此的实施例中,该装置会包含三个沟道半导体材料层108。不过,实务上,可形成有任何所欲数目的沟道半导体材料层108的装置100,甚至包括环绕式栅极装置(gate-all-around device)100的单一沟道半导体材料层108(在工艺期间位在两个第二牺牲材料层106之间)。另外,当材料堆栈101包括多个第二牺牲材料层106时,材料堆栈101内的所有第二牺牲材料层106不需要形成相同的厚度,但有些应用会这样。同样,当材料堆栈101包含多个沟道半导体材料层108时,材料堆栈101内的所有沟道半导体材料层108不需要形成相同的厚度,但有些应用会这样。在图示于此的特定示意实施例中,第一牺牲材料层104经形成有约10nm的初始厚度,所有第二牺牲材料层106经形成有约4nm的初始厚度,以及所有沟道半导体材料层108经形成有约13nm的初始厚度。一般而言,沟道半导体材料层108的初始厚度会明显大于第二牺牲材料层106的初始厚度。在一特别实施例中,沟道半导体材料层108的初始厚度可至少约1.5至3倍大于第二牺牲材料层106的初始厚度。每个应用出于各种原因可选择用于不同材料层104、106及108的不同厚度。例如,在有些情形下,可选择这些层(个别及共同地考虑)的厚度致使材料堆栈101的总高度与用于在同一个衬底102之上所形成的其他装置(例如FinFET装置)的栅极结构一致,以便使得后续制造步骤较容易执行,例如化学机械研磨(CMP)工艺、用于浅沟槽隔离(STI)形成的鳍片暴露工艺等等。熟谙此艺者在读完本申请案后会明白,沟道半导体材料层108可约1.5至3倍大于第二牺牲材料层106的初始厚度的以上陈述不应被视为是要限制揭示于本文的本发明,因为层108、106的相对厚度可随着选定的确切加工流程而有所不同。
当然,在读完本申请案后,熟谙此艺者会明白,在衬底102为SOI型衬底的情形下,第一牺牲材料层104不会出现。在描述于此的示意加工流程中,第一牺牲材料层104的目的是要致能形成底部介电层(bottom dielectric layer),其目的是要提供栅极结构及沟道材料堆栈与纳米片状装置的衬底102的介电隔离,纳米片状装置形成于附图所示的示意块状衬底102上,以便最后有效地成为类SOI组态,即使纳米片状装置制作于块状衬底102上。当然,在装置下提供此类隔离材料的最终目的是要增进装置的电气效能。甚至在纳米片状装置制作于块状衬底上的情形下,可用不涉及第一牺牲材料层104的形成的各种不同方式来隔离装置,亦即,第一牺牲材料层104为可依照选定用于制造纳米片状装置的确切加工流程而纳入或省略的视需要层。例如,可执行离子布植工艺以在块状衬底102中形成众所周知的击穿制止器(Punch-Through Stopper,PTS)植入区以中和或减少电荷载体的不合意流动。
图2的简化平面图图示在执行数个加工操作之后的装置100。首先,通过带图案蚀刻掩膜(未图示)执行一或多个蚀刻工艺,例如各向异性蚀刻工艺,以图案化材料堆栈101以便形成有大体为鳍状组态的长条材料堆栈101A。该带图案材料堆栈在装置100的栅极宽度(GW或W)方向有标称宽度106P。此操作导致形成在长条材料堆栈101A的相对两边上伸入衬底102的多个沟槽(未图示)。在形成长条材料堆栈101A后,沉积一层或数层绝缘材料107(例如,二氧化硅等等)以便过填(overfill)形成于衬底102中的沟槽。当然,绝缘材料107可由单一层材料或多层材料构成,而且可使用熟谙此艺者所习知的各种技术及工艺来形成该(等)层,例如,执行流动式CVD工艺、执行ALD工艺以形成包含绝缘材料的衬里、执行HDP工艺以形成高密度氧化物等等。之后,执行化学机械研磨(CMP)工艺以平坦化绝缘材料层107的上表面与带图案蚀刻掩膜的上表面。然后,对绝缘材料层107执行凹陷蚀刻工艺以减少它在沟槽内的厚度,藉此暴露所有材料层在长条材料堆栈101A中的侧面。这时,通过执行一或多个蚀刻或剥除工艺来移除带图案蚀刻掩膜。
在读完本申请案后会明白,图2图标出最终装置100的栅极长度(GL或Lg–电流传输)方向以及最终装置100的栅极宽度(GW或W)。图示于附图的各种横截面图为会在对应至装置100的栅极长度方向的方向变成装置100的栅极结构的横截面。带图案蚀刻掩膜可由一或多个材料层构成,例如,相对薄的二氧化硅层与相对较厚的氮化硅层,而且它可形成到任何所欲总厚度。继续参考图2,长条材料堆栈101A的宽度及高度可随着特定应用而有所不同。另外,形成于衬底102及长条材料堆栈101A中的沟槽的整体尺寸、形状及组态可随着特定应用而有所不同。在图示于附图的示意实施例中,长条材料堆栈101A图标为已通过执行各向异性蚀刻工艺而形成,该各向异性蚀刻工艺导致长条材料堆栈101A具有大致以矩形示意(简化)图示的组态以及材料堆栈101A中的所有层具有均匀的宽度106P。在实际的真实装置中,长条材料堆栈101A的侧壁可能为有点向外逐渐减小(亦即,长条材料堆栈101A在堆栈101A底部的宽度可能大于在堆栈101A顶部的宽度),然而该组态并未图示于附图。此外,由于上述的这种侧壁逐渐减小的情形,所以堆栈101A内的各个个别材料层的宽度106P会随着从堆栈101的最上层到堆栈101的底部而变化,例如,层106D的宽度106P可小于层106A的宽度106P(至少在某种程度上)。因此,长条材料堆栈101A的大小及组态,及其制造方式不应被视为是本发明的限制。为了便于揭露,后续附图只图示实质矩形的长条材料堆栈101A。
图3及图4(平面图)图示在执行数个加工操作之后的装置100。在图示于此的示意实施例中,会使用取代栅极制造技术来制造装置100的最终栅极结构。因此,图3及图4图示在形成用于装置100的示意图标的牺牲栅极结构110、栅极帽盖(或硬掩膜)112及侧壁间隔件114之后的装置100。牺牲栅极结构110可由栅极绝缘层(未单独图示)(例如二氧化硅)以及牺牲栅极电极(未单独图示)(由例如非晶硅构成)构成。通过执行习知的沉积、掩膜及蚀刻技术,可形成牺牲栅极结构110与栅极帽盖(或硬掩膜)112。通过执行共形沉积工艺以形成间隔件材料共形层于牺牲栅极结构110、栅极帽盖(或硬掩膜)112、及衬底102的其余部分之上,然后执行各向异性蚀刻工艺,可形成侧壁间隔件114。侧壁间隔件114与栅极帽盖(或硬掩膜)112可由各种不同材料构成,例如氮化硅、SiBCN、SiNC、SiN、SiCO及SiNOC等等,而且它们可由相同或不同的材料制成。
图5及图6(平面图)图示在执行数个加工操作之后的装置100。首先,执行一或多个蚀刻工艺以移除长条材料堆栈101A中不被牺牲栅极结构110及间隔件114覆盖的所有材料层。在一具体实施例中,该蚀刻工艺可为各向异性蚀刻工艺。如图5所示,这些蚀刻工艺对于间隔件114呈实质自对准。也应注意,如图6所示,在这些蚀刻工艺完成后,衬底102先前被第一牺牲材料层104中此时已被移除的部分覆盖的部分便暴露出来。
图7图示在执行数个加工操作之后的装置100。首先,执行各向同性蚀刻工艺以对于包括第二牺牲材料层106及沟道半导体材料层108的周围材料选择性地移除第一牺牲材料层104。之后,在衬底102与最下面第二牺牲材料层106A之间的空间中形成一层绝缘材料109。用能够形成实质均匀绝缘材料109层以便提供装置100的沟道区与源极/漏极区的电气隔离的任何技术或技术组合(例如,共形ALD,各向同性/各向异性CVD、HDP等等),可形成该层绝缘材料109。然后,对该层绝缘材料109执行凹陷蚀刻工艺,致使它有最终所欲厚度,然后移除第二牺牲材料层106及沟道半导体材料层108的侧壁的任何绝缘材料。在读完本申请案后,熟谙此艺者会明白,上述加工流程只是在图7之栅极材料堆栈下形成隔离材料的一种方式。
图8图示在执行数个加工操作之后的装置100。首先,执行定时各向同性蚀刻工艺以部分凹陷第二牺牲材料层106从而在相邻沟道半导体材料层108之间建立或界定内间隔件空腔(inner spacer cavity)或末端凹部(end recess)115。然后,执行例如ALD工艺的共形沉积工艺以形成一层绝缘材料(例如,氮化硅)以便实质填满末端凹部115。之后,执行各向异性或各向同性蚀刻工艺以移除绝缘材料的任何多余材料数量从而界定或产生位在末端凹部115内的内间隔件116。应注意,内间隔件116的外表面116S对于间隔件114的外表面114S实质呈自对准。另外,取决于被执行用来部分凹陷第二牺牲材料层106从而界定内间隔件空腔或末端凹部115的横向宽度的上述各向同性蚀刻工艺的持续时间,内间隔件116的内表面116X可能与间隔件114的内表面114X对准或不对准。如下文所详述的(例如,参考图12),第二牺牲材料层106的其余部分会被移除以腾出空间给会在沟道半导体层108四周及在内间隔件116之间(但不限于这些地方)的装置的最终栅极结构。熟谙此艺者在读完本申请案后会明白,相较于传统或标准纳米片状加工流程,使用此加工流程允许第二牺牲材料层106形成到相对小的初始厚度。接着,使用相对薄的第二牺牲材料层106意谓着内间隔件空腔或末端凹部115远小于使用较厚牺牲材料层的先前技术流程的对应内间隔件空腔。因此,通过形成在相对较小的内间隔件空腔或末端凹部115中会夹止(pinch-off)的相对较薄(相较于先前技术加工流程)共形间隔件材料层,可填满本文所揭示的实体较小的内间隔件空腔或末端凹部115。形成此相对较薄(相较于先前技术加工流程)共形内间隔件材料层也意谓着,相较于涉及形成相对较厚共形内间隔件材料层的传统加工流程,在形成相对较薄共形内间隔件材料层时,较少消耗相邻装置的横向间隔。因此,相较于传统工艺,可减少栅极间隔(接触栅极多晶硅节距(Contacted gate Poly-Pitch,CPP)),而不会有使揭示于本文的相对较薄共形内间隔件材料层在相邻栅极结构之间夹止的风险。净结果是,相较于传统纳米片状加工流程,揭示于本文的加工流程有更好的装置缩放潜力。
图9图示在执行数个加工操作之后的装置100。首先,执行外延成长工艺以形成装置100的外延源极/漏极区118于绝缘材料层109之上。沟道半导体材料层108在此外延成长工艺期间用作成长面或种子区。外延源极/漏极区118可由与沟道半导体材料层108相同的半导体材料构成,例如硅,或是它们可由不同的材料构成,例如SiGe。应注意,由于沟道半导体材料层108的初始厚度相对大,所以有效成长面积相对较大,从而有利于/增进外延源极/漏极区118的成核(nucleation)及成长。因此,相较于形成用于纳米片状装置的相对较薄沟道半导体材料层的情形,S/D外延形成的机构可能会更快且提供实体较大的区域118。可取决于建构中装置的类型(N或P)的适当掺杂物类型来原位掺杂外延源极/漏极区118。
继续参考图9,在外延源极/漏极区118形成后,通过执行习知加工操作,在沟道半导体材料层108上形成示意导电源极/漏极接触结构120,例如,沟槽硅化物结构。之后,执行共形沉积工艺以形成共形蚀刻停止层122(例如,氮化硅)于装置100上。蚀刻停止层122可形成到任何所欲厚度。然后,在产品上毯覆沉积一层绝缘材料124以便过填在蚀刻停止层122之上的空间。这时,使用栅极帽盖(或硬掩膜)112作为研磨停止层而执行一或多个CMP工艺以便移除多余数量的绝缘材料124及蚀刻停止层122。
如上述,在图示于此的示意实施例中,会使用取代栅极制造技术来制造装置100的最终栅极结构。因此,图10图示在执行数个加工操作之后的装置100。首先,执行至少一CMP工艺加上蚀刻工艺以移除栅极帽盖(或硬掩膜)112和间隔件114、蚀刻停止层122及绝缘材料124的垂直部分以便藉此暴露牺牲栅极结构110。然后,执行一或多个蚀刻工艺以移除暴露的牺牲栅极结构110。这些加工操作导致在间隔件114之间的区域中形成取代栅极空腔126。牺牲栅极结构110的移除也暴露第二牺牲材料层106及沟道半导体材料层108在取代栅极空腔126内的部分。
图11图示在通过取代栅极空腔126执行各向同性蚀刻工艺以便相对于沟道半导体材料层108及周围材料选择性地移除第二牺牲材料层106的其余部分之后的装置100,亦即,“释出”沟道半导体材料层108及周围材料。应注意,移除第二牺牲材料层106在装置100的栅极长度方向(图11的横截面方向)与装置100的栅极宽度方向(亦即,在进出图11的图面的方向)的其余部分。此加工操作的结果是,取代栅极空腔126此时包括在释出沟道半导体材料层108与内间隔件116之间的空间以及间隔件114之间的空间。应注意,间隔件114形成取代栅极空腔126的至少一部分的横向边界。
图12图示在通过取代栅极空腔126对沟道半导体材料层108执行减薄或修整工艺(thinning or trimming process)以便减少(或修整)沟道半导体材料层108在取代栅极空腔126内露出的至少一部分的厚度之后的装置100。沟道半导体材料层108的未修整部分108X留在相邻内间隔件116之间。图13的横截面图(从图12所示处绘出)图示修整工艺完成后的沟道半导体层108C;图14的端视图(如图12所示)图示修整工艺完成后的沟道半导体层108C;以及图15的平面图(如图12所示)图示修整工艺完成后的沟道半导体层108C。如图12至图15所示,此加工操作使沟道半导体材料层108的被修整部分的厚度从初始垂直厚度108T1减到最终垂直厚度108T2,亦即,相较于沟道半导体材料层108的第一及第二未修整初始厚度部分108X,沟道半导体材料层108的被修整部分有减少的厚度。对于沟道半导体材料层108所做的修整数量可随着特定应用而有所不同。在一示意实施例中,修整工艺的执行可致使最终厚度108T2小于沟道半导体材料层108的初始厚度108T1约25至50%。熟谙此艺者在读完本申请案后会明白,上述范围(约25至50%)不应被视为是要限制揭示于本文的本发明,因为初始厚度108T1与最终厚度108T2的相对减量(按百分比)可随着选定的确切加工流程而有所不同。例如,可形成有相对薄初始厚度108T1的沟道半导体材料层108,然后修整约5至10%以实现目标最终厚度108T2。反之,可形成有极厚初始厚度108T1的沟道半导体材料层108,然后修整约80至90%以满足目标最终厚度108T2。
应注意,由于牺牲栅极结构110在执行修整工艺前被移除,所以沟道半导体材料层108的修整或尺寸缩减会在装置100的栅极宽度(GW)与栅极长度方向(GL)发生。图13至15为最上面沟道半导体层108C的不同视图。如在此所示,层108C的第一及第二未修整初始厚度部分108X的宽度106P(在栅极宽度方向)大约等于层108C在初始被图案化时的宽度106P(参考图2),同时层108C的被修整部分由于修整工艺而有较小宽度106WT(在栅极宽度方向)。宽度106WT与最初图案化宽度106P之间的差额取决于层108C的修整数量。也应注意,层108的未修整部分有简化图示的实质矩形端面108Y,其提供电流从源极区通过沟道区流到漏极区的管道。相较于先前技术装置,由于沟道半导体材料108的初始层有较大的垂直厚度,所以由层108的第一及第二未修整初始厚度部分108X的端面界定的面积也大于先前技术装置的。由相对较大端面108Y所提供的增多面积对装置的操作特性可提供显著的效益,下文有更完整的描述。
相较于对此沟道半导体材料层不做任何修整的先前技术纳米片状装置及/或使用与揭示于本文的沟道半导体材料层108的初始厚度108T1相比有实质较小初始厚度的沟道半导体材料层的先前技术装置,减少沟道半导体材料层108的大小或厚度会有在减薄沟道半导体材料层108之间建立相对较大的空间127(在此会形成栅极材料)的效果。也应注意,在有些应用中,最终修整(厚度减少)的沟道半导体材料层108也可包含简化图示的刻面132(例如,(111)刻面),其用作沟道半导体材料层108的减少厚度108T2部分与沟道半导体材料层108的第一及第二未修整初始厚度部分108X之间的过渡区。在一示意实施例中,沟道半导体材料层108的修整(或减小尺寸)可通过执行气相盐酸蚀刻工艺,使用H2及NH3的Frontier工艺(应用材料公司的)或内层(IL)工艺,其控制良好的氧化工艺结合控制良好的HF蚀刻工艺,或允许控制良好地移除沟道半导体材料层108的材料的任何其他工艺。
若需要,在对沟道半导体材料层108执行修整工艺之前,可通过取代栅极空腔126来执行蚀刻工艺以减小内间隔件116的横向宽度,如图12的虚线116X所反映的。内间隔件116的此一修整也有进一步增加修整沟道半导体材料层108之间的空间127尺寸的效果。或者,参考图8,通过减少末端凹部115(在此处形成内间隔件116)的尺寸(横向宽度),也可实现相同的结果。
熟谙此艺者在读完本申请案后会明白,在修整后,沟道半导体材料层108中垂直位在内间隔件116之间及下面的第一及第二未修整初始厚度部分108X会有与沟道半导体材料层108的初始厚度108T1相同的厚度。在沟道半导体材料层108的减少厚度108T2部分与源极/漏极区之间的位置处,维持有增加厚度108T1的沟道半导体材料层108极其有利。在制造装置100时,需要将外延源极/漏极区118中的掺杂物驱入沟道半导体材料层108的第一及第二未修整初始厚度部分108X的至少数个部分,以便在沟道半导体材料层108的减少厚度108T2部分与源极/漏极区118之间形成延伸区。通常用快速热处理(RTP)工艺或雷射瞬间退火(LSA)工艺来将掺杂物从外延源极/漏极区118驱出。沟道半导体材料层108的电阻通常被称为“延伸部电阻(extension resistance)”,其中较高的延伸部电阻可减少或降低装置100的通态电流(ON-state current),而较低的延伸部电阻可有利地增加(或至少不降低)通态电流。因此,装置的延伸部电阻为装置100的重要特性。如上述,在描述于本文的加工流程中,相较于标准纳米片状加工流程的沟道半导体材料,沟道半导体材料层108会形成有较大的初始厚度108T1。相较于先前技术纳米片状装置,此操作导致相对较厚的第一及第二未修整初始厚度部分108X(具有厚度108T1)位在内间隔件116及相邻的源极/漏极区118下面及其间。如上述,揭示于本文的纳米片状装置具有端面108Y,它有增加的(相较于先前技术装置)有效横截面面积供电子在延伸区中流动通过装置100,从而减少装置的延伸部电阻。
图16图标在使用习知制造技术形成简化图标的取代(最终)栅极结构134及最终栅极帽盖(或硬掩膜)136于取代栅极空腔126中以及于放大区域127中之后的装置100。通常,最终栅极结构134的材料依序地形成于取代栅极空腔126中。例如,参考图16,可执行第一共形沉积工艺以形成遍及产品且在取代栅极空腔126与在此时被修整的沟道半导体材料层108之间的放大区域127内的栅极绝缘层134A。之后,执行一或多个沉积工艺以在取代栅极空腔126中形成一或多个导电材料,以便共同形成最终栅极结构134的导电栅极电极134B。例如,在一具体实施例中,可执行第二共形沉积工艺以形成遍及产品且于在取代栅极空腔126内的栅极绝缘层134A上的功函数调整金属层(未单独图示)。在有些应用中,在取代栅极空腔126中可形成附加共形导电材料层。接下来,可执行毯覆沉积工艺以形成例如钨、铝、多晶硅等等的块状导电材料(未单独图标)于功函数调整金属层上,以便过填取代栅极空腔126的其他未填部分。之后,可执行一或多个CMP工艺以便移除栅极绝缘层134A的多余部分与导电栅极电极134B位于绝缘材料124层上面和在取代栅极空腔126外面的导电材料。
这时,执行一或多个凹陷蚀刻工艺以凹陷最终栅极结构134的材料在取代栅极空腔126内的垂直高度,以便腾出空间(在垂直的意思上)给最终栅极帽盖(或硬掩膜)136。最终栅极帽盖(或硬掩膜)136的形成可通过毯覆沉积一层最终栅极帽盖(或硬掩膜)136的材料于装置100之上以及于在取代栅极空腔126内的凹陷栅极结构134之上的空间中。然后,使用该层绝缘材料124作为研磨停止层,可执行另一CMP工艺,以便移除最终栅极帽盖(或硬掩膜)136的材料的多余数量。在加工此处时,已在纳米片状装置100上形成有最终栅极帽盖(或硬掩膜)136的最终栅极结构134。当然,最终栅极结构134的建构材料可取决于该装置为N型装置还是P型装置而有所不同。另外,取决于建构中装置的类型,最终栅极结构134可具有不同个数的材料层,例如,N型装置的最终栅极结构134可包含比P型装置的最终栅极结构134还多的导电材料层。栅极绝缘层134A可由各种不同材料构成,例如二氧化硅、所谓的高k(k值大于10)绝缘材料(在此k为相对介电常数)等等。取决于所制造的装置的类型(N或P),功函数调整金属层可由各种不同材料构成,例如氮化钛、TiC、TiAlC、W、Al等等。最终栅极帽盖(或硬掩膜)136可由各种不同材料制成,例如氮化硅、SiCN、SiN/SiCN、SiOC、SiOCN等等。
熟谙此艺者在读完本申请案后会明白,增加可用来形成最终栅极结构134(通过修整沟道半导体材料层108)的实体空间127(相较于先前技术装置)极其有利。除此之外,形成可供栅极材料使用的此一相对大的空间127让装置设计者能够订制最终栅极结构134的材料以配合特定需要,因为这与使用于IC产品上的不同电路的不同晶体管装置的晶体管特性有关。例如,由于具有相对较大的空间127,所以相较于其他晶体管装置(例如,在需要高速切换的逻辑电路中的晶体管),栅极绝缘层134A在有些晶体管装置(例如,在低泄露电流为重要考虑的输入/输出电路中的晶体管)上可较大。作为另一实施例,该较大空间127可能是有利的,因为这与在栅极堆栈中形成附加铁电材料层以做成负电容纳米片状装置有关。作为另一实施例,形成具有增加空间127(相较于先前技术装置)的纳米片状装置提供设计者在揭示于本文的纳米片状装置中可高度灵活地通过允许在栅极材料的相对较大的空间127中形成附加功函数金属(或增加彼等的厚度)来制造具有不同临界电压(按某些IC产品的要求)的装置。
以上所揭示的特定具体实施例均仅供图解说明,因为熟谙此艺者在受益于本文的教导后显然可以不同但等价的方式来修改及实施本发明。例如,可用不同的顺序完成以上所提出的工艺步骤。此外,除非在以下权利要求书有提及,不希望本发明受限于本文所示的构造或设计的细节。因此,显然可改变或修改以上所揭示的特定具体实施例而所有此类变体都被认为仍然是在本发明的范畴与精神内。应注意,在本专利说明书及随附权利要求书中为了描述各种工艺或结构而使用的例如“第一”、“第二”、“第三”或“第四”用语只是用来作为该步骤/结构的简写参考且不一定暗示该步骤/结构的执行/形成按照该有序序列。当然,取决于确切的权利要求语言,可能需要或不需要该工艺的有序序列。因此,本文提出以下的权利要求书寻求保护。
Claims (20)
1.一种形成纳米片状晶体管的方法,包含:
形成带图案材料堆栈于半导体衬底之上,该带图案材料堆栈包含至少一沟道半导体材料层以及各自在该至少一沟道半导体材料层之上及之下的第一及第二牺牲材料层,该至少一沟道半导体材料层有一初始厚度;
形成取代栅极空腔于该带图案材料堆栈之上;
通过该取代栅极空腔执行至少一第一蚀刻工艺以对于该至少一沟道半导体材料层选择性地移除该第一及第二牺牲材料层中通过形成该取代栅极空腔而被暴露的至少一部分;
通过该取代栅极空腔执行至少一第二蚀刻工艺以减少该至少一沟道半导体材料层中通过移除该第一及第二牺牲材料层的该至少一部分而被暴露的一部分的该初始厚度,以藉此产生该至少一沟道半导体材料层中具有小于该初始厚度的最终厚度的一减少厚度部分;以及
形成取代栅极结构于该取代栅极空腔内且至少于该至少一沟道半导体材料层的该减少厚度部分四周。
2.如权利要求1所述的方法,其中,该至少一沟道半导体材料层进一步包含:该至少一沟道半导体材料层中具有该初始厚度的第一及第二部分,其中,该至少一沟道半导体材料层的该减少厚度部分位在该至少一沟道半导体材料层的该第一部分与该第二部分之间。
3.如权利要求2所述的方法,其中,该至少一沟道半导体材料层的该第一部分与该第二部分的每一者的至少一部分垂直地位在为该取代栅极空腔的至少一部分的横向边界的侧壁间隔件之下。
4.如权利要求1所述的方法,其中,通过该取代栅极空腔执行该至少一第二蚀刻工艺的步骤包含:执行气相盐酸蚀刻工艺、包含作为蚀刻剂的H2及NH3的蚀刻工艺、或氧化-蚀刻组合工艺中的至少一者。
5.如权利要求1所述的方法,其中,执行该至少一第二蚀刻工艺的步骤包含:执行该至少一第二蚀刻工艺以产生该至少一沟道半导体材料层的该减少厚度部分,该减少厚度部分具有小于该初始厚度约25至50%的最终厚度。
6.如权利要求1所述的方法,其中,执行该至少一第二蚀刻工艺包含:执行该至少一第二蚀刻工艺以各自在该至少一沟道半导体材料层的该第一部分及该第二部分与该至少一沟道半导体材料层的该减少厚度部分之间产生第一及第二刻面化过渡区(facetedtransition region)。
7.如权利要求1所述的方法,其中,该至少一沟道半导体材料层包含硅,以及该第一及第二牺牲材料层包含硅锗(SiGe),其中,该第一及第二牺牲材料层包含不同的锗浓度。
8.如权利要求2所述的方法,其中,该减少厚度部分在该晶体管的栅极宽度方向有最终宽度,该最终宽度小于在该第一部分与该第二部分的每一者的该栅极宽度方向的最终宽度。
9.如权利要求1所述的方法,其中,该至少一沟道半导体材料层的该初始厚度至少1.5至3倍大于该第一及第二牺牲材料层中的任一者的初始厚度。
10.一种形成纳米片状晶体管的方法,包含:
形成带图案材料堆栈于半导体衬底之上,该带图案材料堆栈包含交替的沟道半导体材料层与牺牲半导体材料层,其中,该沟道半导体材料层的每一者的初始厚度至少1.5至3倍大于该牺牲半导体材料层的每一者的初始厚度;
形成取代栅极空腔于该带图案材料堆栈之上;
通过该取代栅极空腔执行至少一第一蚀刻工艺以对于该沟道半导体材料层选择性地移除该牺牲半导体材料层中通过形成该取代栅极空腔而被暴露的至少一部分;
通过该取代栅极空腔执行至少一第二蚀刻工艺以减少每个该沟道半导体材料层中通过移除该牺牲半导体材料层的该至少一部分而暴露的一部分的该初始厚度,以藉此产生每个该沟道半导体材料层的减少厚度部分,其中,每个该沟道半导体材料层的该减少厚度部分具有小于该沟道半导体材料层的该初始厚度约25至50%的最终厚度;以及
形成取代栅极结构于该取代栅极空腔内且至少位于该沟道半导体材料层的该减少厚度部分四周。
11.如权利要求10所述的方法,其中,每个该沟道半导体材料层进一步包含:具有该初始厚度的第一及第二部分,且其中,该减少厚度部分位于在每个该沟道半导体材料层上的该第一部分与该第二部分之间。
12.如权利要求10所述的方法,其中,每个该沟道半导体材料层的该第一部分与该第二部分的每一者的至少一部分垂直地位在为该取代栅极空腔的至少一部分的横向边界的侧壁间隔件之下。
13.如权利要求10所述的方法,其中,通过该取代栅极空腔执行该至少一第二蚀刻工艺包含:执行气相盐酸蚀刻工艺、包含作为蚀刻剂的H2及NH3的蚀刻工艺、或氧化-蚀刻组合工艺中的至少一者。
14.如权利要求10所述的方法,其中,执行该至少一第二蚀刻工艺包含:执行该至少一第二蚀刻工艺以各自在每个该沟道半导体材料层的该第一部分与该第二部分之间产生第一及第二刻面化过渡区。
15.如权利要求11所述的方法,其中,该减少厚度部分在该晶体管的栅极宽度方向有一最终宽度,该最终宽度小于在该第一部分与该第二部分中的每一者的该栅极宽度方向的最终宽度。
16.一种纳米片状晶体管,包含:
栅极结构;
侧壁间隔件,邻近该栅极结构;以及
沟道半导体材料层,该沟道半导体材料层包含:
第一及第二部分与横向位在该第一部分与该第二部分之间的减少厚度部分,其中,该第一部分与该第二部分具有初始厚度以及该减少厚度部分具有小于该初始厚度的最终厚度,且其中,该减少厚度部分的至少一部分垂直地位在该栅极结构下面,且该第一部分与该第二部分的每一者的至少一部分垂直地位在该侧壁间隔件下面,且其中,该栅极结构至少位于该沟道半导体材料层的该减少厚度部分的一部分四周。
17.如权利要求16所述的晶体管,其中,该最终厚度小于该初始厚度约25至50%。
18.如权利要求16所述的晶体管,进一步包含:各自在该沟道半导体材料层的该第一部分及该第二部分与该沟道半导体材料层的该减少厚度部分之间的第一及第二刻面化过渡区。
19.如权利要求16所述的晶体管,其中,该减少厚度部分在该晶体管的栅极宽度方向具有最终宽度,该最终宽度小于在该第一部分与该第二部分的每一者的该栅极宽度方向的最终宽度。
20.如权利要求19所述的晶体管,其中,该栅极结构包含高k栅极绝缘层与至少一层含金属材料。
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