CN106684000A - 制造自对准垂直场效应晶体管的方法和微电子结构 - Google Patents

制造自对准垂直场效应晶体管的方法和微电子结构 Download PDF

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CN106684000A
CN106684000A CN201610978958.7A CN201610978958A CN106684000A CN 106684000 A CN106684000 A CN 106684000A CN 201610978958 A CN201610978958 A CN 201610978958A CN 106684000 A CN106684000 A CN 106684000A
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layer
oxide
gap
groove
vertical semiconductor
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CN106684000B (zh
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洪俊九
博尔纳·J·奥布拉多维奇
马克·S·罗德尔
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

公开了一种制造自对准垂直纳米片场效应晶体管的方法和一种微电子结构。使用反应离子蚀刻在包括多个层的层状结构中对垂直沟槽进行蚀刻，并使用外延工艺用垂直的半导体纳米片填充垂直沟槽。蚀刻掉来自多个层之中的牺牲层并使用涂覆有高介电常数介电材料的导电(例如，金属)栅极层来代替牺牲层。来自所述多个层之中的两个其它层(一个层在栅极层的上方并且一个层在栅极层的下方)被掺杂，并作为用于在垂直半导体纳米片中形成两个PN结的扩散工艺的掺杂剂。

Description

制造自对准垂直场效应晶体管的方法和微电子结构
本申请要求于2015年11月9日提交的标题为“METHOD TO MAKE SELF-ALIGNEDVERTICAL FIELD EFFECT TRANSISTOR(制造自对准垂直场效应晶体管的方法)”的第62/253,013号美国临时申请和于2016年6月28日提交的标题为“METHOD TO MAKE SELF-ALIGNED VERTICAL FIELD EFFECT TRANSISTOR(制造自对准垂直场效应晶体管的方法)”的第15/195,886号美国非临时申请的优先权和权益，上述两件申请的全部内容通过引用包含于此。
技术领域
根据本发明的实施例的一个或更多个方面涉及垂直场效应晶体管，更具体地，涉及一种使用自对准制造工艺制造垂直场效应晶体管的方法。
背景技术
用于场效应晶体管的垂直架构可以具有包括提高的密度和性能的各种优势。然而，使用沉积、掩模和蚀刻工艺来制造这样的结构会具有挑战性，部分地是因为使用这样的工艺制造的器件可以在栅极长度和间隔件厚度上显示出相当大的变化。
因此，需要能提供很好地控制诸如栅极长度和间隔件厚度的器件参数的用于制造垂直场效应晶体管的工艺。
发明内容
本公开的实施例的多个方面在于一种用于制造自对准垂直纳米片场效应晶体管的方法。使用反应离子蚀刻在包括多个层的层状结构中蚀刻垂直沟槽，并使用外延工艺用垂直半导体纳米片填充垂直沟槽。蚀刻掉来自多个层之中的牺牲层并用包括一个栅极介电层(或多个栅极介电层，例如，介电中间层和高介电常数介电层)和后续导电(例如，金属)栅极层的栅极堆叠件来代替牺牲层。来自所述多个层之中的两个其它层(在栅极层上方的一个层和在栅极层下方的一个层)被掺杂，并作为用于在垂直半导体纳米片中形成两个PN结(即，在沟道的每个端部上的两个掺杂区)的扩散工艺的掺杂剂。
根据本发明的实施例，提供一种用于制造具有沟道和栅极的场效应晶体管的方法，所述方法包括下述步骤：在基底上沉积包括牺牲层的多个层；穿过所述多个层蚀刻第一沟槽；使垂直半导体片在第一沟槽中生长以形成沟道；蚀刻牺牲层以形成第一间隙；在第一间隙中形成导电层以形成栅极。
在一个实施例中，牺牲层包括作为主要成分的氮化硅。
在一个实施例中，所述多个层还包括两个非晶碳层、两层未掺杂氧化物层和两层掺杂氧化物。
在一个实施例中，所述多个层包括：两个非晶碳层中的第一非晶碳层、两层掺杂氧化物中的第一层掺杂氧化物、两层未掺杂氧化物中的第一层未掺杂氧化物、包括作为主要成分的氮化硅的牺牲层、两层未掺杂氧化物中的第二层未掺杂氧化物、两层掺杂氧化物中的第二层掺杂氧化物以及两个非晶碳层中的第二非晶碳层。
在一个实施例中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤包括：使垂直半导体片生长为在垂直半导体片的下端处包括第一掺杂剂；使垂直半导体片生长为在垂直半导体片的上端处包括第一掺杂剂。
在一个实施例中，所述方法还包括：加热中间结构以使第二掺杂剂从掺杂氧化物的层扩散出并扩散到垂直半导体片中。
在一个实施例中，包括第一掺杂剂使得垂直半导体片的下端具有第一导电类型和并使得垂直半导体片的上端具有第一导电类型，对第二掺杂剂进行选择以在扩散到垂直半导体片中时产生第一导电类型的半导体材料。
在一个实施例中，第一层未掺杂氧化物和第二层未掺杂氧化物的厚度相同，并被选为提供扩散到垂直半导体片中的第二掺杂剂的期望的分离。
在一个实施例中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤产生中间结构，垂直半导体片在所述两个非晶碳层中的上面一个的上表面上方延伸。
在一个实施例中，所述方法还包括：在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之后，并且在蚀刻牺牲层以形成第一间隙的步骤之前，使用化学机械平坦化(CMP)使中间结构的上表面平坦化。
在一个实施例中，所述方法还包括，在第一间隙中形成导电层以形成栅极的步骤之后：蚀刻所述两个非晶碳层中的下面一个以形成第二间隙；蚀刻所述两个非晶碳层中的上面一个以形成第三间隙；在第二间隙中形成下接触层；在第三间隙中形成上接触层。
在一个实施例中，所述方法还包括：在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，沉积氧化物衬里；在蚀刻所述两个非晶碳层中的下面一个以形成第二间隙的步骤和蚀刻所述两个非晶碳层中的上面一个以形成第三间隙的步骤之后，并且在第二间隙中形成下接触层的步骤和在第三间隙中形成上接触层的步骤之前，蚀刻在第二间隙内和第三间隙内的氧化物衬里。
在一个实施例中，所述方法还包括，在蚀刻牺牲层以形成第一间隙的步骤之后，并且在第一间隙中形成导电层以形成栅极的步骤之前：蚀刻所述两个非晶碳层中的下面一个以形成第二间隙；蚀刻所述两个非晶碳层中的上面一个以形成第三间隙；在第二间隙中形成下接触层；在第三间隙中形成上接触层。
在一个实施例中，所述方法还包括：在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，沉积氧化物衬里；在蚀刻所述两个非晶碳层中的下面一个以形成第二间隙的步骤和蚀刻所述两个非晶碳层中的上面一个以形成第三间隙的步骤之后，并且在第二间隙中形成下接触层的步骤和在第三间隙中形成上接触层的步骤之前，蚀刻在第二间隙内和第三间隙内的氧化物衬里。
在一个实施例中，所述方法还包括：在蚀刻牺牲层以形成第一间隙的步骤之后，并且在第一间隙中形成导电层以形成栅极的步骤之前，在第一间隙的表面上形成介电层。
在一个实施例中，所述方法还包括：在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，沉积氧化物衬里。
在一个实施例中，所述方法还包括：在沉积氧化物衬里的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，使用反应离子蚀刻工艺去除氧化物衬里的水平部分。
在一个实施例中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤包括使用外延工艺使垂直半导体片生长。
根据本发明的实施例，提供了一种微电子结构，所述微电子结构包括：基底；第一导电接触层，在基底上；第一掺杂氧化物层，在第一导电接触层上；第一未掺杂氧化物层，在第一掺杂氧化物层上；第一介电层，在第一未掺杂氧化物层上；第一导电栅极层，在第一介电层上；第二介电层，在第一导电栅极层上；第二未掺杂氧化物层，在第二介电层上；第二掺杂氧化物层，在第二未掺杂氧化物层上；第二导电接触层，在第二掺杂氧化物层上；第一掺杂硅垂直纳米片，延伸通过第二导电接触层、第二掺杂氧化物层、第二未掺杂氧化物层、第二介电层、第一导电栅极层、第一介电层、第一未掺杂氧化物层、第一掺杂氧化物层和第一导电接触层，第一导电栅极层通过平行于第一掺杂硅垂直纳米片并连接第一介电层和第二介电层的第三介电层与第一掺杂硅垂直纳米片分开。
在一个实施例中，第一掺杂硅垂直纳米片包括第一PN结和第二PN结，第一PN结在第一介电层的上表面下方的第一距离处，第二PN结在第二介电层的上表面上方的第二距离处，第一距离与第二距离相同。
附图说明
将参照说明书、权利要求书和附图领会并理解本发明的这些和其它特征和优势，其中：
图1是根据本发明的实施例的垂直场效应晶体管的透视剖面图；
图2是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图3是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图4是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图5是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图6是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图7是根据本发明的实施例的在用于制造垂直场效应晶体管的工艺期间形成的中间结构的剖视图；
图8是根据本发明的实施例的垂直场效应晶体管的模拟电流分布的平面图；
图9是根据本发明的实施例的有效电流作为源漏接触层厚度的函数的曲线图；
图10是根据本发明的实施例的垂直场效应晶体管的剖视图。
具体实施方式
以下结合附图阐述的详细描述意图作为根据本发明提供的制造自对准垂直场效应晶体管的方法的示例性实施例的描述，并不意图代表本发明可以被构造或使用的仅有的形式。所述描述结合示出的实施例阐述了本发明的特征。然而，将理解的是，相同或等同的功能和结构可以通过也意图包含在发明的精神和范围内的不同的实施例来实现。如在这里表示的其它地方，同样的元件标号意图表示同样的元件或特征。
参照图1，在一个实施例中，垂直纳米片场效应晶体管包括一个或更多个栅极110、一个或更多个垂直沟道120以及形成源极接触结构130、漏极接触结构140和栅极接触结构150的多个导电元件。每个栅极110可以缠绕在多个沟道120周围。图1示出了具有位于每个沟道的上端处的漏极和位于每个沟道的下端处的源极的实施例；在其它实施例中，源极位于每个沟道的上端处，漏极位于每个沟道的下端处。尽管一些实施例涉及垂直纳米片场效应晶体管，但是发明不限于这种晶体管，且在一些实施例中使用了其它种类的垂直场效应晶体管。
参照图2，在一个实施例中，在制造垂直纳米片场效应晶体管的工艺中形成的中间结构包括多个层或膜。所述层包括两个非晶碳层205、两个掺杂氧化物(例如，二氧化硅)层210、两个未掺杂氧化物层215、氮化硅(Si3N4)层220、光致抗蚀剂层225和抗反射涂层230。可以通过在基底235上沉积所述层、使光致抗蚀剂层225图案化并使用例如反应离子蚀刻形成多个沟槽240来形成图2的结构。基底235可以包括一个或更多个浅沟槽隔离结构245(例如，防止电流穿过基底235侧向地流动的结构)。
参照图3，在一个实施例中，在制造垂直纳米片场效应晶体管的工艺中形成的中间结构由图2的结构通过去除光致抗蚀剂层225和抗反射涂层230、在所得结构上沉积氧化物衬里或“虚设氧化物”层310，并使用反应离子蚀刻去除氧化物衬里310的水平的或“平面的”部分(即，位于沟槽240的底部处的部分和位于两个非晶碳层205中的上面一个的上表面上的部分)来形成。所得结构于是可以包括多个沟槽，每个沟槽的壁涂覆有氧化物衬里310。
参照图4，在一个实施例中，随后使用外延工艺(例如，气相外延)使垂直纳米片410在沟槽240中生长。通过外延工艺的生长可以持续足够长的时间而使垂直纳米片“过度生长”，即，使得垂直纳米片长得足够高以在两个非晶碳层205中的上面一个的顶表面上方延伸。化学机械平坦化(CMP)工艺可以随后用来使结构的顶表面平坦化，使得每个垂直纳米片的顶表面与两个非晶碳层205中的上面一个的顶表面齐平。可以随后在结构的顶表面上(即，在垂直纳米片的顶表面和两个非晶碳层205中的上面一个的顶表面上)沉积氧化物层420。使用外延工艺使垂直纳米片在沟槽240中生长的工艺会引起宽高比捕获(aspectratio trapping)，在外延工艺期间形成在垂直纳米片中的任何缺陷的工艺会倾向于对角地传播，直到其在限定垂直纳米片的沟槽240的壁处终止。因为沟槽240以及相应地垂直纳米片可以具有高的宽高比(即，相对于其高度的小的宽度)，在终止前每个会传播的距离可以是小的，因此缺陷浓度可以是低的。在外延工艺期间，垂直纳米片可以掺杂有非均匀的掺杂轮廓，使得每个垂直纳米片可以是例如以朝向中部减小(例如，使每个垂直纳米片的中心区域由本征硅组成)的掺杂水平在顶部处和底部处进行重掺杂。
参照图5，在一个实施例中，然后通过(i)蚀刻掉氮化硅层220并在其所在的位置中形成高介电常数绝缘层510和栅极导体(例如，逸出功金属层520)，并且(ii)执行扩散工艺以使掺杂剂从两个掺杂氧化物层210扩散(或“向内扩散”)到垂直纳米片410中，从而在每个垂直纳米片410中形成两个PN结530来形成垂直沟道。在一些实施例中，通过从最初形成在两个未掺杂氧化物层215的上方和下方的两个掺杂氧化物层210扩散的PN结的形成能够使垂直纳米片场效应晶体管的栅极相对于每个沟道中的两个PN结530精确对准。因此，可以减小或消除栅极叠置，或者如图5中所示，可以通过使用两个未掺杂氧化物层215的合适的厚度和/或通过扩散的时间和温度的变化来获得负的栅极叠置(或“栅极欠叠”)。反过来这可以减少栅致漏极泄漏(GIDL)和/或增大有效沟道长度。
可以利用替换金属栅极工艺(其可以包括例如原子层沉积之后的选择性蚀刻)执行蚀刻掉氮化硅层220并在其所在的位置中形成高介电常数绝缘层510和栅极导体520。
在一些实施例中，垂直纳米片410随着其生长而被掺杂并使掺杂剂浓度和/或掺杂剂类型在沉积工艺期间变化，相应地选择两个掺杂氧化物(SiO2)层210的掺杂剂。例如，垂直纳米片410可以生长成在垂直纳米片410的每个端部处被重掺杂为一种导电类型(即，n型或p型)(例如，在上端处和在下端处，形成重掺杂区540)以及在接近垂直纳米片410的中心被更轻地掺杂或者不掺杂或轻掺杂有相反的导电类型。两个掺杂氧化物层210中的每个于是可以包含相同的掺杂剂，并且掺杂剂可以是当向内扩散到垂直纳米片410中时作为产生与重掺杂区540的导电类型相同的导电类型的掺杂剂。
例如，在向内扩散之前，垂直纳米片410的重掺杂区540可以是p型，中心可以是本征的(例如，本征硅)或轻掺杂的n型，两个掺杂氧化物层210中的掺杂剂会使垂直纳米片410在该掺杂剂扩散到垂直纳米片410中时进一步变成p型。在其它实施例中，导电类型可以反转，即，垂直纳米片410的重掺杂区540可以是n型，中心可以是本征的(例如，本征硅)或轻掺杂p型，两个掺杂氧化物层210中的掺杂剂会使垂直纳米片410在该掺杂剂扩散到垂直纳米片410中时进一步变成n型。在一些实施例中，两个掺杂氧化物层210包含不同的掺杂剂，所述不同的掺杂剂被选择为当在扩散工艺期间两种掺杂剂扩散到垂直纳米片410的对应区域中时产生两个相反导电类型的区域；这样的实施例可以用来形成隧道场效应晶体管。
参照图6，在一个实施例中，随后(例如，使用干蚀刻工艺)蚀刻掉非晶碳层205，并且在垂直沟道处，例如，在氧化物衬里310与非晶碳层205中的一个相邻的区域中可以(使用湿蚀刻工艺或干蚀刻工艺)蚀刻掉氧化物衬里310。
参照图7，在因去除非晶碳层205而产生的间隙中形成接触层710(或“源极漏极层”，或“源极漏极接触层”)。填充有硅或硅锗的侧面外延可以用来形成接触层710。在一些实施例中，沟道垂直纳米片410和接触层710可以代替地由III-V半导体组成。
在一些实施例中，以与上面描述的次序不同的次序执行为了形成(i)高介电常数绝缘层510和逸出功金属层520与(ii)接触层710而采用的工艺。例如，以图4中示出的结构开始，可以蚀刻掉非晶碳层205并可以在垂直沟道处蚀刻掉氧化物衬里310，可以通过外延生长来形成接触层710。随后可以蚀刻掉氮化硅层220，并可以在其所在位置处形成高介电常数绝缘层510和逸出功金属层520。
参照图8和图9，用于接触层710的20nm的厚度可以足以使电流密度降至可接受的水平。图8是预测针对具有接触件的结构的电流密度的有限元模型的结果的图示。在图8中的点刻的密度代表电流密度，并且在此示例中，电流密度的明显变化是可见的。图9示出了峰表面电流密度作为接触层710的厚度的函数的曲线图。如可以从图9中看出，对于接触层710的至少20nm的厚度，接入电阻(access resistance)可以是可接受的。在一些实施例中，接触层710的厚度在20nm与40nm之间。
参照图10，在一个实施例中，利用中间线(MOL，middle of line)处理形成顶接触件1010、栅极接触件1020和底接触件1030。顶接触件可以是源极接触件或漏极接触件，因此，底接触件可以是漏极接触件或源极接触件。因为底接触件1030可以形成在截面的平面外(例如，在器件的不存在栅极层的区域中)，使得底接触件1030不短于栅极导体520，所以底接触件1030以虚线示出。
在图5和图6中，仅在一个垂直纳米片410中示出了PN结，但是PN结可以存在于所有垂直纳米片410中。沟道的在垂直纳米片410的生长期间形成的将要被更为重掺杂的区域540示出在图5、图6、图7和图10中，而为了清晰起见没有单独地示出在图4中。
如此，本公开的实施例的多个方面在于一种用于制造自对准垂直纳米片场效应晶体管的方法。使用反应离子蚀刻在包括多个层的层状结构中对垂直沟槽进行蚀刻，并使用外延工艺用垂直半导体纳米片填充垂直沟槽。蚀刻掉多个层之中的牺牲层并用包括一个栅极介电层(或多个栅极介电层，例如，介电中间层和高介电常数介电层)和一个后续导电(例如，金属)栅极层的栅极堆叠件来替换牺牲层。来自多个层之中的两个其它层(在栅极层的上方的一个层和下方的一个层)被掺杂，并作为用于在垂直半导体纳米片中形成两个PN结的扩散工艺的掺杂剂。
另外，根据本发明的实施例，提供包括由上述方法制造的自对准垂直纳米片场效应晶体管的微电子结构。具体地讲，微电子结构可以包括基底以及顺序地设置在基底上的第一导电接触层、第一掺杂氧化物层、第一未掺杂氧化物层、第一介电层、第一导电栅极层、第二介电层、第二未掺杂氧化物层、第二掺杂氧化物层、第二导电接触层和第一掺杂硅垂直纳米片，其中，第一掺杂硅垂直纳米片延伸通过第二导电接触层、第二掺杂氧化物层、第二未掺杂氧化物层、第二介电层、第一导电栅极层、第一介电层、第一未掺杂氧化物层、第一掺杂氧化物层和第一导电接触层，第一导电栅极层通过平行于第一掺杂硅垂直纳米片并连接第一介电层和第二介电层的第三介电层与第一掺杂硅垂直纳米片分开。在微电子结构中，第一掺杂硅垂直纳米片可以包括第一PN结和第二PN结，其中，第一PN结在第一介电层的下表面下方的第一距离处，第二PN结在第二介电层的上表面上方的第二距离处，第一距离与第二距离相同。
将理解的是，尽管在这里可使用术语“第一”、“第二”、“第三”等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应该受这些术语限制。这些术语仅用来将一个元件、组件、区域、层或部分与另一个元件、组件、区域、层或部分区分开来。因此，在不脱离发明构思的精神和范围的情况下，下面讨论的第一元件、组件、区域、层或部分可被称为第二元件、组件、区域、层或部分。
为了描述的容易，这里可以使用诸如“在……之下”、“在……下方”、“下”、“在……下”“在……上方”和“上”等的空间相对术语来描述如图中示出的一个元件或特征与另外的元件或特征的关系。将理解的是，除了图中描绘的方位之外，这样的空间相对术语还意图包含装置在使用或操作中的不同方位。例如，如果图中的装置被翻转，则描述为“在”其它元件或特征“下方”或“之下”或“下”的元件随后将被定位为“在”所述其它元件或特征“上方”。因此，术语“在……下方”和“在……下”可以包括上方和下方两种方位。装置可以另行定位(例如，旋转90度或处于其它方位)，并且应当相应地解释这里使用的空间相对描述语。此外，还将理解的是，当层被称作“在”两个层“之间”时，该层可以是位于两个层之间的唯一的层，或者也可以存在一个或更多个中间层。
这里使用的术语仅用于描述具体实施例的目的，而不意图限制发明构思。如在这里使用的，术语“基本上”、“大约”和相似的术语是用作近似的术语而不是用作程度的术语，并且意图解释本领域的普通技术人员将识别的测量值或计算值中的固有偏差。如在这里使用的，术语“主要成分”是指构成组成物的至少一半重量的成分，术语“主要部分”在应用到多个项目中时，其是指至少一半的项目。
如在这里使用的，除非上下文另有明确指出，否则单数形式“一个”和“一种”也意图包括复数形式。将进一步理解的是，术语“包括”和/或“包含”在本说明书中使用时，说明存在陈述的特征、整体、步骤、操作、元件和/或组件，但是不排除存在或添加一个或更多个特征、整体、步骤、操作、元件、组件和/或它们的组。如在这里使用的，术语“和/或”包括相关所列项目的一个或更多个的任意组合和所有组合。诸如“中的至少一个(种)”的表述在一列元件(要素)之后时，修饰整列元件(要素)，而不是修饰该列的个别元件(要素)。另外，在描述发明构思的实施例时“可以”的使用指的是“本发明的一个或更多个实施例”。另外，术语“示例性”意图指示例或图示。如在这里使用的，术语“使用”及其变型可以被认为分别与“利用”及其变型同义。
将理解的是，当元件或层被称作“在”另一元件或层“上”、“连接到”、“结合到”或“邻近于”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到、直接结合到或直接邻近于所述另一元件或层，或者可以存在一个或更多个中间元件或中间层。相反，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”、“直接结合到”或“直接邻近于”另一元件或层时，不存在中间元件或中间层。
这里陈述的任何数值范围意图包括在陈述的范围内的相同数值精度的所有子范围。例如，“1.0至10.0”的范围意图包括所陈述的最小值1.0与所陈述的最大值10.0之间(包括所陈述的最小值1.0和所陈述的最大值10.0)的所有子范围，即，具有等于或大于1.0的最小值和等于或小于10.0的最大值，诸如以2.4至7.6为例。这里陈述的任何最大数值界限意图包括其中包含的所有较小数值界限，本说明书中陈述的任何最小数值界限意图包括其中包含的所有较大数值界限。
尽管在这里已经具体地描述并示出制造自对准垂直场效应晶体管的方法的示例性实施例，但是对于本领域技术人员而言，许多修改和变化将是明显的。因此，将理解的是，可以不同于如这里具体描述的来实施根据本发明的原理解释的制造自对准垂直场效应晶体管的方法。发明也限定在权利要求中及其等同物中。

Claims (20)

1.一种制造具有沟道和栅极的场效应晶体管的方法，所述方法包括下述步骤：
在基底上沉积包括牺牲层的多个层；
穿过所述多个层蚀刻第一沟槽；
使垂直半导体片在第一沟槽中生长以形成沟道；
蚀刻牺牲层以形成第一间隙；以及
在第一间隙中形成导电层以形成栅极。
2.如权利要求1所述的方法，其中，牺牲层包括作为主要成分的氮化硅。
3.如权利要求1所述的方法，其中，所述多个层还包括：
两个非晶碳层；
两层未掺杂氧化物；以及
两层掺杂氧化物。
4.如权利要求3所述的方法，其中，所述多个层从基底按次序包括：
所述两个非晶碳层中的第一非晶碳层；
所述两层掺杂氧化物中的第一层掺杂氧化物；
所述两层未掺杂氧化物中的第一层未掺杂氧化物；
所述牺牲层，包括作为主要成分的氮化硅；
所述两层未掺杂氧化物中的第二层未掺杂氧化物；
所述两层掺杂氧化物中的第二层掺杂氧化物；以及
所述两个非晶碳层中的第二非晶碳层。
5.如权利要求4所述的方法，其中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤包括：
使垂直半导体片生长为在垂直半导体片的下端处包括第一掺杂剂；以及使垂直半导体片生长为在垂直半导体片的上端处包括所述第一掺杂剂。
6.如权利要求5所述的方法，其中：
使垂直半导体在第一沟槽中生长以形成沟道的步骤产生中间结构，
每层掺杂氧化物包括第二掺杂剂，
所述方法还包括：加热中间结构以使第二掺杂剂扩散出所述两层掺杂氧化物并扩散到垂直半导体片中。
7.如权利要求6所述的方法，其中：
包括第一掺杂剂使得垂直半导体片的下端具有第一导电类型并使得垂直半导体片的上端具有第一导电类型，
对第二掺杂剂进行选择以在扩散到垂直半导体片中时产生第一导电类型的半导体材料。
8.如权利要求7所述的方法，其中，第一层未掺杂氧化物层和第二层未掺杂氧化物的厚度相同，并被选为提供扩散到垂直半导体片中的第二掺杂剂的期望的分离。
9.如权利要求3所述的方法，其中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤产生中间结构，垂直半导体片在所述两个非晶碳层中的上面一个的上表面上方延伸。
10.如权利要求9所述的方法，所述方法还包括：在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之后，并且在蚀刻牺牲层以形成第一间隙的步骤之前：
利用化学机械平坦化使中间结构的上表面平坦化。
11.如权利要求3所述的方法，所述方法还包括，在第一间隙中形成导电层以形成栅极的步骤之后：
蚀刻所述两个非晶碳层中的下面一个以形成第二间隙；
蚀刻所述两个非晶碳层中的上面一个以形成第三间隙；
在第二间隙中形成下接触层；以及
在第三间隙中形成上接触层。
12.如权利要求11所述的方法，所述方法还包括：
在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，沉积氧化物衬里；以及
在蚀刻所述两个非晶碳层中的下面一个以形成第二间隙的步骤和蚀刻所述两个非晶碳层中的上面一个以形成第三间隙的步骤之后，并且在第二间隙中形成下接触层的步骤和在第三间隙中形成上接触层的步骤之前，在第二间隙内和第三间隙内蚀刻氧化物衬里。
13.如权利要求3所述的方法，所述方法包括：在蚀刻牺牲层以形成第一间隙的步骤之后，并且在第一间隙中形成导电层以形成栅极的步骤之前：
蚀刻所述两个非晶碳层中的下面一个以形成第二间隙；
蚀刻所述两个非晶碳层中的上面一个以形成第三间隙；
在第二间隙中形成下接触层；以及
在第三间隙中形成上接触层。
14.如权利要求13所述的方法，所述方法还包括：
在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前，沉积氧化物衬里；以及
在蚀刻所述两个非晶碳层中的下面一个以形成第二间隙的步骤和蚀刻所述两个非晶碳层中的上面一个以形成第三间隙的步骤之后，并且在第二间隙中形成下接触层的步骤和在第三间隙中形成上接触层的步骤之前，在第二间隙内和第三间隙内蚀刻氧化物衬里。
15.如权利要求1所述的方法，所述方法还包括，在蚀刻牺牲层以形成第一间隙的步骤之后，并且在第一间隙中形成导电层以形成栅极的步骤之前：
在第一间隙的表面上形成介电层。
16.如权利要求1所述的方法，所述方法还包括，在穿过所述多个层蚀刻第一沟槽的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前：
沉积氧化物衬里。
17.如权利要求16所述的方法，所述方法还包括，在沉积氧化物衬里的步骤之后，并且在使垂直半导体片在第一沟槽中生长以形成沟道的步骤之前：
使用反应离子蚀刻工艺去除衬里氧化物的水平部分。
18.如权利要求1所述的方法，其中，使垂直半导体片在第一沟槽中生长以形成沟道的步骤包括使用外延工艺使垂直半导体片生长。
19.一种微电子结构，所述微电子结构包括：
基底；
第一导电接触层，位于基底上；
第一掺杂氧化物层，位于第一导电接触层上；
第一未掺杂氧化物层，位于第一掺杂氧化物层上；
第一介电层，位于第一未掺杂氧化物层上；
第一导电栅极层，位于第一介电层上；
第二介电层，位于第一导电栅极层上；
第二未掺杂氧化物层，位于第二介电层上；
第二掺杂氧化物层，位于第二未掺杂氧化物层上；
第二导电接触层，位于第二掺杂氧化物层上；
第一掺杂硅垂直纳米片，延伸通过：第二导电接触层、第二掺杂氧化物层、第二未掺杂氧化物层、第二介电层、第一导电栅极层、第一介电层、第一未掺杂氧化物层、第一掺杂氧化物层和第一导电接触层，
第一导电栅极层通过第三介电层与第一掺杂硅垂直纳米片分开，其中，第三介电层平行于第一掺杂硅垂直纳米片，并连接第一介电层和第二介电层。
20.如权利要求19所述的微电子结构，其中，第一掺杂硅垂直纳米片包括：
第一PN结；以及
第二PN结，
第一PN结在第一介电层的下表面下方的第一距离处，
第二PN结在第二介电层的上表面上方的第二距离处，
第一距离与第二距离相同。
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