TWI712091B - 自對準垂直場效電晶體的製造方法 - Google Patents

自對準垂直場效電晶體的製造方法 Download PDF

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TWI712091B
TWI712091B TW105129760A TW105129760A TWI712091B TW I712091 B TWI712091 B TW I712091B TW 105129760 A TW105129760 A TW 105129760A TW 105129760 A TW105129760 A TW 105129760A TW I712091 B TWI712091 B TW I712091B
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layer
gap
layers
effect transistor
vertical semiconductor
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TW105129760A
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TW201717285A (zh
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洪俊九
博爾納 J. 奧布拉多維奇
馬克 S. 羅德爾
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南韓商三星電子股份有限公司
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Abstract

本發明提供一種用於製造自對準垂直奈米薄片場效電晶體的方法。使用反應性離子蝕刻在包含多個層的層狀結構中蝕刻垂直溝槽，且藉由垂直半導體奈米薄片使用磊晶製程填充所述垂直溝槽。來自所述多個層當中的犧牲層經蝕刻掉，且藉由塗佈有高介電常數介電材料的導電（例如，金屬）閘極層替換。來自所述多個層當中的兩個其他層，一個在所述閘極層上方且一個在所述閘極層下方，經摻雜且充當在所述垂直半導體奈米薄片中形成兩個PN接面的擴散製程的摻雜劑供體。

Description

自對準垂直場效電晶體的製造方法
根據本發明的實施例的一或多個態樣是關於垂直場效電晶體，且更特定而言是關於用於使用自對準製造製程製造垂直場效電晶體的方法。
場效電晶體的垂直架構可具有各種優點，包含提高的密度及效能。然而，藉由沈積製程、遮蔽製程以及蝕刻製程製造這些結構可具有挑戰性，部分由於藉由這些製程所製造的裝置在閘極長度及間隔物厚度上可呈現相當大的變化。
因此，存在對於能夠提供對裝置參數（諸如，閘極長度及間隔物厚度）的良好控制的用於製造垂直場效電晶體的製程的需要。
本發明的實施例的態樣是針對用於製造自對準垂直奈米薄片場效電晶體的方法。使用反應性離子蝕刻（reactive ion etching）在包含多個層的層狀結構中蝕刻垂直溝槽，且藉由垂直半導體奈米薄片使用磊晶製程填充所述垂直溝槽。來自所述多個層當中的犧牲層經蝕刻掉且由包括一閘極介電層（或多個閘極介電層，例如介電間層及高介電常數介電層）及後續導電（例如，金屬）閘極層的閘極堆疊替換。來自所述多個層當中的兩個其他層（一個在所述閘極層上方且一個在所述閘極層下方）經摻雜，且充當在垂直半導體奈米薄片中形成兩個PN接面（亦即，通道的各端上的兩個摻雜區域）的擴散製程的摻雜劑。
根據本發明的實施例，提供用於製造具有通道及閘極的場效電晶體的方法，所述方法包含：將多個層（包含犧牲層）沈積於基板上；蝕刻第一溝槽貫穿所述多個層；在第一溝槽中生長垂直半導體薄片以形成通道；蝕刻犧牲層以形成第一間隙；以及在第一間隙中形成導電層，從而形成閘極。
在一個實施例中，犧牲層包含作為主要組分的氮化矽。
在一個實施例中，所述多個層進一步包含：兩個非晶碳層；兩個未經摻雜的氧化物層；以及兩個經摻雜氧化物層。
在一個實施例中，所述方法包含作為主要組分的氮化矽；兩個未經摻雜氧化物層的第二未經摻雜氧化物層；兩個經摻雜氧化物層的第二經摻雜氧化物層；以及兩個非晶碳層的第二非晶碳層。
在一個實施例中，在第一溝槽中生長垂直半導體薄片以形成通道包含：生長垂直半導體薄片以包含在垂直半導體薄片的下端處的第一摻雜劑；以及生長垂直半導體薄片以包含在垂直半導體薄片的上端處的第一摻雜劑。
在一個實施例中，所述方法包含：加熱中間結構以使得第二摻雜劑擴散至經摻雜氧化物層之外且擴散至垂直半導體薄片中。
在一個實施例中，包含第一摻雜劑導致垂直半導體薄片的下端具有第一導電性類型及垂直半導體薄片的上端具有第一導電性類型，且選擇第二摻雜劑以在擴散至垂直半導體薄片中時產生具有第一導電性類型的半導體材料。
在一個實施例中，第一未經摻雜氧化物層與第二未經摻雜氧化物層的厚度相同，且選擇所述厚度以提供擴散至垂直半導體薄片中的第二摻雜劑的所要分離。
在一個實施例中，在第一溝槽中生長垂直半導體薄片以形成通道產生中間結構，垂直半導體薄片在兩個非晶碳層中的較高者的上部表面上方延伸。
在一個實施例中，所述方法包含在第一溝槽中生長垂直半導體薄片以形成通道之後且在蝕刻犧牲層以形成第一間隙之前：利用化學機械平坦化（chemical mechanical planarization，CMP）使中間結構的上部表面平坦化。
在一個實施例中，所述方法包含在第一間隙中形成導電層從而形成閘極之後：蝕刻兩個非晶碳層中的較低者以形成第二間隙；蝕刻兩個非晶碳層中的較高者以形成第三間隙；在第二間隙中形成下部接觸層；以及在第三間隙中形成上部接觸層。
在一個實施例中，所述方法包含：在蝕刻第一溝槽貫穿所述多個層之後且在第一溝槽中生長垂直半導體薄片以形成通道之前：沈積氧化物內襯；以及在蝕刻兩個非晶碳層中的較低者以形成第二間隙及蝕刻兩個非晶碳層中的較高者以形成第三間隙之後且在第二間隙中形成下部接觸層及在第三間隙中形成上部接觸層之前：蝕刻第二間隙內及第三間隙內的氧化物內襯。
在一個實施例中，所述方法包含在第一溝槽中生長垂直半導體薄片以形成通道之後且在第一間隙中形成導電層從而形成閘極之前：蝕刻兩個非晶碳層中的較低者以形成第二間隙；蝕刻兩個非晶碳層中的較高者以形成第三間隙；在第二間隙中形成下部接觸層；以及在第三間隙中形成上部接觸層。
在一個實施例中，所述方法包含：在蝕刻第一溝槽貫穿所述多個層之後且在第一溝槽中生長垂直半導體薄片以形成通道之前：沈積氧化物內襯；以及在蝕刻兩個非晶碳層中的較低者以形成第二間隙及蝕刻兩個非晶碳層中的較高者以形成第三間隙之後且在第二間隙中形成下部接觸層及在第三間隙中形成上部接觸層之前：蝕刻第二間隙內及第三間隙內的氧化物內襯。
在一個實施例中，所述方法包含在蝕刻犧牲層以形成第一間隙之後且在第一間隙中形成導電層從而形成閘極之前：在第一間隙的表面上形成介電層。
在一個實施例中，所述方法包含在蝕刻第一溝槽貫穿所述多個層之後且在第一溝槽中生長垂直半導體薄片以形成通道之前：沈積氧化物內襯。
在一個實施例中，所述方法包含在沈積氧化物內襯之後且在第一溝槽中生長垂直半導體薄片以形成通道之前：使用反應性離子蝕刻製程移除氧化物內襯的水平部分。
在一個實施例中，在第一溝槽中生長垂直半導體薄片以形成通道包含利用磊晶製程生長垂直半導體薄片。
根據本發明的實施例，提供微電子結構，其包含：基板；基板上的第一導電接觸層；第一導電接觸層上的第一經摻雜氧化物層；第一經摻雜氧化物層上的第一未經摻雜氧化物層；第一未經摻雜氧化物層上的第一介電層；第一介電層上的第一導電閘極層；第一導電閘極層上的第二介電層；第二介電層上的第二未經摻雜氧化物層；未經摻雜氧化物層上的第二經摻雜氧化物層；第二經摻雜氧化物層上的第二導電接觸層；延伸穿過第二導電接觸層、第二經摻雜氧化物層、第二未經摻雜氧化物層、第二介電層、第一導電閘極層、第一介電層、第一未經摻雜氧化物層、第一經摻雜氧化物層以及第一導電接觸層的第一經摻雜矽垂直奈米薄片，第一導電閘極層藉由第三介電層與第一經摻雜矽垂直奈米薄片分離，所述第三介電層平行於第一經摻雜矽垂直奈米薄片以及接合第一介電層與第二介電層。
在一個實施例中，第一經摻雜矽垂直奈米薄片包含：第一PN接面及第二PN接面，第一PN接面處於第一介電層的下部表面下方第一距離，第二PN接面處於第二介電層的上部表面上方第二距離，第一距離與第二距離相同。
下文中結合附圖闡述的詳細描述意欲作為對根據本發明所提供的自對準垂直場效電晶體的製造方法的例示性實施例的描述，且並不意欲表示可構造或利用本發明的僅有形式。描述結合所說明的實施例來闡述本發明的特徵。然而，應理解，可藉由亦意欲涵蓋在本發明的精神及範疇內的不同實施例實現相同或等效功能及結構。如本文中在別處所表示，相同元件編號意欲指示相同元件或特徵。
參看圖1，在一個實施例中，垂直奈米薄片場效電晶體包含一或多個閘極110、一或多個垂直通道120以及形成源極接觸結構130、汲極接觸結構140以及閘極接觸結構150的多個導電元件。每一閘極110可環繞多個通道120。圖1說明汲極在每一通道的上端處且源極在每一通道的下端處的實施例；在其他實施例中，源極在每一通道的上端處且汲極在每一通道的下端處。儘管一些實施例是關於垂直奈米薄片場效電晶體，但本發明不限於此類型的電晶體且在一些實施例中用於其他類型的垂直場效電晶體。
參看圖2，在一個實施例中，在製造垂直奈米薄片場效電晶體的製程中形成的中間結構包含多個層或多個膜。所述層包含兩個非晶碳層205、兩個經摻雜氧化物（例如，二氧化矽）層210、兩個未經摻雜氧化物層215、氮化矽（Si3 N4 ）層220、光阻層225以及抗反射塗層230。圖2的結構可藉由將所述層沈積於基板235上，圖案化光阻層225以及使用例如反應性離子蝕刻形成多個溝槽240而形成。基板235可包含一或多個淺溝槽隔離結構245（例如，防止電流橫向流動穿過基板235的結構）。
參看圖3，在一個實施例中，形成於製造垂直奈米薄片場效電晶體的製程中的中間結構是藉由移除光阻層225及抗反射塗層230，將「虛設氧化物」或氧化物內襯層310沈積於所得結構上，以及使用反應性離子蝕刻移除氧化物內襯310的水平或「平面」部分（亦即，在溝槽240的底部處的部分以及在兩個非晶碳層205中的較高者的上部表面上的部分）而由圖2的結構形成。所得結構可接著包含多個溝槽，每一溝槽的壁塗佈有氧化物內襯310。
參看圖4，在一個實施例中，接著使用磊晶製程（例如，氣相磊晶）在溝槽240中生長垂直奈米薄片410。藉由磊晶製程的生長可持續充分長的時間以「過度生長」垂直奈米薄片，亦即使得垂直奈米薄片生長得足夠高以在兩個非晶碳層205中的較高者的頂部表面上方延伸。化學機械平坦化（CMP）製程隨後可用於平坦化結構的頂部表面，以使得垂直奈米薄片中的每一者的頂部表面與兩個非晶碳層205中的較高者的頂部表面齊平。氧化物層420可接著沈積於結構的頂部表面上，亦即沈積於垂直奈米薄片的頂部表面上及兩個非晶碳層205中的較高者的頂部表面上。使用磊晶製程在溝槽240中生長垂直奈米薄片的製程可導致縱橫比捕獲（aspect ratio trapping），其為在磊晶製程期間在垂直奈米薄片中形成的任何缺陷可傾向於對角傳播直至其終止於界定垂直奈米薄片的溝槽240的壁處的過程。由於溝槽240以及因此垂直奈米薄片可具有高縱橫比（亦即，相對於其高度的小寬度），因此各自在終止之前可傳播的距離較小，且因此缺陷集中度可較低。垂直奈米薄片在磊晶製程期間可以不均勻摻雜分佈進行摻雜，使得每一垂直奈米薄片可例如在頂部處及在底部處經重度摻雜，摻雜程度朝向中部逐漸降低，其中例如每一垂直奈米薄片的中心區域由本質矽組成。
參看圖5，在一個實施例中，接著藉由(i)蝕刻掉氮化矽層220且在其位置中形成高介電常數絕緣層510及閘極導體520（例如，功函數金屬層）；以及(ii)執行擴散製程以將摻雜劑自兩個經摻雜氧化物層210擴散（或「內擴散」）至垂直奈米薄片410中，在垂直奈米薄片410中的每一者中形成兩個PN接面530而形成垂直通道。在一些實施例中，藉由自最初形成於兩個未經摻雜氧化物層215上方及下方的兩個經摻雜氧化物層210的擴散形成PN接面允許實現垂直奈米薄片場效電晶體的閘極相對於每一通道中的兩個PN接面530的準確對準。因此，可減少或消除閘極重疊，或如圖5中所說明，可藉由使用適當厚度的兩個未經摻雜氧化物層215及/或藉由改變擴散的時間及溫度而實現負閘極重疊（或「閘極欠疊」（gate underlap））。此又可減小閘極引發的汲極洩漏（gate induced drain leakage，GIDL）及/或增大有效通道長度。
蝕刻掉氮化矽層220且在其位置中形成高介電常數絕緣層510及閘極導體520可利用替換金屬閘極製程（其可包含例如選擇性蝕刻後接原子層沈積）來執行。
在一些實施例中，垂直奈米薄片410在其生長時經摻雜，其中摻雜劑濃度及/或摻雜劑類型在沈積製程期間不斷變化，且相應地選擇兩個經摻雜氧化物（SiO2 ）層210的摻雜劑。舉例而言，垂直奈米薄片410可在垂直奈米薄片410的各端處生長為經重度摻雜，從而具有一個導電性類型（亦即，n型或p型）（例如，在上端處及在下端處，形成經重度摻雜區域540）；以及在垂直奈米薄片410的中心附近生長為較輕度摻雜、或未經摻雜、或輕度摻雜有相反的導電性類型。兩個經摻雜氧化物層210中的每一者可接著含有相同摻雜劑，且摻雜劑可為一種摻雜劑，其在內擴散至垂直奈米薄片410中時充當產生與經重度摻雜區域540的導電性類型相同的導電性類型的摻雜劑。
舉例而言，在內擴散之前，垂直奈米薄片410的經重度摻雜區域540可為p型，且中心可為本質的（intrinsic）（例如，本質矽）或經輕度摻雜的n型，且兩個經摻雜氧化物層210中的摻雜劑可在其擴散至垂直奈米薄片410中時使得垂直奈米薄片410進一步變為p型。在其他實施例中，導電性類型可顛倒，亦即垂直奈米薄片410的經重度摻雜區域540可為n型，且中心可為本質的（例如，本質矽）或經輕度摻雜的p型，以及兩個經摻雜氧化物層210中的摻雜劑可在其擴散至垂直奈米薄片410中時使得垂直奈米薄片410進一步變為n型。在一些實施例中，兩個經摻雜氧化物層210含有不同摻雜劑，所述摻雜劑經選擇以在擴散製程期間當該兩種摻雜劑擴散至垂直奈米薄片410的各別區域中時形成具有相反導電性類型的兩個區域；可利用此實施例以形成穿隧場效電晶體。
參看圖6，在一個實施例中，非晶碳層205接著經蝕刻掉（例如，使用乾式蝕刻製程），且氧化物內襯310可在垂直通道處（例如，在氧化物內襯310與非晶碳層205中的一者相鄰的區中）經蝕刻掉（使用濕式蝕刻製程或乾式蝕刻製程）。
參看圖7，接觸層710（或「源極汲極層」或「源極汲極接觸層」）形成於由移除非晶碳層205產生的間隙中。藉由矽或矽鍺的側部磊晶填充可用於形成接觸層710。在一些實施例中，通道垂直奈米薄片410及接觸層710可改為由III-V族半導體組成。
在一些實施例中，以不同於上文所描述的次序的次序來執行用以形成(i)高介電常數絕緣層510及功函數金屬層（閘極導體520）以及(ii)接觸層710的製程。舉例而言，以圖4中所說明的結構開始，可蝕刻掉非晶碳層205且可在垂直通道處蝕刻掉氧化物內襯310，以及可藉由磊晶生長形成接觸層710。隨後，可蝕刻掉氮化矽層220，且高介電常數絕緣層510及功函數金屬層（閘極導體520）可形成於氮化矽層220的位置中。
參看圖8及圖9，接觸層710的20 nm的厚度可足以將電流密度減小至可接受位準。圖8為對預測具有接觸件的結構的電流密度的有限元模型的結果的說明。圖8中的點畫（stippling）的密度表示電流密度，且在此實例中，電流密度的顯著變化為可見的。圖9展示隨接觸層710的厚度而變的峰值表面電流密度的曲線。如根據圖9可見，對於接觸層710的至少20 nm的厚度，存取電阻可為可接受的。在一些實施例中，接觸層710的厚度在20 nm與40 nm之間。
參看圖10，在一個實施例中，藉由中線（middle of line，MOL）處理形成頂部接觸件1010、閘極接觸件1020以及底部接觸件1030。頂部接觸件可為源極接觸件或汲極接觸件，且相應地，底部接觸件可為汲極接觸件或源極接觸件。以虛線展示底部接觸件1030，因為其可能形成於截面平面之外，例如在不存在閘極層的裝置區域中，使得底部接觸件1030不短接至閘極導體520。
在圖5及圖6中，僅在垂直奈米薄片410中的一者中說明PN接面，但其可存在於所有垂直奈米薄片410中。在生長垂直奈米薄片410期間形成為較重度摻雜的通道的經重度摻雜區域540展示於圖5、圖6、圖7以及圖10中且出於明晰之目的，在圖4中並不分開說明。
因而，本發明的實施例的態樣是針對用於製造自對準垂直奈米薄片場效電晶體的方法。使用反應性離子蝕刻在包含多個層的層狀結構中蝕刻垂直溝槽，且藉由垂直半導體奈米薄片使用磊晶製程填充垂直溝槽。來自所述多個層當中的犧牲層經蝕刻掉且藉由包括閘極介電層（或多個閘極介電層，例如介電間層及高介電常數介電層）及後續導電（例如，金屬）閘極層的閘極堆疊替換。來自所述多個層當中的兩個其他層，一個在閘極層上方且一個在閘極層下方，經摻雜且充當在垂直半導體奈米薄片中形成兩個PN接面的擴散製程的摻雜劑。
應理解，儘管本文中可使用術語「第一」、「第二」、「第三」等以描述各種元件、組件、區域、層及/或區段，但所述元件、組件、區域、層及/或區段不應受所述術語限制。這些術語僅用以將一個元件、組件、區域、層或區段與另一元件、組件、區域、層或區段區別開來。因此，在不脫離本發明概念的精神及範疇的情況下，下文論述的第一元件、組件、區域、層或區段可被稱為第二元件、組件、區域、層或區段。
為了易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...下面」、「在...上方」、「上部」及其類似者的空間相對術語，以描述如諸圖中所說明的一個元件或特徵相對於另一元件或特徵的關係。應理解，這些空間相對術語意欲涵蓋除圖中所描繪的定向之外的在使用中或在操作中的裝置的不同定向。舉例而言，若圖中的裝置翻轉，則描述為「在」其他元件或特徵「下方」或「以下」或「下面」的元件將定向為「在」其他元件或特徵「上方」。因此，實例術語「在...下方」及「在...下面」可涵蓋上方及下方的定向兩者。裝置可以其他方式定向（例如，旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞應相應地進行解釋。另外，亦應理解，當將層稱作「在」兩個層「之間」時，其可為兩個層之間的唯一層，或亦可存在一或多個介入層。
本文中使用的術語僅出於描述特定實施例的目的，且並不意欲限制本發明概念。如本文中所使用，術語「實質上」、「約」及類似術語用作表示近似的術語且並不用作表示程度的術語，以及意欲考慮將由一般熟習此項技術者識別的量測值或計算值的固有偏差。如本文所使用，術語「主要組分」意謂按重量計構成組成物的至少一半的組分，且術語「主要部分」在應用於多個項時意謂所述項的至少一半。
如本文中所使用，單數形式「一」意欲亦包含複數形式，除非上下文另外清楚地指示。應進一步理解，術語「包括」在用於本說明書中時指定所陳述特徵、整數、步驟、操作、元件以及/或組件的存在，但不排除一或多個其他特徵、整數、步驟、操作、元件、組件以及/或其群組的存在或添加。如本文中所用，術語「及/或」包含相關聯列舉項目中的一或多者的任何組合及所有組合。諸如「……中的至少一者」的表達在位於元件清單之前時修飾元件的整個清單，而並不修飾清單的個別元件。另外，當描述本發明概念的實施例時「可」的使用指代「本發明的一或多個實施例」。此外，術語「例示性」意欲指代實例或說明。如本文中所使用，可認為術語「使用」分別與術語「利用」同義。
應理解，當稱元件或層在另一元件或層「上」、「連接至」另一元件或層、「耦接至」另一元件或層或「與」另一元件或層「相鄰」時，其可直接在所述另一元件或層上，直接連接至所述另一元件或層、直接耦接至所述另一元件或層或直接與所述另一元件或層相鄰，或可存在一或多個介入元件或介入層。相比之下，當元件或層被稱作「直接在」另一元件或層「上」、「直接連接至」另一元件或層、「直接耦接至」另一元件或層或「緊鄰於」另一元件或層時，不存在介入元件或介入層。
本文中所列舉的任何數值範圍意欲包含所列舉的範圍內包含的具有相同數值精確度的所有子範圍。舉例而言，範圍「1.0至10.0」意欲包含所列舉的最小值1.0與所列舉的最大值10.0之間（且包括所述最小值及最大值）的所有子範圍，即具有等於或大於1.0的最小值及等於或小於10.0的最大值，諸如2.4至7.6。本文中所列舉的任何最大數值限制意欲包含其中所包含的所有較低數值限制，且本說明書中所列舉的任何最小數值限制意欲包含其中所包含的所有較高數值限制。
儘管製造自對準垂直場效電晶體的方法的例示性實施例已經特定描述且說明於本文中，但對於熟習此項技術者而言許多修改及變化將顯而易見。因此，應理解，可與本文中的特定描述不同地體現製造根據本發明的原理所構造的自對準垂直場效電晶體的方法。亦在以下申請專利範圍及其等效物中界定本發明。
110‧‧‧閘極 120‧‧‧垂直通道 130‧‧‧源極接觸結構 140‧‧‧汲極接觸結構 150‧‧‧閘極接觸結構 205‧‧‧非晶碳層 210‧‧‧經摻雜氧化物層 215‧‧‧未經摻雜氧化物層 220‧‧‧氮化矽層 225‧‧‧光阻層 230‧‧‧抗反射塗層 235‧‧‧基板 240‧‧‧溝槽 245‧‧‧淺溝槽隔離結構 310‧‧‧氧化物內襯 410‧‧‧垂直奈米薄片 420‧‧‧氧化物層 510‧‧‧高介電常數絕緣層 520‧‧‧閘極導體 530‧‧‧PN接面 540‧‧‧經重度摻雜區域 710‧‧‧接觸層 1010‧‧‧頂部接觸件 1020‧‧‧閘極接觸件 1030‧‧‧底部接觸件
將參看說明書、申請專利範圍以及附圖來瞭解及理解本發明的這些特徵及優點以及其他特徵及優點，其中： 圖1為根據本發明的實施例的垂直場效電晶體的透視剖視圖。 圖2為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖3為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖4為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖5為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖6為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖7為根據本發明的實施例的在用於製造垂直場效電晶體的製程期間形成的中間結構的橫截面圖。 圖8為根據本發明的實施例的垂直場效電晶體的模擬電流分佈的平面圖。 圖9為根據本發明的實施例的隨源極汲極接觸層厚度而變的有效電流的曲線圖。 圖10為根據本發明的實施例的垂直場效電晶體的橫截面圖。
110‧‧‧閘極
120‧‧‧垂直通道
130‧‧‧源極接觸結構
140‧‧‧汲極接觸結構
150‧‧‧閘極接觸結構

Claims (20)

  1. 一種用於製造場效電晶體的方法，所述場效電晶體具有通道及閘極，所述用於製造場效電晶體的方法包括：將包含犧牲層的多個層沈積於基板上；蝕刻第一溝槽貫穿所述多個層；在所述第一溝槽中生長垂直半導體薄片以形成所述通道；蝕刻所述犧牲層以形成第一間隙；以及在所述第一間隙中形成導電層，從而形成所述閘極，其中所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道包括將所述第一溝槽填滿。
  2. 如申請專利範圍第1項所述的用於製造場效電晶體的方法，其中所述犧牲層包括作為主要組分的氮化矽。
  3. 如申請專利範圍第1項所述的用於製造場效電晶體的方法，其中所述多個層更包括：兩個非晶碳層；兩個未經摻雜氧化物層；以及兩個經摻雜氧化物層。
  4. 如申請專利範圍第3項所述的用於製造場效電晶體的方法，其中所述多個層包括自所述基板起按次序的以下各者：所述兩個非晶碳層的第一非晶碳層；所述兩個經摻雜氧化物層的第一經摻雜氧化物層；所述兩個未經摻雜氧化物層的第一未經摻雜氧化物層；所述犧牲層，其包括作為主要組分的氮化矽；所述兩個未經摻雜氧化物層的第二未經摻雜氧化物層； 所述兩個經摻雜氧化物層的第二經摻雜氧化物層；以及所述兩個非晶碳層的第二非晶碳層。
  5. 如申請專利範圍第4項所述的用於製造場效電晶體的方法，其中所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道包括：生長所述垂直半導體薄片以包含在所述垂直半導體薄片的下端處的第一摻雜劑；以及生長所述垂直半導體薄片以包含在所述垂直半導體薄片的上端處的所述第一摻雜劑。
  6. 如申請專利範圍第5項所述的用於製造場效電晶體的方法，其中：所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道產生中間結構，以及所述經摻雜氧化物層中的每一者包含第二摻雜劑，所述用於製造場效電晶體的方法更包括：加熱所述中間結構以使得所述第二摻雜劑擴散至所述經摻雜氧化物層之外且擴散至所述垂直半導體薄片中。
  7. 如申請專利範圍第6項所述的用於製造場效電晶體的方法，其中：包含所述第一摻雜劑導致所述垂直半導體薄片的下端具有第一導電性類型及所述垂直半導體薄片的所述上端具有所述第一導電性類型，以及選擇所述第二摻雜劑以在擴散至所述垂直半導體薄片中時產生具有所述第一導電性類型的半導體材料。
  8. 如申請專利範圍第7項所述的用於製造場效電晶體的方法，所述第一未經摻雜氧化物層與所述第二未經摻雜氧化物層的厚度相同，且選擇所述厚度以提供擴散至所述垂直半導體薄片中的所述第二摻雜劑的所要分離。
  9. 如申請專利範圍第6項所述的用於製造場效電晶體的方法，其中所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道產生中間結構，所述垂直半導體薄片在所述兩個非晶碳層中的較高者的上部表面上方延伸。
  10. 如申請專利範圍第9項所述的用於製造場效電晶體的方法，更包括在所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道之後且在蝕刻所述犧牲層以形成所述第一間隙之前：利用化學機械平坦化(CMP)使所述中間結構的上部表面平坦化。
  11. 如申請專利範圍第3項所述的用於製造場效電晶體的方法，更包括在所述在所述第一間隙中形成所述導電層從而形成所述閘極之後：蝕刻所述兩個非晶碳層中的較低者以形成第二間隙；蝕刻所述兩個非晶碳層中的較高者以形成第三間隙；在所述第二間隙中形成下部接觸層；以及在所述第三間隙中形成上部接觸層。
  12. 如申請專利範圍第11項所述的用於製造場效電晶體的方法，更包括：在所述蝕刻所述第一溝槽貫穿所述多個層之後且在所述在所 述第一溝槽中生長所述垂直半導體薄片以形成所述通道之前：沈積氧化物內襯；以及在所述蝕刻所述兩個非晶碳層中的所述較低者以形成所述第二間隙及所述蝕刻所述兩個非晶碳層中的所述較高者以形成所述第三間隙之後且在所述在所述第二間隙中形成所述下部接觸層及所述在所述第三間隙中形成所述上部接觸層之前：蝕刻所述第二間隙內及所述第三間隙內的所述氧化物內襯。
  13. 如申請專利範圍第3項所述的用於製造場效電晶體的方法，更包括在所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道之後且在所述在所述第一間隙中形成所述導電層從而形成所述閘極之前：蝕刻所述兩個非晶碳層中的較低者以形成第二間隙；蝕刻所述兩個非晶碳層中的較高者以形成第三間隙；在所述第二間隙中形成下部接觸層；以及在所述第三間隙中形成上部接觸層。
  14. 如申請專利範圍第13項所述的用於製造場效電晶體的方法，更包括：在所述蝕刻所述第一溝槽貫穿所述多個層之後且在所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道之前：沈積氧化物內襯；以及在所述蝕刻所述兩個非晶碳層中的所述較低者以形成所述第二間隙及所述蝕刻所述兩個非晶碳層中的所述較高者以形成所述第三間隙之後且在所述在所述第二間隙中形成所述下部接觸層及所述在所述第三間隙中形成所述上部接觸層之前： 蝕刻所述第二間隙內及所述第三間隙內的所述氧化物內襯。
  15. 如申請專利範圍第1項所述的用於製造場效電晶體的方法，更包括在所述蝕刻所述犧牲層以形成所述第一間隙之後且在所述在所述第一間隙中形成所述導電層從而形成所述閘極之前：在所述第一間隙的表面上形成介電層。
  16. 如申請專利範圍第1項所述的用於製造場效電晶體的方法，更包括在所述蝕刻所述第一溝槽貫穿所述多個層之後且在所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道之前：沈積氧化物內襯。
  17. 如申請專利範圍第16項所述的用於製造場效電晶體的方法，更包括在所述沈積所述氧化物內襯之後且在所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道之前：使用反應性離子蝕刻製程移除所述氧化物內襯的水平部分。
  18. 如申請專利範圍第1項所述的用於製造場效電晶體的方法，其中所述在所述第一溝槽中生長所述垂直半導體薄片以形成所述通道包括利用磊晶製程生長所述垂直半導體薄片。
  19. 一種微電子結構，包括：基板：所述基板上的第一導電接觸層；所述第一導電接觸層上的第一經摻雜氧化物層；所述第一經摻雜氧化物層上的第一未經摻雜氧化物層；所述第一未經摻雜氧化物層上的第一介電層； 所述第一介電層上的第一導電閘極層；所述第一導電閘極層上的第二介電層；所述第二介電層上的第二未經摻雜氧化物層；所述未經摻雜氧化物層上的第二經摻雜氧化物層；所述第二經摻雜氧化物層上的第二導電接觸層；第一經摻雜矽垂直奈米薄片，其延伸穿過：所述第二導電接觸層；所述第二經摻雜氧化物層；所述第二未經摻雜氧化物層；所述第二介電層；所述第一導電閘極層；所述第一介電層；所述第一未經摻雜氧化物層；所述第一經摻雜氧化物層；以及所述第一導電接觸層，所述第一導電閘極層藉由第三介電層與所述第一經摻雜矽垂直奈米薄片分離：所述第三介電層，其平行於所述第一經摻雜矽垂直奈米薄片以及接合所述第一介電層與所述第二介電層。
  20. 如申請專利範圍第19項所述的微電子結構，其中所述第一經摻雜矽垂直奈米薄片包括：第一PN接面；以及第二PN接面，所述第一PN接面處於所述第一介電層的下部表面下方第一 距離處，所述第二PN接面處於所述第二介電層的上部表面上方第二距離處，所述第一距離與所述第二距離相同。
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