TW202006953A - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TW202006953A
TW202006953A TW108108296A TW108108296A TW202006953A TW 202006953 A TW202006953 A TW 202006953A TW 108108296 A TW108108296 A TW 108108296A TW 108108296 A TW108108296 A TW 108108296A TW 202006953 A TW202006953 A TW 202006953A
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TWI714020B (zh
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大藤徹
蔡慶威
黃俊嘉
程冠倫
徐繼興
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台灣積體電路製造股份有限公司
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Abstract

本揭露描述一種效能可調式之環繞閘極(gate-all-around,GAA)奈米片材場效電晶體的形成方法。此方法包含在基板上設置具有不同寬度之第一和一第二垂直結構，第一和一第二垂直結構具有一頂部，且頂部包含具有穿插的第一和第二奈米片材層的多層奈米片材堆疊。此方法亦包含設置犧牲閘極結構於第一和第二垂直結構的頂部之上；沉積隔離層於第一和第二垂直結構之上，使隔離層圍繞犧牲閘極結構之側壁；蝕刻犧牲閘極結構以從第一和第二垂直結構中暴露各個多層奈米片材堆疊；從各暴露的多層奈米片材堆疊中移除第二奈米片材層以形成懸浮的第一奈米片材層。

Description

高效能金氧半場效電晶體
應用於行動裝置(例如：行動計算、智慧型手機、平板電腦、智能裝備...等)之積體電路(ICs)具有嚴格的功率和效能要求。舉例來說，P型和N型場效電晶體(FETs)在芯片的邏輯和靜態隨機存取記憶體(SRAM)的區域內表現出平衡的切換效能(例如：相似的開啟和關閉特性)。然而，由於場效電晶體的尺寸的改變，P型和N型場效電晶體可能會產生一種效能不匹配。舉例來說，由於在它們各自的製造中使用不同材料、不同晶格排列，或是應用他們各自通道區域的不同應變工程條件，使得N型場效電晶體可以變得比P型場效電晶體更快速。
100‧‧‧方法
105、110、115、120、125、130、140‧‧‧操作
200‧‧‧基板
200t‧‧‧頂面
300‧‧‧硬遮罩層
400‧‧‧凹槽區
405‧‧‧水平面
410‧‧‧垂直表面
500‧‧‧多層奈米片材堆疊
510‧‧‧矽奈米片材層
505‧‧‧矽鍺奈米片材層
505p、510p‧‧‧間距
510t、510t1、510t2‧‧‧厚度
510w、510w1、510w2、700w、805w、810w‧‧‧寬度
515‧‧‧部分
520‧‧‧氧化物
525‧‧‧覆蓋層
700‧‧‧圖案化光阻結構
805‧‧‧鰭片
805h、810h‧‧‧高度
810、810'‧‧‧垂直結構
900‧‧‧犧牲閘極結構
905‧‧‧襯墊
910、1010‧‧‧絕緣層
915‧‧‧閘極間隔物(分隔物)
920‧‧‧覆蓋層
925‧‧‧氧化物層
930‧‧‧犧牲閘電極
935‧‧‧犧牲閘極介電層
1000‧‧‧磊晶堆疊
1005‧‧‧保護性氮化物層
1015‧‧‧開口
1300‧‧‧金屬閘極結構
1305‧‧‧高k介電層
1310‧‧‧金屬閘電極堆疊
1315‧‧‧線
1320‧‧‧氮化物覆蓋層
當結合隨附圖式進行閱讀時，本揭露發明實施例之詳細描述將能被充分地理解。應注意，根據業界標準實務，各特徵並非按比例繪製且僅用於圖示目的。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。在說明書及圖式中以相同的標號表示相似的特徵。
第1圖係依據本揭露的一些實施方法呈現用於製造環繞閘極(gate-all-around,GAA)奈米片材場效電晶體之方法的流程圖。
第2圖至第13圖係依據本揭露的一些實施方法，呈現在不同製造階段之環繞閘極奈米片材場效電晶體結構的等角視圖。
第14圖係依據本揭露的一些實施方法，呈現環繞閘極奈米片材場效電晶體的一剖視圖。
第15圖係依據本揭露的一些實施方法，呈現具有不同奈米片材層寬度之二個環繞閘極奈米片材場效電晶體的剖視圖。
第16圖係依據本揭露的一些實施方法，呈現具有環繞閘極奈米片材場效電晶體和鰭片場效電晶體的混合結構的剖視圖。
第17圖係依據本揭露的一些實施方法，呈現具有減少之奈米片層數量的環繞閘極奈米片材場效電晶體的等角視圖。
第18圖係依據本揭露的一些實施方法，呈現具有不同數量之奈米片材層的二個環繞閘極奈米片材場效電晶體的剖視圖。
應理解，以下揭示內容提供許多不同實施例或實例，以便實施本揭露發明實施例之不同特徵。以下揭露內容對於實施所提供主題的不同特徵提供許多不同的實施方法或實例，下文描述組件及排列之特定實例以簡化本揭露書的內容。當然，該等實例僅為示例且並不意欲為限制性。舉 例來說，在下文的描述中，形成於一第二特徵之上的一第一特徵可包含該第一和第二特徵係以直接接觸形成的實施方法，且亦可包含形成於該第一和第二特徵之間的附加實施特徵的實施方法，使第一和第二特徵不直接接觸。
另外，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」及類似者)來描述諸圖中所圖示之一元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中裝置之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向上)且因此可同樣解讀本文所使用之空間相對性描述詞。
在此使用之術語「標稱」係指在一產品或一過程之設計階段的期間，設定一元件或一過程操作的一特徵或一參數的一期望值或目標值，以及在該期望值之上和/或之下的一範圍值。該範圍值通常是由於製造過程或公差的微小變化。
在此使用之術語「實質上」係表示基於與主題半導體裝置相關聯之一特定技術節點而變化的一給定量的數值。基於該特定技術節點，該術語「實質上」可表示一給定量之數值，其值可於，例如：該值的±5%內變化。
在此使用之術語「大約」係表示一給定數量之數值，其可基於與主題半導體裝置相關聯之一特定技術節點而變化。基於此特定技術節點，此術語「大約」可表示一給 定量之數值，其值可於，例如：該值的10-30%內變化(例如：該值的±10%、±20%或±30%)。
在此使用之術語「垂直」意味著名義上垂直於基板的表面。
在此使用之術語「絕緣層」係指用於電絕緣器(例如：介電層)之層。
應用於行動裝置(例如：行動計算、智慧型手機、平板電腦、智能裝備...等等)之積體電路(ICs)具有嚴格的功率和效能要求。舉例來說，P型和N型場效電晶體(FETs)在芯片的邏輯和靜態隨機存取記憶體(SRAM)的區域內表現出平衡的切換效能(例如：相似的開啟和關閉特性)。然而，由於場效電晶體的尺寸的改變，P型場效電晶體(PFETs)和N型場效電晶體(NFETs)可能會產生一種效能不匹配。舉例來說，由於(i)在它們各自的製造過程中使用不同的材料(ii)不同的晶格排列(iii)應用於場效電晶體之通道區域的不同應變工程條件或其組合，使得N型場效電晶體可弱於P型場效電晶體。此外，當閘極失去對通道區域之控制時，雙閘極或三閘極場效電晶體可遭受短通道效應。舉例來說，在雙閘極或三閘極中積極改變尺寸可導致汲極感應能障降低(DIBL)。例如，由於汲極電壓導致通道上的閘極控制耗損。
此揭露所描述之實施方法係涉及一種製造方法和結構，其提供具有效能可調式/可調節之不同類型的環繞閘極(GAA)奈米片材場效電晶體(nano-sheet FETs)。舉例 來說，N型場效電晶體和P型場效電晶體可調式環繞閘極奈米片材場效電晶體(於本文亦可稱為奈米片材場效電晶體)均可源自於多層奈米片材堆疊，多層奈米片材堆疊具有可交替的第一和第二奈米片材層對。作為實施例而非限制，在多層奈米片材堆疊中，第一和第二奈米片材層可分別包括磊晶生長的矽鍺(SiGe)和矽(Si)奈米片材層。在一些實施方法中，N型場效電晶體之特徵為具有矽奈米片材層的通道區域，而P型場效電晶體之特徵為具有矽鍺奈米片材層的通道區域。於各個奈米片材場效電晶體中，奈米片材層的尺寸和數量可於奈米片材場效電晶體製造過程之早期階段進行控制，以生成不同類型之環繞閘極奈米片材場效電晶體。此外，奈米片材層之尺寸和數量可用於調整所得的環繞閘極奈米片材場效電晶體的電器效能。舉例來說，所得的奈米片材環繞閘極可展現優異的閘極控制(例如：低汲極感應能障降低)，以及可調節的驅動電流和功率消耗。再者，透過使用本文所描述之實施例，可以在相同基板上形成具有鰭片場效電晶體和不同種類之環繞閘極奈米片材場效電晶體的混合裝置。
第1圖係根據一些實施方法呈現製造方法100的流程圖。製造方法100係根據一些實施方法描述環繞閘極奈米片材場效電晶體的形成。可在方法100的各種操作間執行其他製造操作，且可以僅為了清楚起見而省略。本揭露不限於此操作的描述。相反地，其他操係作落於本揭露之精神和範圍內。應理解，可執行額外的操作，此外，執行本 揭露所提供之內容時，並非所有的操作都是必須的。再者，一些操作可同時執行或者以不同於第1圖之順序執行。在一些實施方法中，除了當前所描述之操作或代替當前所描述之操作外，可執行一個或多個其他操作。出於說明性之目的，請參考第2圖至第18圖中繪示之實施方法所描述的製造方法100。
方法100起始於操作105，並在基板上形成多層奈米片材堆疊。根據一些實施方法，多層奈米片材堆疊包含可交替的第一和第二奈米片材層配對，所述多個第一和第二奈米片材層互相在彼此的頂部垂直生長。第2圖至第8圖係部分製造結構之等角視圖，其可用於描述操作105的製造階段。舉例來說，第2圖係根據一些實施方法所示基板200之部份的等角視圖。作為實施例而非限制，基板200可作為主體半導體晶圓(bulk semiconductor wafer)或絕緣層上半導體(semiconductor-on-insulator,SOI)晶圓的頂部半導體層(未繪示)，例如，絕緣層上覆矽。此外，基板200可包含矽晶，其頂面200t平行於(100)晶面(例如，x-y平面)。在一些實施方法中，基板200可包含另一基本半導體，例如(i)鍺(Ge)；(ii)包含碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)和/或銻化銦(InSb)之化合物半導體；(iii)包含矽鍺(SiGe)、砷磷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化銦鎵(GaInP)和/或砷磷化銦鎵(GaInAsP)之合金半導體；或(iv)其組合。
出於實施例之目的，將在矽晶的背景下描述方法100中平行於頂面200t之(100)晶面的基板200。基於本揭露的內容，可使用如上所述之其他材料。此些材料作落於本揭露之精神和範圍內。
在一些實施方法中，如第3圖所示，多層奈米片材堆疊製造起始於在基板200上沉積以及圖案化硬遮罩層300。因此，可暴露基板200的選定區域，如第3圖中所示之基板200的頂面200t。如上所述，基板200的頂面200t係平行於(100)晶面(例如x-y平面)。作為實施例而非限制，硬遮罩層300可包含氮化矽(Si3N4，此後“SiN”)、矽氮化碳(SiCN)、二氧化矽(SiO2)以及其他適合的材料或任何其結合。可對硬遮罩層300進行圖案化，使得基板200的頂面200t可暴露於多個位置中。如第4圖所示，一連串的各向異性乾蝕刻製程可蝕刻暴露的基板200，以形成一個或多個凹槽區400。凹槽區400的深度(例如，在z方向)可透過乾蝕刻製程來控制。在一些實施方法中，可根據硬遮罩蓋300的圖案設計，於基板200中形成多於一個相似於凹槽區400的凹槽區。凹槽區400具有底部水平面405以及一個或多個垂直表面410(例如，垂直側壁)。根據一些實施方式，水平面405係平行於(100)晶面(例如，x-y平面)，且垂直表面410係平行於(100)晶面(例如，y-z平面)。作為實施例而非限制，凹槽區400的面積(例如，水平面405的面積)可為約500 x 0.1平方微米(例如，分別為x方向和y方向)，其在垂直之z-方向的深度係介於約100奈至約 200奈米之間。然而，上述提及的體積並非限制性的，且凹槽區400可小於或大於上述提及之體積。
接著，穿插的第一和第二奈米片材層配對可生長於凹槽區400中，以形成填充凹槽區400的多層奈米片材堆疊。在一些實施方法中，第一和第二奈米片材層可使用暴露的水平面405(例如，x-y平面)作為晶種表面，於凹槽區400中磊晶地生長。如上所述，暴露的水平面係平行於基板200的頂面，因而共享相同的晶體方向(例如，平行於(100)晶面，x-y平面)。因此，形成於暴露之水平面405的磊晶層將具有與如同生長在基板200之頂面200t上(如第2圖所示)相同的晶體方向，奈米片材層可以不用在硬遮罩層300覆蓋之基板200的區域上生長。因此，在一些實施方法中，奈米片材層的生長被限制於凹槽區400之暴露表面。在一些實施方法中，凹槽區400的垂直表面410可用硬遮罩層覆蓋以防止奈米片材層生長。在一些實施方法中，奈米片材層的磊晶傾向於在(100)晶面上生長(例如，在暴露的水平面405上)，與(110)晶面(例如，垂直表面410)相反。
在一些實施方法中，第一和第二奈米片材層分別包含矽鍺和矽。另外，第一奈米片材層可包含第III族到第V族之化合物半導體，例如：砷化鎵、磷化銦、磷化鎵、氮化鎵...等。出於實施例之目的，在方法100中奈米片材多層堆疊將在穿插的矽鍺和矽奈米片材磊晶層的背景下描 述。基於本揭露所示之內容，可使用如上述所提及的其他材料，此些材料係作落於本揭露之精神和範圍內。
作為實施例而非限制，可使用在矽鍺和矽奈米片材層生長的前驅氣體包含矽烷(SiH4)、二矽烷(Si2H6)、鍺烷(GeH4)、二鍺烷(Ge2H6)、二氯矽烷(SiH2Cl2)、任何其他合適的氣體或其組合。根據一些實施方法，第5圖係於凹槽區400中形成多層奈米片材堆疊500後之基板200的等角視圖。作為實施例而非限制，多層奈米片材堆疊500可包含穿插的矽鍺奈米片材層505(底層)和矽奈米片材層510(上層)的配對。矽鍺奈米片材層505可含有約10%至約50%的鍺(例如，15%、20%、30%、40%...等)。矽鍺奈米片材層中鍺的存在增加矽鍺奈米片材層中的本質應力，且改善P型奈米片材場效電晶體的電洞移動力。在矽鍺奈米片材層中，鍺濃度低於10%可提供有限的電洞移動力效益，且鍺濃度高於50%時可導致疊差和缺陷。在矽鍺奈米片材堆疊中的缺陷可能對P型奈米片材場效電晶體有害，因為它們會增加通道電阻。在一些實施方法中，如第5圖所示，多層奈米片材堆疊的頂層係為矽奈米片材層510，且底層係為矽鍺奈米片材層505。
在一些實施方法中，矽奈米片材層510的厚度可控制矽鍺奈米片材層505彼此之間的間距(或間隔)，並且類似地，矽鍺奈米片材層505之厚度可控制矽奈米片材層510彼此之間的間距(或間隔)。舉例來說，請參考第6圖，其係為第5圖中之部分515的放大視圖，矽奈米片材層510 的厚度510t可用於限定矽鍺奈米片材層505的間距505p。於此製造階段定義了相似類型的奈米片材層的間距。此外，每個奈米片材層可具有相同或不同的厚度。在一些實施方法中，矽鍺奈米片材層505和矽奈米片材層510之厚度範圍可在約5奈米至約20奈米之間(例如，從5奈米至10奈米、從10奈米至15奈米、從5奈米至15奈米、從10奈米至20奈米...等)。由於矽鍺和矽奈米片材層分別生長，鍺奈米片材層505和矽奈米片材層510彼此間具有相同或不同之厚度。再者，矽鍺奈米片材層可具有彼此相同或不同之厚度，並且相似地，矽奈米片材層彼此間具有相同或不同之厚度。
在一些實施方法中，多層奈米片材堆疊500可包括多達10至15個的總奈米片材層(例如，約5至6對的矽鍺/矽奈米片材層)。然而，可能有更多或更少的奈米片材層，其取決於所得的奈米片材場效電晶體的設計。在一些實施方法中，可調整如第4圖中所示之凹槽區400的深度，以適應更多或更少數量的矽鍺和矽奈米片材層。在一些實施方法中，多層奈米片材堆疊500的高度(在垂直的Z-方向上)可介於約100奈米至約200奈米的範圍內(例如，介於100奈米至150奈米、140奈米至180奈米、160奈米至200奈米...等)。再者，多層奈米片材堆疊500的高度可等同於凹槽區400的深度，使得多層奈米片材堆疊500的頂面與基板200中未凹槽區的頂面實質上係共平面。然而，此並並非一種限制，且更短或更高的多層奈米片材堆疊500係 為可能的。另外，如上所述，每個奈米片材層和多層奈米片材堆疊的厚度並非限制性的。
在形成多層奈米片材堆疊500後，移除(例如，用濕的清潔劑剝離)硬遮罩層300(未示於第5圖中)。如第5圖所示，氧化物520和覆蓋層525可實質上生長於基板200之未凹槽區和多層奈米片材堆疊500之上。在一些實施方法中，氧化物520包含二氧化矽層，且覆蓋層525包含氮化物層，例如氮化矽。
請參考第1圖，方法100繼續操作110，且通過蝕刻如第5圖中所示之多層奈米片材堆疊500的選擇部分以形成垂直結構。舉例來說，請參照第7圖，可在覆蓋層525上旋塗(spin-coated)光阻層，並隨後圖案化以形成圖案化光阻結構700。在一些實施方法中，如第7圖所示，光阻結構700係沿著y軸或(110)方向定向。圖案化光阻結構可在隨後的蝕刻製程作為蝕刻光罩。於蝕刻製程期間，多層奈米片材堆疊500之未被光阻結構700遮罩的部分將被移除，以形成具有多層奈米片材堆疊的垂直結構，其沿著y軸或(110)方向定向。在一些實施方法中，在(110)方向中之垂直結構其方向係為故意的，使得所得的奈米片材場效電晶體的通道區域沿著(110)方向形成。此意味著所得之奈米片材場效電晶體的電流將沿著(110)方向。沿著(110)方向之電流方向有利於N型場效電晶體中的電子移動率。
相似地，位於基板200之上的光阻結構700可用於形成由基板材料組成之鰭片。所述多個單一材料鰭片 (此後為”鰭片”)可用於在基板200上形成雙閘極或三閘極鰭狀場效電晶體。
因此，圖案化光阻結構700之寬度700w可限定垂直結構的寬度，其隨後限定奈米片材場效電晶體中通道區域的寬度。根據一些實施方法，場效電晶體中之通道區域的寬度可決定流過通道區域的電流量。舉例來說，寬通道區域可承載比窄通道區域更高的電流密度。然而，窄通道區域可提供比寬通道區域更好的閘極控制。因此，可調整多層奈米片材堆疊中每個垂直結構的寬度，以在通道區域之上提供電流密度和閘極控制間的平衡。此外，藉由控制各圖案化光阻結構700的寬度700w，可在基板200之上形成具有不同寬度的垂直結構。換句話說，奈米片材場效電晶體可在基板上任何傾向的位置建立不同的奈米片材層寬度。
第8圖所示為上述蝕刻製程後所得的結構，例如鰭片805和具有多層奈米片材堆疊500的垂直結構810。如上所述，鰭片805係由基板材料所構成，例如：矽或另一基本半導體，例如(i)鍺；(ii)化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；(iii)合金半導體，包含矽鍺、磷砷化鎵、砷化銦鋁、砷化鋁鎵、砷化鎵銦、磷化銦鎵和/或砷磷化銦鎵；或(iv)其組合。
在一些實施方法中，鰭片805的寬度805w範圍係從約4奈米至約15奈米(例如：從4奈米至10奈米、8奈米至12奈米、10奈米至15奈米...等)，且具有奈米片 材堆疊500之垂直結構810的寬度810w範圍係從約4奈米至約50奈米(例如：從4奈米至10奈米、8奈米至15奈米、10奈米至25奈米、15奈米至30奈米、20奈米至50奈米...等)。因此，可形成比鰭片805更寬的具有多層奈米片材堆疊500之垂直結構810。
第8圖之配置在本揭露中稱為「混合」配置，其中具有多層奈米片材堆疊的垂直結構與鰭片同時形成於基板200上。根據一些實施方法，多層奈米片材垂直結構810上將形成奈米片材場效電晶體，且鰭片805上將形成鰭狀場效電晶體。如上所述，基板200上之鰭片805和垂直結構810的不同排列係為可能的；舉例來說，多層奈米片材垂直結構810之列陣、矽鰭片805之列陣或其組合。因此，奈米片材場效電晶體的組合在基板200係為可能的。
此外，多層奈米片材垂直結構810可形成為具有不同的寬度810w。因此，在基板200上可形成具有奈米片材寬度(例如，通道寬度)之範圍的奈米片材場效電晶體。
在一些實施方法中，鰭片805的高度805h係等於或不同於垂直結構810的高度810h。舉例來說，805h可高於或矮於810h。在一些實施方法中，810h的範圍可從約100奈米至約200奈米(例如：100奈米至150奈米、140奈米至180奈米、160奈米至200奈米...等)。
請參考第1圖，方法100繼續操作115，且在具有多層奈米片材堆疊500的垂直結構810上形成犧牲閘極結構。在一些實施方法中，根據操作115，犧牲閘極結構 亦可同時形成於鰭片805上。出於實施例之目的，操作115將針對在具有多層奈米片材堆疊500之垂直結構810上形成犧牲閘極結構來作描述。基於本揭露的內容，如上所述，操作115可用於在犧牲閘極結構上形成鰭片805以及具有多層奈米片材堆疊500的垂直結構。
第9圖係形成於二個垂直結構810之上的犧牲閘極結構900的等角視圖，每個垂直結構810都具有多層奈米片材堆疊，犧牲閘極結構900係沿著x軸形成(例如，垂直於垂直結構810的長度)。在一些實施方法中，與第8圖相比，第9圖係為後來的「製造階段」，因此，第9圖包含額外的結構元件，例如襯墊905、絕緣層910、閘極間隔物915、覆蓋層920和氧化物層925。
在一些實施方法中，犧牲閘極結構900包含犧牲閘電極930和犧牲閘極介電層935。作為實施例而非限制，犧牲閘極介電層935在犧牲閘電極930之前沉積，且其插入於垂直結構810和犧牲閘極結構930之間。根據一些實施方法，犧牲閘極介電層935包含二氧化矽或氮氧化矽(SiON)，且其可在隨後的閘極結構替代操作中以高介電常數(高-k)介電質取代。另外，犧牲閘電極930可包含聚矽晶(多晶矽)，且可在隨後的閘極結構替代操作中以金屬閘電極堆疊取代。作為實施例而非限制，犧牲閘極介電層935和犧牲閘電極930可沉積為毯覆層且利用光刻和蝕刻操作來圖案化，以在多層垂直結構810和絕緣層910上形成犧牲閘極結構900。
應理解，額外的犧牲閘極結構(例如，像犧牲閘極結構900)可與犧牲閘極結構900平行地形成，且垂直於沿著y軸的垂直結構810的投影。因此，第9圖可包含額外的犧牲閘極結構900，其彼此平行且位於垂直結構810上。
在一些實施方法中，絕緣層910可作為隔離結構，例如淺渠溝隔離區(STI)，其包含二氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass,FSG)、低k介電材料(例如，具有低於約3.9的k值)和/或具有填充特性的其他合適介電材料，襯墊可作為氮化物，例如氮化矽。
在用於垂直結構810上源極/汲極點交界處之形成的離子佈植(ion implantation)操作中，閘極間隔物915(或分隔物915)可作為對準光罩。作為實施例而非限制，分隔物915可沉積為覆蓋膜，其可用回蝕過程蝕刻以在犧牲閘極結構900之側壁上形成分隔物915。在一些實施方法中，回蝕過程係為各向異性蝕刻，其相較於垂直表面(例如，在y-z或x-z平面)可更快的從水平面(例如，在x-y平面)上移除間隔物材料層。當間隔物材料層係毯覆沉積時，其可覆蓋垂直結構810之暴露的表面。側壁拉回過程可移除來自於垂直結構之側壁表面的間隔物材料層。
在一些實施方法中，分隔物915可包含介電材料，例如，二氧化矽、氮氧化矽、碳氮化矽、碳氧化矽(SiOC)或氮化矽。在一些實施方法中，分隔物915的厚度範圍可 從約2奈米至約5奈米。分隔物915可作為包含相同或不同材料之一層或多層的堆疊。根據一些實施方法，分隔物915在金屬閘極替換過程中不會被移除，並可做為將取代犧牲閘極結構900之金屬閘極結構的結構元件。
請參考第10圖，源極/汲極(S/D)磊晶堆疊1000可在每個垂直結構810上生長且相鄰於犧牲閘極結構900。在一些實施方法中，磊晶堆疊1000可以是適用於P型奈米片材場效電晶體的硼摻雜矽鍺堆疊，或適用於N型奈米片材場效電晶體的磷摻雜矽層。舉例來說，將在用於P型奈米片材場效電晶體之硼摻雜矽鍺堆疊的背景下，描述硼摻雜矽鍺堆疊磊晶堆疊1000。基於本揭露的內容，亦可生長用於P型奈米片材場效電晶體的硼摻雜矽鍺堆疊。此些源極/汲極磊晶堆疊作落於本揭露之精神和範圍內。此外，由於N型和P型奈米片材場效電晶體可形成於單一基板上，硼摻雜的矽鍺堆疊和磷摻雜的矽層可於穿過基板200之所需的垂直結構810上生長。
在一些實施方法中，可利用矽烷(SiH4)前驅物對磷摻雜(N型)矽源極/汲極層磊晶地生長，可在生長期間將磷摻雜劑導入矽磊晶生長層。在一些實施方法中，磷的濃度範圍可從約1021原子/立方公分至約8x1021原子/立方公分。應理解，前述的摻雜劑濃度範圍並非限制性的，且其他摻雜濃度範圍係作落於本揭露之精神和範圍內。
在一些實施方法中，硼摻雜(P型)矽鍺源極/汲極可作為磊晶堆疊，其可包含二個或更多連續生長的磊晶層 (未示於第10圖中)，且可具有不同的鍺(Ge)原子%和不同的硼摻雜濃度。作為實施例而非限制，第一層可具有範圍從0至約40%的鍺原子%，且硼摻雜濃度範圍從約5x1019原子/立方公分至約1x1021原子/立方公分。第二磊晶層可具有範圍從約20%至約80%的鍺原子%，且硼摻雜濃度範圍從約3x1020原子/立方公分至約5x1021原子/立方公分。最後，第三磊晶層可具有覆蓋層，其可具有與第一層相似的鍺原子%和硼摻雜濃度(例如，對於鍺為0至約40%，對於硼摻雜為約5x1019原子/立方公分至約1x1021原子/立方公分)。此些層的厚度可依據元件效能要求而變化。舉例來說，第一磊晶層可具有範圍從約10奈米至約20奈米的厚度，第二壘晶層可據有範圍從約30奈米至約60奈米的厚度，且第三壘晶層可具有範圍從0至約10奈米的厚度。應理解，前述厚度和摻雜濃度並非限制性的，且其他厚度和摻雜濃度係作落於本揭露之精神和範圍內。
於磊晶堆疊形成後，保護性氮化物層1005可沉積於磊晶堆疊1000、絕緣層910和分隔物915之上。在一些實施方法中，保護性氮化物層1005可具有範圍從約3奈米至約5奈米之厚度。作為實施例而非限制，可藉由保形的沉積過程來沉積保護性氮化物層1005，例如，原子層沉積(ALD)、電漿加強原子層沉積(PEALD)、化學氣相沉積(CVD)、電漿加強化學氣相沉積(PECVD)或任何其他合適的沉積方法。舉例來說，可在約500℃下使用原子層沉積過程來沉積保護性氮化物層1005。根據一些實施方法，在 源極/汲極磊晶堆疊1000上之接觸開口(未示於第10圖中)的形成期間，保護性氮化物層1005可作為後續蝕刻製程的蝕刻終止層(ESL)。
請參考第1圖和第10圖，方法100繼續操作120，且在垂直結構810上形成絕緣層1010以環繞犧牲閘極結構900。根據一些實施方法，絕緣層1010係為層間介電質(ILD)，其包含二氧化矽、碳氧化矽、氮氧化矽、矽氧氮化碳(SiOCN)或矽氮化碳，其可透過化學氣相沉積、物理氣相沉積(PVD)、熱生長過程或任何其他合適的沉積方法來沉積。在一些實施方法中，以此沉積的絕緣層1010可位於犧牲閘極結構900之上，化學機械拋光(CMP)過程可對來自犧牲閘極結構900之頂部的絕緣材料進行拋光，使得絕緣層1010的頂面和犧牲閘極結構900的頂面實質上係為共平面。根據一些實施方法，第10圖所示為上述化學機械拋光過程後的絕緣層1010。應理解，絕緣層1010可在鄰近的犧牲閘極結構900之間延伸著，且為絕緣層1010所環繞的結構元件提供電隔離，舉例來說，犧牲閘極結構900、源極/汲極磊晶堆疊1000以及將形成於鄰近的閘極結構的源極/汲極金屬接觸。在一些實施方法中，自選的覆蓋層或硬遮罩層(未示於第10圖中)可生長於絕緣層1010上，以保護絕緣層1010在閘極替換過程中被蝕刻(例如，在犧牲閘極介電層935蝕刻期間)。
在第1圖中的操作125中，如第11圖所示，可移除犧牲閘極結構900(如第10圖所示)以形成一開口 1015於絕緣層1010中。在一些實施方法中，操作120可包含雙溼蝕刻製程，在此製程中可依序地移除犧牲閘電極930和犧牲閘極介電層935。作為實施例而非限制，可利用第一溼蝕刻製程來移除犧牲閘極結構900，第一溼蝕刻製程設計成對於犧牲閘電極930的多晶矽材料係具有選擇性的。舉例來說，第一溼化學的選擇性可高於約1000：1(例如，10000：1)，使得閘極間隔物915、犧牲閘極介電層935和絕緣層1010不會被第一溼蝕刻製程移除。應理解，由於犧牲閘極介電層935係介於垂直結構810和犧牲閘電極930之間，因此犧牲閘極介電層935可保護垂直結構810之矽鍺/矽奈米片材層505/510在第一溼蝕刻製程期間不被蝕刻。此外請參考第11圖，隨後的溼蝕刻製程可在不蝕刻閘極間隔物915、絕緣層1010和垂直結構810的情況下移除犧牲閘極介電層935。作為實施例而非限制，第二溼蝕刻化學可對犧牲閘極介電層935分別具有選擇性，使得周圍的材料，例如，閘極間隔物915、多層奈米片材堆疊的第一和第二奈米片材層以及絕緣層1010不會被移除。在第二蝕刻化學可蝕刻絕緣層1010的情況下，如稍早所述，覆蓋層或硬遮罩可於操作120後形成於絕緣層1010之上。在一些實施方法中，在操作125以及移除犧牲閘極結構900之後，垂直結構810的矽鍺和矽奈米片材層暴露於開口1015內，而開口1015外的垂直結構810的矽鍺和矽奈米片材層被源極/汲極磊晶堆疊1000、保護性氮化物層1005和絕緣層1010所覆蓋。
在方法100之操作130中，可從開口1015中將矽鍺奈米片材層505移除，使得N型奈米片材場效電晶體可形成於開口1015上。在一些實施方法中，如果源極/汲極磊晶堆疊1000係為硼摻雜的矽鍺推疊(例如，而非磷摻雜的矽層)，可從開口1015移除矽奈米片材層，而非矽鍺奈米片材層505，以形成P型奈米片材場效電晶體。換句話說，在操作130中，假設適當的源極/汲極堆疊1000類型(例如，矽鍺或磷摻雜的矽)已經在垂直結構810上生長，可從開口1015中移除矽或矽鍺奈米片材層。此外，在基板200上的一些位置，可從N型奈米片材場效電晶體移除矽奈米片材層510，而在基板200上的其他位置，可從P型奈米片材場效電晶體移除矽鍺奈米片材層505。作為實施例而非限制，N型和P型奈米片材場效電晶體可依序地形成。舉例來說，用於P型奈米片材場效電晶體的垂直結構810可用硬遮罩、光阻或犧牲閘極結構900來覆蓋，同時從用於N型奈米片材場效電晶體的垂直結構810中移除矽鍺奈米片材層。
出於實施例之目的，將描述操作130，其中可從垂直結構810中移除矽鍺奈米片材層505，以形成N型奈米片材場效電晶體。基於本揭露的內容，如上所述，可從P型奈米片材場效電晶體中交替地移除矽奈米片材層510。因此，從開口1015中移除矽奈米片材層510係作落於本揭露之精神和範圍內。
作為實施例而非限制，可使用對於矽鍺具有選擇性的乾蝕刻製程，實現從開口1015中移除矽鍺奈米片材層505。舉例來說，鹵素化學物可對鍺展現高蝕刻選擇性，對矽展現低蝕刻選擇性。因此，數種鹵素氣體可比矽更快地蝕刻鍺。此外，數種鹵素氣體可比矽更快地蝕刻矽鍺。在一些實施方方法中，鹵素化學物包含以氟為基底和/或以氯為基底的氣體。或者，可使用對矽鍺有高選擇性的溼蝕刻化學。作為實施例而非限制，溼蝕刻化學可包含硫酸(H2SO4)和過氧化氫(H2O2)(SPM)的混合物，或具有過氧化氫的氫氧化銨和水(APM)的混合物。作為操作130的結果，矽奈米片材層510在分隔物915間的開口1015中係懸掛和分離的。
由於操作130的乾或溼蝕刻製程設計成不會蝕刻垂直結構810的矽奈米片材層510(因此通常是任何矽材料)，鰭片805(如第8圖所示)，其可能已經形成於基板200的其他位置，不會受到操作130的乾或溼蝕刻製程影響。
在一些實施方法中，如第12圖所示，金屬閘極結構可形成於暴露的矽奈米片材層510之上的開口1015中，第12圖係如第11圖所示之繞著z軸旋轉45度的結構的等角視圖。舉例來說，請參考第13圖，金屬閘極結構1400包含(i)界面層(未示於第13圖)、(ii)高k介電層1305(例如，具有高於3.9的k值)和(iii)形成於第12圖中的開口1015中的金屬閘電極堆疊1310。出於說明性目的，第13圖包含半導體結構的選定部分，且可包含其他部分(未繪 示)，舉例來說，可包含界面層以及一層或多層的金屬閘電極堆疊1310。
在一些實施方法中，高k介電層1305係可為氧化鉿(HfO2)、鉿矽酸鹽基(hafnium silicate-based)的材料或具有高於3.9之k值的另一合適介電層，其數值係為化學劑量二氧化矽的介電常數並用於作為參考。此外，閘電極堆疊1310可包含位於閘極介電層之上的覆蓋層、一個或多個金屬層、功函數金屬(WFM)堆疊以及金屬填充層。在閘電極堆疊中之金屬層的數量和類型取決於所述多個鰭狀場效電晶的臨界電壓要求。在閘電極堆疊中的示例性金屬層可包含氮化鉭(TaN)底層以及一個或多個氮化鈦(TiN)層。在一些實施方法中，功函數金屬堆疊可包含鈦/鋁(Ti/Al)雙層或鈦-鋁(Ti-Al)合金。功函數金屬堆疊可微調金屬閘電極堆疊1310的功函數並影響所得之鰭狀場效電晶體的臨界電壓。結合功函數金屬堆疊一個或多個氮化鈦層的厚度和數量與功函數金屬堆疊可設置鰭狀場效電晶體的臨界電壓。在一些實施方法中，金屬填充層可包含氮化鈦阻障層和鎢(W)金屬堆疊。高k介電層1305和閘電極堆疊1310並非限制於上述多個材料組合。因此，額外的材料可用於此且作落於本揭露之精神和範圍內。
根據一些實施方法，界面層係於高k介電層1305的沉積期間自然地形成的氧化物，界面層和高k介電層1305係直接形成於開口1015內之第二矽奈米片材層510的暴露表面上(如第12圖所示。金屬閘電極堆疊1310 可隨後沉積於開口1015中的高k介電層1305之上，以完成N型奈米片材場效電晶體或奈米片材N型場效電晶體的形成。第14圖係沿著第13圖的線1315，介於閘極間隔物915之間的垂直結構810的剖視圖。根據一些實施方法，第14圖係為環繞閘極奈米片材N型場效電晶體結構的剖視圖，其中多個矽奈米片材層被至少高k介電層1305和金屬閘電極堆疊1310環繞。如稍早所述，當環繞閘極奈米片材N型場效電晶體導通時，電流沿(110)方向(例如沿著y軸)流動且平行於(100)晶面(例如x-y平面)。
在第14圖中，在垂直結構810中之矽奈米片材層510所示為具有厚度510t和寬度510w，寬度510w實質上等同於如第8圖中所示之垂直結構810的寬度810w。如稍早所述，第7圖所示之矽奈米片材層510的寬度810w可控制於圖案化光阻結構700的寬度700w。藉由調整圖案化光阻結構700的寬度700w，可調製矽奈米片材層510的寬度510w。因此，可在基板200上形成具有不同寬度的多層垂直結構。舉例來說，根據一些實施方法，如第15圖所示，具有不同寬度510w1和510w2的垂直結構810可形成於基板200上。在第15圖的實施例中，510w1係大於510w2。如稍早所述，奈米片材場效電晶體建於垂直結構810上，且擁有不同寬度510w1和510w2的奈米片材層(矽或矽鍺)可具有不同驅動電流能力和汲極感應能障降低行為。根據一些實施方法，因此，可以藉由控制奈米 片材層的寬度，在基板所需的區域中個別調控奈米片材場效電晶體。
此外，並參考第14圖和第15圖，如第6圖所述，在矽奈米片材層的生長期間可控制矽奈米片材層510的厚度510t。另外，並參考第14圖和第15圖，如第6圖所述矽鍺奈米片材層505的厚度可控制矽奈米片材層510的間距510p。
基於上述所示的內容，具有不同尺寸之矽奈米片材層510的垂直結構810可形成於基板200上。類似地，根據一些實施方法，具有不同尺寸之矽鍺奈米片材層505的垂直結構810可形成於基板200上。
根據一些實施方法，第16圖所示為混合結構，其中鰭片805係與垂直結構810相鄰形成。因此，可在垂直結構810上形成的奈米片材環繞閘極N型場效電晶體的結構，以及在鰭片805上形成的N型鰭狀場效電晶體的結構之間共享閘電極堆疊1310。如稍早所述，矽奈米片材層510的寬度510w係可大於鰭片805的寬度805w。根據一些實施方法，形成於垂直結構810上的奈米片材環繞閘極N型場效電晶體相較形成於鰭片805上的N型鰭狀場效電晶體在其通道區域上具有優越的閘極控制。類似地，環繞閘極奈米片材N型場效電晶體可與P型和N型鰭狀場效電晶體相鄰形成。再者，基板200的某些區域可配置為僅具有奈米片材環繞閘極N型場效電晶體或P型場效電晶體、P型和N型鰭狀場效電晶體或是其組合。
請參考第13圖，氮化物覆蓋層1320可形成於金屬閘電極堆疊1310之上。在一些實施方法中，源極/汲極接觸的形成如下，其中接觸形成於垂直穿過絕緣層1010的源極/汲極磊晶堆疊1000上(未繪示於第13圖中)。
第1圖的方法100亦可包含可選操作140，其中移除或凹陷金屬閘極結構1300的金屬閘電極堆疊1310的一部份，以移除垂直結構810多達一半的矽奈米片材層510。作為實施例而非限制，可在自選操作140期間移除一至三個矽奈米片材層510，以形成具有六個矽奈米片材層的奈米片材N型場效電晶體。根據一些實施方法，移除(例如，切割)一部分的閘電極堆疊1310和相對應數量的矽奈米片材層510可減少環繞閘極片材N型場效電晶體的功率消耗。可在基板200上的一或多個環繞閘極奈米片材N型場效電晶體上選擇性地執行自選操作140，以調製環繞閘極奈米片材N型場效電晶體的驅動電流和功率消耗。因此，根據一些實施方法，操作140可應用於環繞閘極奈米片材P型場效電晶體。
作為實施例而非限制，第17圖係為在方法100的自選操作140後沿著第13圖y-z平面的剖視圖。如上所述，部份金屬閘極結構1300已被移除或凹陷，使得多達一半的矽奈米片材層510從垂直結構的頂部被移除。在一些實施方法中，基板200可具有擁有改良的閘電極結構1300的多個環繞閘極奈米片材場效電晶體。在自選操作140之 後，氮化物層(例如，類似於氮化物層1320)可生長於改良的金屬閘極結構1300之上，未示於第17圖中。
第18圖係根據此揭露之另一實施方法的結構的剖視圖，其中二個環繞閘極奈米片材N型場效電晶體的剖面係繪示於不同的垂直結構810和810'上。作為操作140的結果。垂直結構810和810'分別具有不同的矽奈米片材層寬度(例如，510w1和510w2)以及不同數量的奈米片材層。在第18圖的實施例中，510w1係比510w2更寬。然而，此並非限制的，且510w1可具有等於或窄於510w2的寬度。此外，矽奈米片材層510t1和510t2的厚度可為相同或不同的。舉例來說，510t1
Figure 108108296-A0202-12-0026-21
510t2或510t1
Figure 108108296-A0202-12-0026-22
510t2。在一些實施方法中，在垂直結構810'上的環繞閘極奈米片材N型場效電晶體相較於垂直結構810上的環繞閘極奈米片材，可具有較低驅動電流能力的低功率奈米片材場效電晶體。再者，810和810'可作落於基板200之相同或不同的區域上。舉例來說，垂直結構810和810'彼此間可不相鄰。
在一些實施方法中，方法100的操作140係在犧牲閘極結構900後以及在源極/汲極磊晶堆疊1000上形成源極/汲極接觸之前執行。
於本揭露所描述之實施方法係關於具有效能可調式之(例如，可調式驅動電流和功率消耗)環繞閘極奈米片材N型場效電晶體和P型場效電晶體的形成方法。在一些實施方法中，可調式N型和/或P型奈米片材場效電晶體的 通道區域可形成於垂直結構，其垂直結構具有在彼此頂部堆積之穿插的第一和第二奈米片材層對。作為實施例而非限制，環繞閘極奈米片材N型場效電晶體可包含矽奈米片材層，且奈米片材環繞閘極P型場效電晶體可包含矽鍺奈米片材層。在一些實施方法中，於製造過程的早期階段期間可控制每個環繞閘極奈米片材場效電晶體中之奈米片材層的數量、寬度、厚度和間距，且可使用於定制所得的環繞閘極奈米片材場效電晶體的電氣特性和效能。由於選擇性處理，具有鰭狀場效電晶體和環繞閘極奈米片材場效電晶體的混合結構可同時形成於相同基板上。此外，根據一些實施方法，可形成不同的寬度、數量、厚度和電氣特性的環繞閘極奈米片材場效電晶體於相同的基板上，與鰭狀場效電晶體相比，所得的環繞閘極奈米片材場效電晶體可表現出優越的汲極感應能障降低行為。
在一些實施方法中，半導體結構包含鰭片和位於基板上之垂直結構。此外，垂直結構包含具有穿插的第一和第二奈米片材層的第一部分，以及具有所述多個第二奈米片材層的第二部分，其中源自第一部分之第二片材層延伸穿過第二部分。此半導體結構更包含閘極結構，其位於鰭片的一部分之上以及位於第一垂直結構的第二部分之上，其中閘極結構環繞第一垂直結構之第二部分的第二奈米片材層、頂部以及鰭片之側邊部分。
在一些實施方法中，半導體結構包含位於基板上之垂直結構，其中垂直結構包含具有穿插的第一和第二奈 米片材層的第一部份、不具所述多個奈米片材層的第二部分以及具有來自第一部分之不同數量的第二奈米片材層。此半導體結構亦包含位於基板之上的鰭片、環繞垂直結構之第二部分的各第二奈米片材層的頂部、底部和側邊部分的第一閘極結構；以及環繞鰭片之部分的第二閘極結構，其中第二閘極結構係高於第一閘極結構。
在一些實施方法中，一方法包含暴露第一和第二垂直結構於基板之上，其中第一和第二垂直結構係由第一介電隔開。此外，各個第一和第二垂直結構具有不同寬度和頂部分，在第一絕緣層之上，包含具有穿插之第一和第二奈米片材層的多層奈米片材堆疊。此方法亦包含沉積犧牲閘電極結構於第一和第二奈米片材層之頂部分之上以及於第一絕緣層之一部分之上；沉積第二絕緣層於第一和第二奈米片材層以及第一絕緣層之上，使得第二絕緣層環繞犧牲閘電極結構之側壁；蝕刻犧牲閘電極結構以於第一和第二奈米片材層中暴露各個多層奈米片材堆疊；於各個暴露之多層奈米片材堆疊中移除各個第一奈米片材層以形成懸浮的第二奈米片材層；以及形成金屬閘極結構以環繞懸浮的第二奈米片材層。
應理解，實施方式旨在用於解釋申請專利範圍，而不是揭露摘要部分。摘要部分的揭露可闡述發明人所預期之本揭露的一個或多個實施方法，但不是所有可能的實施方法，因此，不旨在以任何方式限制所附加的申請專利範圍。
上文概述若干實施例或示例之特徵，使得熟習此項技術者可更好地理解本揭露之態樣。熟習此項技術者應瞭解，可輕易使用本揭露作為基礎來設計或修改其他製程及結構，以便實施本文所介紹之實施例的相同目的及/或實現相同優點，熟習此項技術者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇。
200‧‧‧基板
505‧‧‧矽鍺奈米片材層
510‧‧‧矽奈米片材層
810‧‧‧垂直結構
905‧‧‧襯墊
910‧‧‧絕緣層
915‧‧‧閘極間隔物(分隔物)
1000‧‧‧磊晶堆疊
1005‧‧‧保護性氮化物層
1010‧‧‧絕緣層
1300‧‧‧金屬閘極結構
1305‧‧‧高k介電層
1310‧‧‧金屬閘電極堆疊
1315‧‧‧線
1320‧‧‧氮化物覆蓋層

Claims (20)

  1. 一半導體結構，包含：一鰭片，位於一基板上；一垂直結構，位於該基板上，其中該垂直結構包含：一第一部分，具有穿插的數個第一和第二奈米片材層；以及一第二部分，具有該等第二奈米片材層，其中源自該第一部分之該等第二片材層延伸穿過該第二部分；以及一閘極結構，位於該鰭片的一部分之上以及位於該第一垂直結構的該第二部分之上，其中該閘極結構環繞該第一垂直結構之該第二部分的該等第二奈米片材層、一頂部以及該鰭片之一側邊部分。
  2. 如請求項1所述之該半導體結構，更包含：一源極/汲極磊晶推疊，位於該垂直結構的該第一部分上且相鄰於該閘極結構；以及另一源極/汲極磊晶推疊，位於該鰭片上且相鄰於該閘極結構。
  3. 如請求項1所述之該半導體結構，其中該垂直結構之一寬度係等於或寬於該鰭片之一寬度。
  4. 如請求項3所述之該半導體結構，其中該垂直結構之該寬度係等同於該第二奈米片材層之一寬度，且範圍從約4奈米至約50奈米。
  5. 如請求項4所述之該半導體結構，更包含：另一垂直結構，位於該基板之上，其中該另一垂直結構包含：一第一部分，具有穿插的數個第一和第二奈米片材層；以及一第二部分，具有另該垂直結構之該第二奈米片材層，其中另該垂直結構之數個第二奈米片材層的一寬度係不同於該垂直結構之該等第二奈米片材層的該寬度。
  6. 如請求項1所述之該半導體結構，其中該等第一奈米片材層之一間距係基於該等第二奈米片材層之一厚度，且其中該等第二奈米片材層之一間距係基於該等第一奈米片材層之一厚度。
  7. 如請求項1所述之該半導體結構，其中該等第一奈米片材層包含矽鍺且該等第二奈米片材層包含矽。
  8. 如請求項1所述之該半導體結構，其中該等第一奈米片材層包含矽且該等第二奈米片材層包含矽鍺。
  9. 如請求項1所述之該半導體結構，其中該等第一和第二奈米片材層包含不同的磊晶生長材料。
  10. 如請求項1所述之該半導體結構，其中該等第一和第二奈米片材層之一頂面係平行於一(100)晶面。
  11. 一半導體結構，包含：一垂直結構，位於一基板上，其中該垂直結構包含：一第一部分，具有穿插的數個第一和第二奈米片材層；以及一第二部分，不具該等第一奈米片材層，且具有源自於該第一部分之一不同數量的該等第二奈米片材層；一鰭片，位於該基板之上；一第一閘極結構，環繞該垂直結構之該第二部分的各該第二奈米片材層的頂部、底部和側邊部分；以及一第二閘極結構，環繞該鰭片之一部分，其中該第二閘極結構係高於該第一閘極結構。
  12. 如請求項11所述之該半導體結構，更包含：一源極/汲極磊晶堆疊，位於該垂直結構之該第一部分上，且相鄰於該第一閘極結構；以及另一源極/汲極磊晶堆疊，位於該鰭片上，且相鄰於該第二閘極結構。
  13. 如請求項11所述之該半導體結構，更包 含：另一垂直結構，位於該基板之上，其中另該垂直結構包含：一第一部分，具有穿插的數個第一和第二奈米片材層；以及一第二部分，不具有該等第一奈米片材層，且具有如該第一部分之一相同數量的數個第二奈米片材層；以及一第三閘極結構，環繞另該垂直結構之該第二部分的各該第二奈米片材層，其中該第三閘極結構係高於該第一閘極結構。
  14. 如請求項13所述之該半導體結構，其中該第二垂直結構之一寬度係等同於或不同於該第一垂直結構的該寬度。
  15. 如請求項14所述之該半導體結構，其中該第一和第二垂直結構之該等寬度限定該等第一和第二奈米片材層的各別寬度。
  16. 如請求項13所述之該半導體結構，其中該垂直結構之該第二部分相較於另該垂直結構之該第二部分，具有較少的第二奈米片材層。
  17. 如請求項11所述之該半導體結構，其中該等第一奈米片材層包含矽，且該等第二奈米片材層包含 矽鍺。
  18. 如請求項11所述之該半導體結構，其中各該第一和第二奈米片材層具有一厚度，其範圍從約5奈米至約20奈米。
  19. 一方法，包含：暴露一第一和一第二垂直結構於一基板之上，其中該等第一和第二垂直結構係由一第一介電隔開，且各該第一和第二垂直結構具有不同寬度和一頂部分，在該第一絕緣層之上，包含具有穿插之數個第一和第二奈米片材層的一多層奈米片材堆疊；沉積一犧牲閘電極結構於該等第一和第二奈米片材層之該頂部分之上以及於該第一絕緣層之一部分之上；沉積一第二絕緣層於該等第一和第二奈米片材層以及該第一絕緣層之上，使得該第二絕緣層環繞該犧牲閘電極結構之一側壁；蝕刻犧牲閘電極結構以於該等第一和第二奈米片材層中暴露各個多層奈米片材堆疊；於各個暴露之多層奈米片材堆疊中移除各該第一奈米片材層以形成數個懸浮的第二奈米片材層；以及形成一金屬閘極結構以環繞該等懸浮的第二奈米片材層。
  20. 如請求項19所述之該方法，更包含： 蝕刻該金屬閘極結構以移除一或多個該第一垂直結構之該等第二奈米片材層；以及沉積一氮化物層於該金屬閘極結構之上。
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