CN106558501A - 元件的金属栅极方案及形成所述金属栅极方案的方法 - Google Patents

元件的金属栅极方案及形成所述金属栅极方案的方法 Download PDF

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CN106558501A
CN106558501A CN201510853179.XA CN201510853179A CN106558501A CN 106558501 A CN106558501 A CN 106558501A CN 201510853179 A CN201510853179 A CN 201510853179A CN 106558501 A CN106558501 A CN 106558501A
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metal
containing compound
substrate
source
work function
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CN106558501B (zh
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吴仲强
李家庆
李达元
曹学文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及元件的金属栅极方案及形成所述金属栅极方案的方法。更具体的，本发明描述栅极结构及形成所述栅极结构的方法。在一些实施例中，一种方法包含在衬底中形成源极区/漏极区，及在所述源极区/漏极区之间形成栅极结构。所述栅极结构包含所述衬底上方的栅极介电层、所述栅极介电层上方的功函数调谐层、所述功函数调谐层上方的含金属化合物以及所述含金属化合物上方的金属，其中所述含金属化合物包括所述金属作为所述化合物的元素。

Description

元件的金属栅极方案及形成所述金属栅极方案的方法
技术领域
本发明关于半导体技术领域，更具体的，涉及元件的金属栅极方案及形成所述金属栅极方案的方法。
背景技术
半导体元件用于多种电子应用中，例如个人计算机、蜂窝电话、数码相机及其它电子装备(作为实例)。半导体元件通常通过在半导体衬底上依序沉积隔离或介电层、导电层及半导电材料层并使用光刻来图案化各种材料层来制造，以在上面形成电路组件及器件。
晶体管为常常形成于半导体元件上的电路组件或器件。视电路设计而定，许多晶体管外加电容器、电感器、电阻器、二极管、导电线或其它器件形成于半导体元件上。场效应晶体管(FET)为一种类型的电晶体。
通常，在习知结构中，电晶体包含形成于源极区与漏极区之间的栅极堆叠。源极区及漏极区可包含衬底的掺杂区，且可显现适合于特定应用的掺杂概况栅极堆叠定位于通道区上方，且可包含衬底中插入于栅极电极与通道区之间的栅极介电质。
发明内容
根据本发明一实施例的方法包括：在衬底中形成第一源极/漏极区及第二源极/漏极区；以及在第一源极/漏极区与第二源极/漏极区之间且在衬底上方形成栅极结构，栅极结构包括：衬底上方的栅极介电层，栅极介电层上方的功函数调谐层，功函数调谐层上方的含金属化合物，以及含金属化合物上方的金属，其中含金属化合物包括金属作为化合物的元素，且其中含金属化合物包括C、N、O或其组合。
根据本发明另一实施例的方法，其中金属为钨；含金属化合物包括WCx、WCxNy或WCxNyOz；该方法进一步包括通过改变含金属化合物中氮的浓度来调谐含金属化合物的功函数；或该方法进一步包括通过改变含金属化合物中氧的浓度来调谐含金属化合物的功函数；其中栅极结构进一步包括栅极介电层与功函数调谐层之间的罩盖层。
根据本发明又一实施例的方法包括：在衬底中形成第一源极/漏极区及第二源极/漏极区；在衬底上方形成层间介电质，开口穿过层间介电质到衬底，开口是在第一源极/漏极区与第二源极/漏极区之间；在开口中且在衬底上方形成栅极介电层；在开口中且在栅极介电层上方形成功函数调谐层；在开口中且在功函数调谐层上方形成含金属化合物；以及在开口中且在含金属化合物上方形成金属，其中含金属化合物包括金属作为含金属化合物的元素，且其中含金属化合物具有大于金属的功函数。
本发明又一实施例还提供一种结构，其包括：衬底中的第一源极/漏极区及第二源极/漏极区；衬底上及第一源极/漏极区与第二源极/漏极区之间的栅极结构，该栅极结构包括：衬底上方的栅极介电层，栅极介电层上方的功函数调谐层，功函数调谐层上方的含金属化合物，以及含金属化合物上方的金属，其中含金属化合物包括金属作为含金属化合物的元素，且其中含金属化合物具有大于金属的功函数；以及衬底上方及栅极结构周围的层间介电质。
附图说明
当结合附图阅读时，从以下实施方式最好地理解本发明的各方面。应注意，根据业界中的标准惯例，各种特征未按比例绘制。事实上，为了论述清楚起见，可任意增加或减小各种特征的尺寸。
图1至8为根据一些实施例的制造场效应晶体管(FET)中的中间阶段的各横截面图。
具体实施方式
以下揭示内容提供用于实施本发明的不同特征的许多不同实施例或实例。下文描述组件及布置的特定实例以简化本发明。当然，这些组件以及布置仅为实例且并不意欲为限制性的。举例来说，在以下描述中第一特征在第二特征上方或上的形成可包含第一特征和第二特征直接接触地形成的实施例，并且还可包含额外特征可在第一特征和第二特征之间形成使得第一特征和第二特征可不直接接触的实施例。另外，本揭示内容可在各种实例中重复参考标号和/或字母。此重复是出于简化和清楚的目的，且本身并不指示所论述的各种实施方案和/或配置之间的关系。
另外，例如“底下”、“以下”、“下部”、“以上”、“上部”及其类似者的空间相关术语本文中为易于描述而使用，以描述如图中所说明的一个器件或特征与另一器件或特征的关系。除图中所描绘的定向以外，空间相关术语意欲包涵元件在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相关描述词可相应地进行解释。
场效应晶体管(FET)及形成所述FET的方法根据各种实施例来提供。说明形成FET的中间阶段。本文中论述的一些实施例在使用后栅极过程(gate-last process)形成的平面FET的情形下论述。一些实施例想到用于例如finFET的其它元件中的各方面。在p型元件的情形下论述一些实施例。一些实施例又适合于n型元件。论述实施例的一些变化。本领域的普通技术人员将易于理解涵盖于其它实施例的范围内的可进行的其它修改。尽管以特定次序论述方法实施例，但各种其它方法实施例可以任何逻辑次序执行，且可包含本文中所描述的较少或更多步骤。
图1至8为根据例示性实施例的制造FET中中间阶段的横截面图。图1说明衬底40。衬底40可为半导体衬底，例如块体半导体衬底、绝缘体上半导体(SOI)衬底、多层化或梯度衬底，或其类似者。衬底40可包含半导体材料，例如，包含Si及Ge的基本半导体；包含SiC、SiGe、GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb及/或GaInAsP的化合物或合金半导体；或其组合。衬底40可经掺杂或不经掺杂。在特定实例中，衬底40为块体硅衬底。
图2说明例如浅渠道隔离(STI)区的隔离区42于衬底40中的形成。在一些实施例中，为了形成隔离区42，渠道通过蚀刻形成于衬底40中。蚀刻可为任一可接受蚀刻过程，例如，反应性离子蚀刻(RIE)、中性束蚀刻(NBE)、类似者，或其组合。蚀刻可为非等向性的。绝缘材料形成于渠道中。绝缘材料可为氧化物，例如氧化硅、氮化物、类似者或其组合；且可通过高密度等离子化学气相沉积(HDP-CVD)、可流动CVD(FCVD)(例如，远程等离子系统中基于CVD的材料沉积，及后固化以使得绝缘材料转化为另一材料例如氧化物)、类似者，或其组合。可使用由任何可接受过程形成的其它绝缘材料。在所说明的实施例中，绝缘材料为通过FCVD过程形成的氧化硅。一旦形成绝缘材料，便可执行退火过程。另外，在图2中，例如化学机械抛光(CMP)的平坦化过程可移除任何过量绝缘材料，且形成为共面的隔离区42的顶表面及衬底40的顶表面。
尽管未具体说明，但适当井可形成于衬底40中。举例来说，n型井可形成于衬底40中，其中将形成p型元件，例如p型FET。举例来说，为了在衬底40中形成n型井，光致抗蚀剂可形成于衬底40上方。光致抗蚀剂可经图案化以暴露衬底40的正形成n型井的区。光致抗蚀剂可通过使用旋涂技术来形成，且可使用可接受光刻技术来图案化。一旦图案化了光致抗蚀剂，则可执行n型杂质布植，且光致抗蚀剂可充当掩模以实质上防止n型杂质在所要布植区外部布植到衬底40中。n型杂质可为布植于衬底40中达等于或小于1018cm-3例如在约1017cm-3与约1018cm-3之间的浓度的磷、砷或类似者。在布植之后，可例如通过可接受灰化过程来移除光致抗蚀剂。在布植之后，退火可经执行以激活布植的杂质。布植可在衬底40中形成n井。
其它实施例有可能。举例来说，在制造n型元件中，p型杂质而非n型杂质使用相同或类似于上文所描述的过程的过程布植到衬底40中。p型杂质可为硼、BF2或类似者，且可经布植达等于或小于1018cm-3例如在约1017cm-3与约1018cm-3之间的浓度。
在图3中，虚设介电层形成于衬底40上。虚设介电层可为(例如)氧化硅、氮化硅、其组合或类似者，且可根据例如CVD、热氧化或类似者的可接受技术而沉积或热生长。虚设栅极层形成于虚设介电层上方。虚设栅极层可例如通过使用CVD或类似者沉积于虚设介电层上方，且接着例如由CMP来平坦化。虚设栅极层可包括(例如)多晶硅，尽管也可使用具有高蚀刻选择性的其它材料。掩模层接着形成于虚设栅极层上方。掩模层可例如通过使用CVD或类似者沉积于虚设栅极层上方。掩模层可包括(例如)氮化硅、氮氧化硅、氮化硅碳或类似者。
掩模层可使用可接受光刻及蚀刻技术来图案化以形成掩模50。掩模50的图案接着可通过可接受蚀刻技术经转印至虚设栅极层及虚设介电层，以分别自虚设栅极层及虚设介电层形成虚设栅极48及虚设栅极介电质46。蚀刻可包括可接受非等向性蚀刻，例如RIE、NBE或类似者。虚设栅极48及虚设栅极介电质46的宽度W可在自约10nm至约300nm的范围内，例如约20nm。虚设栅极48及虚设栅极介电质46具有经组合的高度H。高度H可在自约50nm至约200nm的范围内，例如约100nm。高度H与宽度W的纵横比可在自约1至约10的范围内，例如约5。虚设栅极48覆盖衬底40中的通道区。
可执行经轻度掺杂的源极/漏极(LDD)区的布植。类似于上文所论述的布植，例如光致抗蚀剂的掩模可形成于衬底40上方，且经图案化，且p型杂质可在p型元件的LDD区中布植到所暴露衬底40中。可接着移除掩模。p型杂质可为硼、BF2或类似者。轻度掺杂的源极/漏极区52可具有自约1015cm-3至约1016cm-3的杂质浓度。退火可用于激活经布植杂质。
其它实施例有可能。举例来说，在n型元件的制造中，n型杂质而非p型杂质可使用相同或类似于上述过程的过程在n型元件的LDD区中布植到衬底40中。n型杂质可为先前论述的n型杂质或其类似者中的任一者，且可经布植达等于或小于1018cm-3的浓度，例如在约1017cm-3与约1018cm-3之间的浓度。
栅极间隔物54沿着虚设栅极48及虚设栅极介电质46的侧壁形成。栅极间隔物54可通过例如由CVD或类似者保形地沉积材料且随后非等向性地蚀刻材料来形成。栅极间隔物54的材料可为氮化硅、氮化硅碳、其组合或类似者。
参考图4，外延源极/漏极区56形成于衬底40中。硬掩模层可经形成从而覆盖衬底40。硬掩模层可为氮化硅、氮化硅碳、氮氧化硅、硅碳氮氧化物、类似者，或其通过CVD或类似者沉积的组合。可使用形成硬掩模层的其它材料及方法。硬掩模层可经图案化以暴露衬底40的元件将使用例如RIE、NBE或类似者的任何可接受光刻及蚀刻过程形成的区。一旦已图案化了硬掩模层，便执行对于衬底40为选择性的蚀刻。蚀刻可为例如干式或湿式蚀刻的任何可接受蚀刻，所述蚀刻可为非等向性或各向同性的。蚀刻使源极/漏极区在衬底40中凹陷。外延源极/漏极区56接着在凹陷部中外延地生长。外延生长可为通过使用金属有机化学气相沉积(MOCVD)、分子束外延法(MBE)、液相外延法(LPE)、气相外延法(VPE)、其类似者或其组合。外延源极/漏极区56可包括任一可接受材料，例如对于元件类型(例如，p型)适当的材料。举例来说，p型元件的外延源极/漏极区56可包括SiGe、SiGeB、Ge、GeSn或类似者。接着，硬掩模层可(例如)使用对于硬掩模层的材料为选择性的蚀刻来移除。
其它实施例有可能。举例来说，在制造n型元件中，外延源极/漏极区可包括硅、SiC、SiCP、SiP或类似者，且外延源极/漏极区可使用相同或类似于上文所描述的过程的过程来形成。
外延源极/漏极区56类似于先前所论述的用于形成经轻度掺杂源极/漏极区的过程可掺杂有掺杂剂，继之以退火。源极/漏极区可具有在约1019cm-3与约1021cm-3之间的杂质浓度。针对p型元件的源极/漏极区的p型杂质可为先前论述的p型杂质中的任一者。在n型元件的状况下，n型杂质可为先前论述的n型杂质中的任一者。在其它实施例中，外延源极/漏极区56在生长期间可经现场掺杂。
在图4中，蚀刻停止层(ESL)58保形地形成于外延源极/漏极区56、栅极间隔物54、掩模50及隔离区42上。在一些实施例中，ESL 58可包括使用原子层沉积(ALD)、CVD、类似者或其组合形成的氮化硅、氮化硅碳或类似者。底部层间介电质(ILD0)60沉积于ESL 58上方。ILD0 60可包括二氧磷基硅酸盐玻璃(PSG)、硼-硅酸盐玻璃(BSG)、经硼掺杂的二氧磷基硅酸盐玻璃(BPSG)、未经掺杂的硅酸盐玻璃(USG)或类似者，且可由例如CVD、等离子增强型CVD(PECVD)、FCVD、类似者或其组合的任何合适方法来沉积。
在图5中，例如CMP的平坦化过程经执行以使ILD0 60的顶表面与虚设栅极48的顶表面水平。CMP亦可自虚设栅极48上方移除掩模50及ESL 58。因此，虚设栅极48的顶表面经由ILD0 60暴露。虚设栅极48及虚设栅极介电质46在蚀刻步骤中被移除，使得穿过ILD0 60且由栅极间隔物54定义的开口形成于衬底40中。开口可具有上文关于图3所论述的对应于宽度W及高度H的纵横比，此是由于开口由虚设栅极48及虚设栅极介电质46的移除来定义。开口暴露衬底40中相应活性区中的通道区。通道区安置于一对外延源极/漏极区56之间。蚀刻步骤对于虚设栅极48及虚设栅极介电质46的材料为选择性的，所述蚀刻可为干式或湿式蚀刻。在蚀刻期间，当虚设栅极48经蚀刻时，虚设栅极介电质46可用作蚀刻停止层。虚设栅极介电质46可接着在移除虚设栅极48之后经蚀刻。尽管未具体说明出，但取决于用于ILD0 60及虚设栅极介电质46的材料的类似性，ILD0 60在移除虚设栅极介电质46时可凹陷，且此凹陷可使得ESL 58及/或栅极间隔物54的部分突出于ILD0 60的顶表面上方。
界面介电质62形成于每一开口中且衬底40上。界面介电质62可为(例如)通过热氧化、化学氧化、ALD或类似者形成的氧化物或类似者。界面介电质62的厚度范围可为自约至约例如约栅极介电层64接着保形地形成于ILD0 60的顶表面上且沿着栅极间隔物54的侧壁形成于开口中且界面介电质62上。在一些实施例中，栅极介电层64包括高k介电质材料，且在这些实施例中，栅极介电层64可具有大于约7.0的k值，且可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其组合的金属氧化物或硅酸盐。栅极介电层64的形成方法可包含ALD、CVD、分子束沉积(MBD)、类似者或其组合。栅极介电层64的厚度范围可为自约到约例如约
罩盖层接着保形地形成于栅极介电层64上。在所说明实施例中，罩盖层包括第一子层66及第二子层68。在一些实施例中，罩盖层可为单一层或可包括额外子层。罩盖层可充当阻障层以防止随后沉积的含金属材料扩散到栅极介电层64中。另外，如果第一子层66由与功函数调谐层相同的材料形成，例如如果不同层将形成于不同区中(其可包含使用蚀刻)，则第二子层68如所说明在形成功函数调谐层期间可充当蚀刻停止件。第一子层66可包括通过ALD、CVD或类似者保形地沉积于栅极介电层64上的氮化钛(TiN)或类似者。第二子层68可包括通过ALD、CVD或类似者保形地沉积于第一子层66上的氮化钽(TaN)或类似者。罩盖层的厚度范围可为自约至约例如约在所说明的实施例中，第一子层66的厚度范围可为自约至约例如约且第二子层68的厚度范围可为自约至约例如约
第一功函数调谐层70接着保形地形成于罩盖层上，例如第二子层68上。第一功函数调谐层70可为具有任何可接受厚度的任何可接受材料以在给定待形成的元件的应用情况下调谐例如p型元件的元件的功函数达所要量，且可使用任何可接受沉积过程来沉积。在一些实施例中，第一功函数调谐层70包括通过ALD、CVD或类似者沉积的氮化钛(TiN)或类似者。第一功函数调谐层70的厚度范围可为自约至约例如约
例如含金属化合物78的层的含金属材料层接着保形地形成于阻障层76上。如本文中所使用，含金属材料为含有金属及非金属(例如，N、C、O等)的材料，其中非金属以大于可通过单独金属的沉积自然或附带地发生的浓度存在，如本领域的技术人员将理解。含金属化合物78可为基于钨的化合物。举例来说，含金属化合物78可为WNx、WCx、WCxNy、及/或WCxNyOz，或其组合。其它基于钨的化合物可用于一些实施例中。在一些实施例中，基于钨的含金属化合物层使得元件能够进一步调谐元件的功函数以达成较大阈值电压调谐。举例来说，如本文中所描述的基于钨的含金属化合物层可使得元件能够达成自约0.1V至约0.4V(例如约0.2V)的阈值电压。在一些实施例中，由基于钨的含金属化合物层的增加的功函数调谐允许功函数调谐层70更薄同时仍达成元件的所要阈值电压，其可改良元件的制造。举例来说，更薄的功函数调谐层可有助于减小或消除用后续金属层填充栅极开口的问题，其在开口因为较厚功函数调谐层过窄之处可为困难的。在一些实施例中，基于钨的含金属化合物层可具有较小电阻率且可减小总体栅极电阻率，其在一些应用中可有用。在一些实施例中，基于钨的含金属化合物层可有助于阻断某些元素(例如，铜及/或氟)的扩散。
在一些实施例中，含金属化合物78的功函数可通过改变伴随非金属元素(例如，氮、碳及/或氧)的组合物来调谐。举例来说，当含金属化合物78包括WNx时，层的功函数可通过改变Nx的浓度来调谐。在WNx的状况下，Nx的浓度对于功函数调谐可自约0％变化至约50％，且更具体而言自约15％改变至约30％。其它浓度及其它化合物可用于一些实施例中。
含金属化合物78可使用任何可接受沉积过程来沉积。在一些实施例中，含金属化合物78的层通过物理气相沉积(PVD)、ALD、CVD或类似者来沉积或为通过物理气相沉积(PVD)、ALD、CVD或类似者沉积的类似者。含金属化合物78的层的厚度范围可为自约至约例如约
金属82形成于含金属化合物78上。含金属化合物78的功函数大于金属82的功函数。在一些实施例中，金属82包括钨。金属82可使用任何可接受沉积过程例如PVD、CVD、ALD或类似者来沉积。金属82填充开口的未经填充部分。
在图7中，例如CMP的平坦化过程可经执行以移除含金属化合物78，金属82及层64、66、68及70的过量部分，所述过量部分是在ILD0 60的顶表面上。接着，对于含金属化合物78，金属82及层64、66、68及70为选择性的受控回蚀经执行以使那些材料从ILD0 60的顶表面凹陷，其导致说明于图7中的栅极结构。回蚀可包括可接受非等向性蚀刻，例如RIE、NBE或类似者。
介电质盖86形成于通过回蚀形成的凹陷区中。为了形成介电质盖86，盖介电层可沉积于开口中且ILD0 60的顶表面上。盖介电层可包括使用CVD、PECVD或类似者形成的氮化硅、氮化硅碳或类似者。盖介电层可接着例如由CMP平坦化，以形成与ILD060的顶表面共面的顶表面，借此形成介电质盖。
在图8中，上部ILD(ILD1)88沉积于ILD0 60及介电质盖86上方，且接点90经由ILD1 88、ILD0 60及ESL 58形成至外延源极/漏极区56。ILD1 88由例如PSG、BSG、BPSG、USG或类似者的介电质材料形成，且可由例如CVD及PECVD的任何合适方法来沉积。针对接点90的开口经由ILD1 88、ILD0 60及ESL 58形成。开口可使用可接受光刻及蚀刻技术来形成。例如扩散阻障层、黏附层或类似者及导电材料的衬垫形成于开口中。衬垫可包含钛、氮化钛、钽、氮化钽或类似者。导电材料可为铜、铜合金、银、金、钨、铝、镍或类似者。例如CMP的平坦化过程可经执行以自ILD1 88的顶表面移除过量材料。剩余衬垫及导电材料形成开口中的接点90。退火过程可经执行以分别在外延源极/漏极区56与接点90之间的界面处形成硅化物。
图8说明p型FET元件。元件归因于包含于栅极结构中的含金属化合物78，金属82及层64、66、68及70而具有经调谐阈值电压。
尽管未明确展示，但所属领域的技术人员将易于理解，进一步处理步骤可对图8中的结构执行。举例来说，各种金属间介电质(IMD)及其对应金属化物可形成于ILD1 88上方。
一些实施例可达成多个优点。在一些实施例中，如早先所描述，可为基于钨的含金属化合物78可使得元件进一步调谐功函数以达成比使用仅功函数调谐层70有可能的阈值电压调谐大的阈值电压调谐。举例来说，例如如本文中所描述的基于钨的材料的含金属化合物78可使得元件能够达成自约0.1V至约0.4V例如约0.2V的阈值电压。在一些实施例中，通过基于钨的含金属化合物层提供的增加的功函数调谐允许功函数调谐层70更薄同时仍达成所要求阈值电压，其可改良元件的制造。举例来说，更薄的功函数调谐层可有助于减小或消除用后续金属层填充栅极开口的问题，其在开口因为较厚功函数调谐层过窄之处可为困难的。在一些实施例中，基于钨的含金属化合物层可具有较小电阻率，且可减小总体栅极电阻率，其在一些应用中可有帮助。在一些实施例中，基于钨的含金属化合物层可有助于阻断某些元素(例如，铜及/或氟)的扩散。
根据一些实施例，一种方法包含在衬底中形成第一源极/漏极区及第二源极/漏极区。栅极结构形成于第一源极/漏极区与第二源极/漏极区之间且衬底上方。栅极结构包含所述衬底上方的栅极介电层，所述栅极介电层上方的功函数调谐层，所述功函数调谐层上方的含金属化合物，以及所述含金属化合物上方的金属。含金属化合物包含金属作为化合物的元素。含金属化合物亦包含C、N、O或其组合。
根据一些实施例，一种方法包含在衬底中形成第一源极/漏极区及第二源极/漏极区。层间介电质形成于衬底上方，其中穿过层间介电质到衬底的开口是在第一源极/漏极区与第二源极/漏极区之间。栅极介电层形成于开口中且衬底上方。在所述开口中且在所述栅极介电层上方形成功函数调谐层。在所述开口中且在所述功函数调谐层上方形成含金属化合物。金属形成于开口中且含金属化合物上方。含金属化合物包含金属作为含金属化合物的元素，且含金属化合物具有大于金属的功函数。
根据一些实施例，结构包含衬底中的第一源极/漏极区及第二源极/漏极区，及衬底上且第一源极/漏极区与第二源极/漏极区之间的栅极结构。栅极结构包含所述衬底上方的栅极介电层，所述栅极介电层上方的功函数调谐层，所述功函数调谐层上方的含金属化合物，以及所述含金属化合物上方的金属。含金属化合物包含金属作为含金属化合物的元素，且含金属化合物具有大于金属的功函数。结构包含衬底上方且栅极结构周围的层间介电质。
前文概述若干实施例的特征使得本领域技术人员可以更好地理解本公开内容的各方面。本领域技术人员应理解，其可以易于使用本公开内容作为设计或修改用于实现本文中所引入的实施例的相同目的和/或获得相同优点的其它过程和结构的基础。本领域的普通技术人员应认识到，此类等效构造并不脱离本发明的精神和范围，且其可在不脱离本发明的精神和范围的情况下在本文中进行各种改变、替代和更改。

Claims (10)

1.一种方法，其包括：
在衬底中形成第一源极/漏极区及第二源极/漏极区；以及
在所述第一源极/漏极区与所述第二源极/漏极区之间且在所述衬底上方形成栅极结构，所述栅极结构包括：
所述衬底上方的栅极介电层，
所述栅极介电层上方的功函数调谐层，
所述功函数调谐层上方的含金属化合物，以及
所述含金属化合物上方的金属，其中所述含金属化合物包括所述金属作为所述化合物的元素，且其中所述含金属化合物包括C、N、O或其组合。
2.根据权利要求1所述的方法，其中所述金属为钨。
3.根据权利要求1所述的方法，其中所述含金属化合物包括WCx。
4.根据权利要求1所述的方法，其中所述含金属化合物包括WCxNy。
5.根据权利要求1所述的方法，其中所述含金属化合物包括WCxNyOz。
6.根据权利要求1所述的方法，其进一步包括通过改变所述含金属化合物中氮的浓度来调谐所述含金属化合物的所述功函数。
7.根据权利要求1所述的方法，其进一步包括通过改变所述含金属化合物中氧的浓度来调谐所述含金属化合物的所述功函数。
8.根据权利要求1所述的方法，其中所述栅极结构进一步包括所述栅极介电层与所述功函数调谐层之间的罩盖层。
9.一种方法，其包括：
在衬底中形成第一源极/漏极区及第二源极/漏极区；
在所述衬底上方形成层间介电质，开口穿过所述层间介电质到所述衬底，所述开口是在所述第一源极/漏极区与所述第二源极/漏极区之间；
在所述开口中且在所述衬底上方形成栅极介电层；
在所述开口中且在所述栅极介电层上方形成功函数调谐层；
在所述开口中且在所述功函数调谐层上方形成含金属化合物；以及
在所述开口中且在所述含金属化合物上方形成金属，其中所述含金属化合物包括所述金属作为所述含金属化合物的元素，且其中所述含金属化合物具有大于所述金属的功函数。
10.一种结构，其包括：
衬底中的第一源极/漏极区及第二源极/漏极区；
所述衬底上及所述第一源极/漏极区与所述第二源极/漏极区之间的栅极结构，所述栅极结构包括：
所述衬底上方的栅极介电层，
所述栅极介电层上方的功函数调谐层，
所述功函数调谐层上方的含金属化合物，以及
所述含金属化合物上方的金属，其中所述含金属化合物包括所述金属作为所述含金属化合物的元素，且其中所述含金属化合物具有大于所述金属的功函数；以及
所述衬底上方及所述栅极结构周围的层间介电质。
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