TW201712738A - 元件的金屬柵極結構及其形成方法 - Google Patents
元件的金屬柵極結構及其形成方法 Download PDFInfo
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- TW201712738A TW201712738A TW104137831A TW104137831A TW201712738A TW 201712738 A TW201712738 A TW 201712738A TW 104137831 A TW104137831 A TW 104137831A TW 104137831 A TW104137831 A TW 104137831A TW 201712738 A TW201712738 A TW 201712738A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 127
- 239000002184 metal Substances 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims abstract description 51
- 150000001875 compounds Chemical class 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000010410 layer Substances 0.000 claims description 139
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 150000002736 metal compounds Chemical class 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 23
- 239000012535 impurity Substances 0.000 description 20
- 238000005530 etching Methods 0.000 description 16
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- -1 GaInP Chemical compound 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- BEJRNLMOMBGWFU-UHFFFAOYSA-N bismuth boron Chemical compound [B].[Bi] BEJRNLMOMBGWFU-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical class OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- DQUIAMCJEJUUJC-UHFFFAOYSA-N dibismuth;dioxido(oxo)silane Chemical compound [Bi+3].[Bi+3].[O-][Si]([O-])=O.[O-][Si]([O-])=O.[O-][Si]([O-])=O DQUIAMCJEJUUJC-UHFFFAOYSA-N 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
本發明描述柵極結構及形成所述柵極結構的方法。在一些實施例中,一種方法包含在基板中形成源極區/汲極區,及在所述源極區/汲極區之間形成柵極結構。所述柵極結構包含所述基板上方的柵極介電層、所述柵極介電層上方的功函數調整層、所述功函數調整層上方的含金屬化合物以及所述含金屬化合物上方的金屬,其中所述含金屬化合物包括所述金屬作為所述化合物的元素。
Description
本發明關於半導體技術領域,更具體的,涉及元件的金屬柵極方案及形成所述金屬柵極方案的方法。
半導體元件用於多種電子應用中,例如個人電腦、蜂窩電話、數碼相機及其它電子裝備(作為實例)。半導體元件通常藉由在半導體基板上依序沉積隔離或介電層、導電層及半導電材料層並使用微影來圖案化各種材料層來製造,以在上面形成電路部件及組件。
電晶體為常常形成於半導體元件上的電路部件或組件。視電路設計而定,許多電晶體外加電容器、電感器、電阻器、二極體、導電線或其它器件形成於半導體元件上。場效應電晶體(FET)為一種電晶體的類型。
通常,在習知結構中,電晶體包含形成於源極區與汲極區之間的柵極堆疊。源極區及汲極區可包含基板的摻雜區,且可呈現適合於特定應用的摻雜輪廓。柵極堆疊位於通道區上方,且可包含基板中插入於柵極電極與通道區之間的柵極介電質。
根據本發明一實施例的方法包括:在基板中形成第一源極/汲極區及第二源極/汲極區;以及在第一源極/汲極區與第二源極/汲極區之
間且在基板上方形成柵極結構,柵極結構包括:基板上方的柵極介電層,柵極介電層上方的功函數調整層,功函數調整層上方的含金屬化合物,以及含金屬化合物上方的金屬,其中含金屬化合物包括金屬作為化合物的元素,且其中含金屬化合物包括C、N、O或其組合。
根據本發明另一實施例的方法,其中金屬為鎢;含金屬化合物包括WCx、WCxNy或WCxNyOz;該方法進一步包括藉由改變含金屬化合物中氮的濃度來調整含金屬化合物的功函數;或該方法進一步包括藉由改變含金屬化合物中氧的濃度來調整含金屬化合物的功函數;其中柵極結構進一步包括柵極介電層與功函數調整層之間的罩蓋層。
根據本發明又一實施例的方法包括:在基板中形成第一源極/汲極區及第二源極/汲極區;在基板上方形成層間介電質,開口穿過層間介電質到基板,開口是在第一源極/汲極區與第二源極/汲極區之間;在開口中且在基板上方形成柵極介電層;在開口中且在柵極介電層上方形成功函數調整層;在開口中且在功函數調整層上方形成含金屬化合物;以及在開口中且在含金屬化合物上方形成金屬,其中含金屬化合物包括金屬作為含金屬化合物的元素,且其中含金屬化合物具有大於金屬的功函數。
本發明又一實施例還提供一種結構,其包括:基板中的第一源極/汲極區及第二源極/汲極區;基板上及第一源極/汲極區與第二源極/汲極區之間的柵極結構,該柵極結構包括:基板上方的柵極介電層,柵極介電層上方的功函數調整層,功函數調整層上方的含金屬化合物,以及含金屬化合物上方的金屬,其中含金屬化合物包括金屬作為含金屬化合物的元素,且其中含金屬化合物具有大於金屬的功函數;以及基板上方及柵極結構周圍的層間介電質。
40‧‧‧基板
42‧‧‧隔離區
46‧‧‧虛設柵極介電質
48‧‧‧虛設柵極
50‧‧‧遮罩
52‧‧‧輕度摻雜源極/汲極區
54‧‧‧柵極間隔物
56‧‧‧磊晶源極/汲極區
58‧‧‧蝕刻停止層(ESL)
60‧‧‧底部層間介電質
62‧‧‧介面介電質
64‧‧‧柵極介電層
66‧‧‧第一子層
68‧‧‧第二子層
70‧‧‧第一功函數調整層
78‧‧‧含金屬化合物
82‧‧‧金屬
86‧‧‧介電質罩蓋
88‧‧‧上部層間介電質
90‧‧‧接點
H‧‧‧高度
W‧‧‧寬度
由以下詳細說明與附隨圖式得以最佳瞭解本揭露之各方面。注意,根據產業之標準實施方式,各種特徵並非依比例繪示。實際上,
為了清楚討論,可任意增大或縮小各種特徵的尺寸。
圖1至8為根據一些實施例製造場效應電晶體(FET)的各個中間階段的橫截面圖。
以下揭示內容提供許多不同的實施例或範例,用於實施本揭露之不同特徵。器件與配置的特定範例之描述如下,以簡化本揭露之揭示內容。當然,這些僅為範例,並非用於限制。例如,以下描述在第二特徵上或上方形成第一特徵,可包含第一與第二特徵直接接觸的之實施例,亦可包含在該第一與第二特徵之間形成其他特徵的實施例,因而該第一與第二特徵並非直接接觸。此外,本揭露可在不同範例中重複器件符號與/或字母。此重複係為了簡化與清楚之目的,而非描述不同實施例與/或所討論架構之間的關係。
再者,本揭露可使用空間相對用語,例如「之下」、「低於」、「較低」、「高於」、「較高」等類似用語之簡單說明,以描述圖式中一器件或特徵與另一器件或特徵的關係。空間相對用語係用以包括除了裝置在圖式中描述的位向之外,還有在使用中或步驟中之不同位向。該裝置或可被重新定位(旋轉90度或是其他位向),並且可相應解釋本揭露案使用的空間對應描述。
場效應電晶體(FET)及形成所述FET的方法係根據各種實施例來提供。說明形成FET的中間階段。本文中論述的一些實施例在使用後柵極過程(gate-last process)形成的平面FET的情形下論述。一些實施例想到用於例如finFET的其它元件中的各方面。在p型元件的情形下論述一些實施例。一些實施例又適合於n型元件。論述實施例的一些變化。本領域的普通技術人員將易於理解涵蓋於其它實施例的範圍內的可進行的其它修改。儘管以特定次序論述方法實施例,但各種其它方法實施例可以任何邏輯次序執行,且可包含本文中所描述的較少或更多步驟。
圖1至8為根據例示性實施例製造FET中中間階段的橫截面圖。圖1說明基板40。基板40可為半導體基板,例如塊體半導體基板、絕緣體上半導體(SOI)基板、多層化或梯度基板,或其類似者。基板40可包含半導體材料,例如,包含Si及Ge的元素半導體;包含SiC、SiGe、GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb及/或GaInAsP的化合物或合金半導體;或其組合。基板40可經摻雜或不經摻雜。在特定實例中,基板40為塊體矽基板。
圖2說明例如淺溝槽隔離(STI)區的隔離區42於基板40中的形成。在一些實施例中,為了形成隔離區42,溝槽藉由蝕刻形成於基板40中。蝕刻可為任一可接受蝕刻過程,例如,反應性離子蝕刻(RIE)、中性束蝕刻(NBE)、類似者,或其組合。蝕刻可為非等向性的。絕緣材料形成於溝槽中。絕緣材料可為氧化物,例如氧化矽、氮化物、類似者或其組合;且可藉由高密度等離子化學氣相沉積(HDP-CVD)、可流動CVD(FCVD)(例如,遠端等離子系統中基於CVD的材料沉積,及後固化以使得絕緣材料轉化為另一材料例如氧化物)、類似者,或其組合。可使用由任何可接受過程形成的其它絕緣材料。在所說明的實施例中,絕緣材料為藉由FCVD過程形成的氧化矽。一旦形成絕緣材料,便可執行退火過程。另外,在圖2中,例如化學機械拋光(CMP)的平坦化過程可移除任何多餘絕緣材料,且形成為共面的隔離區42的頂面及基板40的頂面。
儘管未具體說明,但適當井可形成於基板40中。舉例來說,n型井可形成於基板40中,其中將形成p型元件,例如p型FET。舉例來說,為了在基板40中形成n型井,光阻可形成於基板40上方。光阻可經圖案化以暴露基板40的區域在該處形成n型井。光阻可藉由使用旋塗技術來形成,且可使用可接受的微影技術來圖案化。一旦圖案化了光阻,則可執行n型雜質佈植,且光阻可充當遮罩以實質上防止n型雜質在所要佈植區外部佈植到基板40中。n型雜質可為佈植於基板40中達等於或小於1018cm-3,例如在
約1017cm-3與約1018cm-3之間的濃度的磷、砷或類似者。在佈植之後,例如可藉由合適的灰化過程來移除光阻。在佈植之後,退火可經執行以活化佈植的雜質。佈植可在基板40中形成n井。
其它實施方式亦有可能。舉例來說,在製造n型元件中,p型雜質而非n型雜質使用相同或類似於上文所描述的過程佈植到基板40中。p型雜質可為硼、BF2或類似者,且可經佈植達等於或小於1018cm-3例如在約1017cm-3與約1018cm-3之間的濃度。
在圖3中,虛設介電層形成於基板40上。虛設介電層可為(例如)氧化矽、氮化矽、其組合或類似者,且可根據例如CVD、熱氧化或類似者的可接受技術而沉積或熱生長。虛設柵極層形成於虛設介電層上方。虛設柵極層可例如藉由使用CVD或類似者沉積於虛設介電層上方,且接著例如由CMP來平坦化。虛設柵極層可包括(例如)多晶矽,儘管也可使用具有高蝕刻選擇性的其它材料。遮罩層接著形成於虛設柵極層上方。遮罩層可例如藉由使用CVD或類似者沉積於虛設柵極層上方。遮罩層可包括(例如)氮化矽、氮氧化矽、氮化矽碳或類似者。
遮罩層可使用可接受微影及蝕刻技術來圖案化以形成遮罩50。遮罩50的圖案接著可藉由可接受蝕刻技術經轉印至虛設柵極層及虛設介電層,以分別自虛設柵極層及虛設介電層形成虛設柵極48及虛設柵極介電質46。蝕刻可包括可接受非等向性蝕刻,例如RIE、NBE或類似者。虛設柵極48及虛設柵極介電質46的寬度W可在自約10nm至約300nm的範圍內,例如約20nm。虛設柵極48及虛設柵極介電質46具有總合的高度H。高度H可在自約50nm至約200nm的範圍內,例如約100nm。高度H與寬度W的高寬比可在自約1至約10的範圍內,例如約5。虛設柵極48覆蓋基板40中的通道區。
可執行輕度摻雜源極/汲極(LDD)區的佈植。類似於上文所論述的佈植,例如光阻的遮罩可形成於基板40上方,且經圖案化,且p型雜質可在p型元件的LDD區中佈植到所暴露基板40中。可接著移除遮罩。p型
雜質可為硼、BF2或類似者。輕度摻雜源極/汲極區52可具有自約1015cm-3至約1016cm-3的雜質濃度。退火可用於啟動經佈植雜質。
其它實施方式亦有可能。舉例來說,在n型元件的製造中,n型雜質而非p型雜質可使用相同或類似於上述過程的過程在n型元件的LDD區中佈植到基板40中。n型雜質可為先前論述的n型雜質或其類似者中的任一者,且可經佈植達等於或小於1018cm-3的濃度,例如在約1017cm-3與約1018cm-3之間的濃度。
柵極間隔物54沿著虛設柵極48及虛設柵極介電質46的側壁形成。柵極間隔物54可藉由例如由CVD或類似者保形地沉積材料且隨後非等向性地蝕刻材料來形成。柵極間隔物54的材料可為氮化矽、氮化矽碳、其組合或類似者。
參考圖4,磊晶源極/汲極區56形成於基板40中。硬遮罩層可經形成從而覆蓋基板40。硬遮罩層可為氮化矽、氮化矽碳、氮氧化矽、矽碳氮氧化物、類似者,或其藉由CVD或類似者沉積的組合。可使用形成硬遮罩層的其它材料及方法。硬遮罩層可經圖案化以暴露基板40的元件將使用例如RIE、NBE或類似者的任何可接受微影及蝕刻過程形成的區。一旦已圖案化了硬遮罩層,便執行針對基板40的選擇性蝕刻。蝕刻方式可為例如乾式或濕式蝕刻的任何可接受蝕刻方式,所述蝕刻可為非等向性或等向性的。蝕刻使源極/汲極區在基板40中凹陷。磊晶源極/汲極區56接著在凹陷部中磊晶生長。磊晶生長可使用金屬有機化學氣相沉積(MOCVD)、分子束磊晶法(MBE)、液相磊晶法(LPE)、氣相磊晶法(VPE)、其類似者或其組合。磊晶源極/汲極區56可包括任一可接受材料,例如對於元件類型(例如,p型)適當的材料。舉例來說,p型元件的磊晶源極/汲極區56可包括SiGe、SiGeB、Ge、GeSn或類似者。接著,硬遮罩層可(例如)使用對於硬遮罩層材料有選擇性的蝕刻方式來移除。
其它實施方式亦有可能。舉例來說,在製造n型元件中,
磊晶源極/汲極區可包括矽、SiC、SiCP、SiP或類似者,且磊晶源極/汲極區可使用相同或類似於上文所描述的過程的過程來形成。
磊晶源極/汲極區56可摻入摻雜劑,其類似於先前所論述用於形成輕度摻雜源極/汲極區的過程,繼之以退火。源極/汲極區可具有在約1019cm-3與約1021cm-3之間的雜質濃度。針對p型元件的源極/汲極區的p型雜質可為先前論述的p型雜質中的任一者。在n型元件的狀況下,n型雜質可為先前論述的n型雜質中的任一者。在其它實施例中,磊晶源極/汲極區56在生長期間可進行原位(in-situ)摻雜。
在圖4中,蝕刻停止層(ESL)58保形地形成於磊晶源極/汲極區56、柵極間隔物54、遮罩50及隔離區42上。在一些實施例中,ESL 58可包括使用原子層沉積(ALD)、CVD、類似者或其組合形成的氮化矽、氮化矽碳或類似者。底部層間介電質(ILD0)60沉積於ESL 58上方。ILD0 60可包括二氧磷基矽酸鹽玻璃(PSG)、硼-矽酸鹽玻璃(BSG)、經硼摻雜的二氧磷基矽酸鹽玻璃(BPSG)、未經摻雜的矽酸鹽玻璃(USG)或類似者,且可由例如CVD、等離子增強型CVD(PECVD)、FCVD、類似者或其組合的任何合適方法來沉積。
在圖5中,例如CMP的平坦化過程經執行以使ILD0 60的頂面與虛設柵極48的頂面水準。CMP亦可自虛設柵極48上方移除遮罩50及ESL 58。因此,虛設柵極48的頂面經由ILD0 60暴露。虛設柵極48及虛設柵極介電質46在蝕刻步驟中被移除,使得穿過ILD0 60且由柵極間隔物54定義的開口形成於基板40中。開口可具有上文關於圖3所論述的對應於寬度W及高度H的高寬比,此是由於對開口的移除係由虛設柵極48及虛設柵極介電質46來定義。該開口暴露基板40中與主動區相對應的通道區。通道區置於一對磊晶源極/汲極區56之間。蝕刻步驟對於虛設柵極48及虛設柵極介電質46的材料為選擇性的,所述蝕刻可為乾式或濕式蝕刻。在蝕刻期間,當虛設柵極48經蝕刻時,虛設柵極介電質46可用作蝕刻停止層。虛設柵極介電質46可接著在
移除虛設柵極48之後蝕刻。儘管未具體說明出,但取決於用於ILD0 60及虛設柵極介電質46的材料的類似性,ILD0 60在移除虛設柵極介電質46時可能會凹陷,且此凹陷可使得ESL 58及/或柵極間隔物54的部分突出於ILD0 60的頂面上方。
介面介電質62形成於每一開口中以及基板40上。介面介電質62可為(例如)藉由熱氧化、化學氧化、ALD或類似者形成的氧化物或類似者。介面介電質62的厚度範圍可為自約5Å至約15Å,例如約8Å。柵極介電層64接著保形地形成於ILD0 60的頂面上且沿著柵極間隔物54的側壁形成於開口中以及介面介電質62上。在一些實施例中,柵極介電層64包括高k介電質材料,且在這些實施例中,柵極介電層64可具有大於約7.0的k值,且可包含Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其組合的金屬氧化物或矽酸鹽。柵極介電層64的形成方法可包含ALD、CVD、分子束沉積(MBD)、類似者或其組合。柵極介電層64的厚度範圍可為自約5Å到約25Å,例如約10Å。
罩蓋層接著保形地形成於柵極介電層64上。在所說明實施例中,罩蓋層包括第一子層66及第二子層68。在一些實施例中,罩蓋層可為單一層或可包括額外子層。罩蓋層可充當阻障層以防止隨後沉積的含金屬材料擴散到柵極介電層64中。另外,如果第一子層66由與功函數調整層相同的材料形成,例如,如果將不同層形成於不同區中(其可包含使用蝕刻),則第二子層68如所說明在形成功函數調整層期間可充當蝕刻停止件。第一子層66可包括藉由ALD、CVD或類似者保形地沉積於柵極介電層64上的氮化鈦(TiN)或類似者。第二子層68可包括藉由ALD、CVD或類似者保形地沉積於第一子層66上的氮化鉭(TaN)或類似者。罩蓋層的厚度範圍可為自約5Å至約20Å,例如約10Å。在所說明的實施例中,第一子層66的厚度範圍可為自約5Å至約20Å,例如約10Å,且第二子層68的厚度範圍可為自約5Å至約20Å,例如約10Å。
第一功函數調整層70接著保形地形成於罩蓋層上,例如第
二子層68上。第一功函數調整層70可為具有任何可接受厚度的任何可接受材料,以配合待形成元件(例如p型元件)的應用而調整元件的功函數至理想的量值,且可使用任何可接受沉積過程來沉積。在一些實施例中,第一功函數調整層70包括藉由ALD、CVD或類似者沉積的氮化鈦(TiN)或類似者。第一功函數調整層70的厚度範圍可為自約15Å至約50Å,例如約25Å。
例如含金屬化合物78的層的含金屬材料層接著保形地形成於阻障層76上。如本文中所使用,含金屬材料為含有金屬及非金屬(例如,N、C、O等)材料,其中如本領域的技術人員所理解的,該非金屬以比單獨沉積該金屬時自然或附帶地產生者更大的濃度存在。含金屬化合物78可為基於鎢的化合物。舉例來說,含金屬化合物78可為WNx、WCx、WCxNy、及/或WCxNyOz,或其組合。其它基於鎢的化合物可用於一些實施例中。在一些實施例中,基於鎢的含金屬化合物層使得元件能夠進一步調整元件的功函數以達到較大閾值電壓的調整。舉例來說,如本文中所描述基於鎢的含金屬化合物層可使得元件能夠達成自約0.1V至約0.4V(例如約0.2V)的閾值電壓。在一些實施例中,由基於鎢的含金屬化合物層的增加的功函數調整允許功函數調整層70更薄,同時仍達成元件的所要閾值電壓,其可改良元件的製造。舉例來說,更薄的功函數調整層可有助於減少或消除利用後續金屬層填充柵極開口的問題,這若在功函數調整層較厚時導致開口過窄,會有困難。在一些實施例中,基於鎢的含金屬化合物層可具有較小電阻率且可減少總體柵極電阻率,其在一些應用中會有幫助。在一些實施例中,基於鎢的含金屬化合物層可有助於阻斷某些元素(例如,銅及/或氟)的擴散。
在一些實施例中,含金屬化合物78的功函數可藉由改變伴隨的非金屬元素(例如,氮、碳及/或氧)的組合物來調整。舉例來說,當含金屬化合物78包括WNx時,層的功函數可藉由改變Nx的濃度來調整。在WNx的狀況下,Nx的濃度對於功函數調整可自約0%變化至約50%,且更具體而言自約15%改變至約30%。其它濃度及其它化合物可用於一些實施例中。
含金屬化合物78可使用任何可接受的沉積過程來沉積。在一些實施例中,含金屬化合物78的層藉由物理氣相沉積(PVD)、ALD、CVD或類似者來沉積或為藉由物理氣相沉積(PVD)、ALD、CVD或類似者沉積的類似者。含金屬化合物78的層的厚度範圍可為自約10Å至約50Å,例如約25Å。
金屬82形成於含金屬化合物78上。含金屬化合物78的功函數大於金屬82的功函數。在一些實施例中,金屬82包括鎢。金屬82可使用任何可接受的沉積過程例如PVD、CVD、ALD或類似者來沉積。金屬82填充開口的未經填充部分。
在圖7中,例如CMP的平坦化過程可經執行以移除含金屬化合物78,金屬82及層64、66、68及70的多餘部分,所述多餘部分位於ILD0 60的頂面上。接著,執行對於含金屬化合物78,金屬82及層64、66、68及70具有選擇性的受控回蝕,以使那些材料從ILD0 60的頂面凹陷,其產生圖7所說明的柵極結構。回蝕可包括可接受非等向性蝕刻,例如RIE、NBE或類似者。
介電質罩蓋86形成於藉由回蝕形成的凹陷區中。為了形成介電質罩蓋86,罩蓋介電層可沉積於開口中且ILD0 60的頂面上。罩蓋介電層可包括使用CVD、PECVD或類似者形成的氮化矽、氮化矽碳或類似者。罩蓋介電層可接著例如由CMP平坦化,以形成與ILD0 60的頂面共面的頂面,借此形成介電質罩蓋。
在圖8中,上部ILD(ILD1)88沉積於ILD0 60及介電質罩蓋86上方,且接點90經由ILD1 88、ILD0 60及ESL 58形成至磊晶源極/汲極區56。ILD1 88由例如PSG、BSG、BPSG、USG或類似者的介電質材料形成,且可由例如CVD及PECVD的任何合適方法來沉積。針對接點90的開口經由ILD1 88、ILD0 60及ESL 58形成。該開口可使用可接受的微影及蝕刻技術來形成。例如擴散阻障層、黏附層或類似者及導電材料的襯層形成於開口中。
襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似者。導電材料可為銅、銅合金、銀、金、鎢、鋁、鎳或類似者。例如CMP的平坦化過程可經執行以自ILD1 88的頂面移除過量材料。剩餘襯層及導電材料形成開口中的接點90。退火過程可經執行以分別在磊晶源極/汲極區56與接點90之間的介面處形成矽化物。
圖8說明p型FET元件。該元件因包含於柵極結構中的含金屬化合物78,金屬82及層64、66、68及70而具有調整過的閾值電壓。
儘管未明確展示,但所屬領域的技術人員將易於理解,可對圖8中的結構執行進一步處理步驟。舉例來說,各種金屬間介電質(IMD)及其對應金屬化物可形成於ILD1 88上方。
一些實施例可達成多個優點。在一些實施例中,如之前所描述,基於鎢的含金屬化合物78可使得元件進一步調整功函數,可達到比僅使用功函數調整層70可能的閾值電壓調整更大的閾值電壓調整。舉例來說,例如如本文中所描述的基於鎢的材料的含金屬化合物78可使得元件能達到約0.1V至約0.4V(例如約0.2V)的閾值電壓。在一些實施例中,藉由基於鎢的含金屬化合物層所提供更多的功函數調整,可允許功函數調整層70更薄,同時仍達到所要求的閾值電壓,其可改良元件的製造。舉例來說,更薄的功函數調整層可有助於減少或消除利用後續金屬層以填充柵極開口的問題,其填充過程在功函數調整層較厚而導致開口過窄的狀況會產生困難。在一些實施例中,基於鎢的含金屬化合物層可具有較小電阻率,且可減小總體柵極電阻率,其在一些應用中有幫助。在一些實施例中,基於鎢的含金屬化合物層可有助於阻斷某些元素(例如,銅及/或氟)的擴散。
根據一些實施例,一種方法包含在基板中形成第一源極/汲極區及第二源極/汲極區。柵極結構形成於第一源極/汲極區與第二源極/汲極區之間且基板上方。柵極結構包含所述基板上方的柵極介電層,所述柵極介電層上方的功函數調整層,所述功函數調整層上方的含金屬化合物,以及
所述含金屬化合物上方的金屬。含金屬化合物包含金屬作為化合物的元素。含金屬化合物亦包含C、N、O或其組合。
根據一些實施例,一種方法包含在基板中形成第一源極/汲極區及第二源極/汲極區。層間介電質形成於基板上方,其中穿過層間介電質到基板的開口是在第一源極/汲極區與第二源極/汲極區之間。柵極介電層形成於開口中以及基板上方。在所述開口中且在所述柵極介電層上方形成功函數調整層。在所述開口中且在所述功函數調整層上方形成含金屬化合物。金屬形成於開口中以及含金屬化合物上方。含金屬化合物包含金屬作為含金屬化合物的元素,且含金屬化合物具有大於金屬的功函數。
根據一些實施例,結構包含基板中的第一源極/汲極區及第二源極/汲極區,以及位於基板上且第一源極/汲極區與第二源極/汲極區之間的柵極結構。柵極結構包含所述基板上方的柵極介電層,所述柵極介電層上方的功函數調整層,所述功函數調整層上方的含金屬化合物,以及所述含金屬化合物上方的金屬。含金屬化合物包含金屬作為含金屬化合物的元素,且含金屬化合物具有大於金屬的功函數。該結構包含基板上方且柵極結構周圍的層間介電質。
前述內容概述一些實施方式的特徵,因而熟知此技藝之人士可更加理解本申請案揭示內容之各方面。熟知此技藝之人士應理解可輕易使用本申請案揭示內容作為基礎,用於設計或修飾其他製程與結構而實現與本申請案該之實施方式具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本申請案揭示內容的精神與範圍,以及熟知此技藝之人士可進行各種變化、取代與替換,而不脫離本申請案揭示內容之精神與範圍。
42‧‧‧隔離區
52‧‧‧輕度摻雜源極/汲極區
56‧‧‧磊晶源極/汲極區
58‧‧‧蝕刻停止層(ESL)
60‧‧‧底部層間介電質
86‧‧‧介電質罩蓋
88‧‧‧上部層間介電質
90‧‧‧接點
Claims (10)
- 一種方法,其包括:在基板中形成第一源極/汲極區及第二源極/汲極區;以及在該第一源極/汲極區與該第二源極/汲極區之間且在該基板上方形成柵極結構,該柵極結構包括:該基板上方的柵極介電層,該柵極介電層上方的功函數調整層,該功函數調整層上方的含金屬化合物,以及該含金屬化合物上方的金屬,其中該含金屬化合物包括該金屬作為該化合物的元素,且其中該含金屬化合物包括C、N、O或其組合。
- 根據請求項1所述的方法,其中該金屬為鎢。
- 根據請求項2所述的方法,其中該含金屬化合物包括WNx。
- 根據請求項3所述的方法,其中該含金屬化合物的N濃度是在0%與50%之間。
- 根據請求項1所述的方法,其中該含金屬化合物包括WCx。
- 根據請求項1所述的方法,其中該含金屬化合物包括WCxNy。
- 根據請求項1所述的方法,其中該含金屬化合物包括WCxNyOz。
- 根據請求項1所述的方法,其進一步包括藉由改變該含金屬化合物中氮或氧的濃度來調整該含金屬化合物的該功函數。
- 一種方法,其包括:在基板中形成第一源極/汲極區及第二源極/汲極區;在該基板上方形成層間介電質,開口穿過該層間介電質到該基板,該開口是在該第一源極/汲極區與該第二源極/汲極區之間;在該開口中且在該基板上方形成柵極介電層;在該開口中且在該柵極介電層上方形成功函數調整層; 在該開口中且在該功函數調整層上方形成含金屬化合物;以及在該開口中且在該含金屬化合物上方形成金屬,其中該含金屬化合物包括該金屬作為該含金屬化合物的元素,且其中該含金屬化合物具有大於該金屬的功函數。
- 一種結構,其包括:基板中的第一源極/汲極區及第二源極/汲極區;該基板上及該第一源極/汲極區與該第二源極/汲極區之間的柵極結構,該柵極結構包括:該基板上方的柵極介電層,該柵極介電層上方的功函數調整層,該功函數調整層上方的含金屬化合物,以及該含金屬化合物上方的金屬,其中該含金屬化合物包括該金屬作為該含金屬化合物的元素,且其中該含金屬化合物具有大於該金屬的功函數;以及該基板上方及該柵極結構周圍的層間介電質。
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US9871114B2 (en) * | 2015-09-30 | 2018-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate scheme for device and methods of forming |
CN108807378A (zh) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应管及其形成方法 |
US10490649B2 (en) * | 2017-05-30 | 2019-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device with adhesion layer |
KR102341721B1 (ko) * | 2017-09-08 | 2021-12-23 | 삼성전자주식회사 | 반도체 소자 |
CN108493246A (zh) * | 2018-02-09 | 2018-09-04 | 中国科学院微电子研究所 | 半导体器件与其制作方法 |
US11289578B2 (en) | 2019-04-30 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective etching to increase threshold voltage spread |
US11694958B2 (en) | 2020-06-03 | 2023-07-04 | International Business Machines Corporation | Layout design for threshold voltage tuning |
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- 2015-09-30 US US14/871,580 patent/US9871114B2/en active Active
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-
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Also Published As
Publication number | Publication date |
---|---|
US20170092740A1 (en) | 2017-03-30 |
TWI594304B (zh) | 2017-08-01 |
US10283619B2 (en) | 2019-05-07 |
CN106558501B (zh) | 2020-03-13 |
CN106558501A (zh) | 2017-04-05 |
US20180145151A1 (en) | 2018-05-24 |
US20190259853A1 (en) | 2019-08-22 |
US11127836B2 (en) | 2021-09-21 |
US9871114B2 (en) | 2018-01-16 |
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