CN203760482U - 在硅衬底上的全隔离FinFET晶体管及电隔离晶体管 - Google Patents

在硅衬底上的全隔离FinFET晶体管及电隔离晶体管 Download PDF

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CN203760482U
CN203760482U CN201320643522.4U CN201320643522U CN203760482U CN 203760482 U CN203760482 U CN 203760482U CN 201320643522 U CN201320643522 U CN 201320643522U CN 203760482 U CN203760482 U CN 203760482U
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fin
substrate
silicon substrate
raceway groove
conduction fin
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N·劳贝特
P·卡雷
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STMicroelectronics lnc USA
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Abstract

本实用新型的实施例提供一种在硅衬底上的全隔离FinFET晶体管及电隔离晶体管。通过在半传导沟道(鳍)与衬底之间插入绝缘层来防止FinFET器件中的沟道到衬底泄漏。类似地，通过在源极/漏极区域与衬底之间插入绝缘层隔离源极/漏极区域与衬底来防止FinFET器件中的源极/漏极到衬底泄漏。绝缘层物理和电隔离传导路径与衬底，因此防止电流泄漏。如果半传导鳍阵列由多层堆叠组成，则可以去除底部材料，因此产生在硅表面上方悬置的鳍阵列。然后可以向在剩余顶部鳍材料下面的所得间隙填充氧化物以更好地支撑鳍并且隔离鳍阵列与衬底。所得FinFET器件在栅极区域和源极/漏极区域二者中为全衬底隔离。

Description

在硅衬底上的全隔离FinFET晶体管及电隔离晶体管
技术领域
本公开内容涉及集成电路晶体管的制作，并且具体涉及低泄漏三维FinFET(场效应晶体管)器件的制作。
背景技术
在数字电路中，晶体管是开关，该开关理想地：a)在它关断时传递零电流；b)在它导通时供应大电流流动；并且c)在导通与关断状态之间瞬时地切换。遗憾的是，在构造于集成电路中时晶体管并非是理想的并且往往即使在它关断时仍然泄漏电流。经过器件或者从器件泄漏的电流往往耗尽向器件供应功率的电池。多年来，通过缩减临界尺度以增加切换速度来改进集成电路晶体管性能。然而随着基于硅的晶体管的尺度继续缩减，维持包括关断状态泄漏的各种电特性的控制变得越来越有挑战性，而从缩减器件尺度获得的性能益处已经变得不太显著。因此一般有利的是通过包括改变材料和器件几何形状的备选手段减少晶体管中的漏电流。
集成电路通常并入FET，在这些FET中，电流响应于向栅极施加的电压流过在源极与漏极之间的半传导沟道。在图1A中示出并且以下更具体描述传统平面(2D)晶体管结构。为了提供对电流流动的更佳控制，已经开发有时称为3D晶体管的FinFET晶体管，诸如图1B中所示FinFET晶体管。FinFET是电子切换器件，在该电子切换器件中，传统FET的平面半传导沟道被替换为与衬底表面垂直向外延伸的半传导鳍(fin)。在这样的器件中，控制鳍中的电流流动的栅极在鳍的三侧周围卷包(wrap)以便从三个表面而不是一个表面影响电流流动。用FinFET设计实现的改进的控制产生更快的切换性能和减少的电流泄漏。
英特尔在2011年5月4日的通报中描述了这一类型的晶体管，将它冠以包括3D晶体管、3D三栅极晶体管或者FinFET的各种称谓。(例如参见在因特网上位于http：//news.cnet.com/8301-13924_3-20059431-64.html的、标题为″How Intel′s3D tech redefines the transistor"的文章；也参见：Kavalieros等人的美国公开NO.2009/0090976，公开于2009年4月9日；Rakshit等人的美国专利NO.8,120,073；Rios等人的美国专利NO.7,973,389；Hareland等人的美国专利NO.7,456,476；以及Chau等人的美国专利NO.7,427,794。)
通常，可以通过在鳍阵列之上保形地沉积公共栅极来形成多个晶体管的阵列。另外，可以通过在鳍阵列之上保形地沉积多个公共栅极来形成多栅极晶体管阵列。在源极与漏极区域之间有三个栅极的这样的FinFET阵列称为三栅极晶体管。
在开发FinFET之前，开发了应变硅晶体管以增加对半传导沟道中的电荷载流子的迁移率控制。向晶体管材料中引入压缩应变往往增加电荷迁移率，从而产生对向栅极施加的电压的改变的更快切换响应。可以例如通过用外延生长的硅化合物替换源极和漏极区域中或者沟道本身中的体硅来引入应变。术语外延指的是受控晶体生长工艺，在该工艺中从体晶体的表面生长新外延晶体层，而维持下面的体晶体管的相同晶体结构。
尽管有三维结构和应变硅材料提供的改进，晶体管仍然随着器件尺度缩减到1-50纳米的范围内而继续遭受某些类型的性能下降。这些性能下降具体包括在半传导沟道与衬底之间的电荷泄漏。
实用新型内容
本实用新型旨在解决晶体管随着器件尺度缩减到1-50纳米的范围内而遭受某些类型的性能下降的问题，这些性能下降具体包括在半传导沟道与衬底之间的电荷泄漏。
根据本实用新型的一个方面，提供一种在硅衬底上的全隔离 FinFET晶体管，所述晶体管包括：
传导鳍沟道阵列，悬置于所述硅衬底之上并且通过绝缘层与所述硅衬底间隔开；
原位掺杂外延层，与所述传导鳍沟道阵列的部分接触，所述原位掺杂外延层悬置于所述硅衬底之上并且通过绝缘层与所述硅衬底间隔开；
保形栅极，覆盖在所述传导鳍沟道阵列上面，所述保形栅极可操作用于响应于施加的电压控制所述传导鳍沟道内的电流流动；以及
成对的绝缘沟槽，与所述传导鳍沟道基本上平行地对准。
优选地，所述保形栅极包括具有大于4.0的介电常数的电介质层和包括金属的体栅极材料。
优选地，还包括在所述硅衬底内的阱注入物和袋注入物中的一个或者多个注入物。
优选地，所述传导鳍沟道阵列包括外延生长的硅材料。
优选地，所述绝缘层是氧化物。
优选地，所述原位掺杂外延层与所述传导鳍沟道阵列的在所述保形栅极以外的部分接触。
根据本实用新型的另一方面，提供一种在硅衬底上形成的电隔离晶体管，所述晶体管包括：
一个或者多个半传导鳍沟道；
掺杂外延层，与所述半传导鳍沟道接触；
保形金属栅极，覆盖在所述一个或者多个半传导鳍沟道上面，所述栅极可操作用于响应于施加的电压控制所述半传导鳍沟道内的电流流动；
用于将所述半传导鳍沟道与邻近区域隔离的装置；以及
用于将所述半传导鳍沟道和所述掺杂外延层与所述硅衬底隔离以便防止向所述硅衬底中的电荷泄漏的装置。
根据如本文描述的一个实施例，通过在作为鳍的沟道与衬底之 间插入绝缘层而隔离沟道与衬底来防止FinFET器件中的沟道到衬底泄漏。绝缘层物理和电隔离鳍与衬底，因此防止在鳍与衬底之间的电流泄漏。理论上，在无泄漏时，器件为全通或者全断。
如果鳍包含两种不同材料，则可以容易去除底部材料而留下顶部材料，因此产生在硅表面上方悬置的半传导鳍阵列。然后如果希望则可以用氧化物填充在剩余顶部鳍材料下面的所得间隙以更好地支撑鳍并且隔离鳍沟道阵列与衬底。
类似地，根据如本文描述的一个实施例，通过在源极/漏极区域与衬底之间插入绝缘层而隔离源极/漏极区域与衬底来防止FinFET器件中的源极/漏极到衬底泄漏。绝缘层物理和电隔离源极/漏极区域与衬底，因此防止在源极/漏极与衬底之间的电流泄漏。因此，所得FinFET器件在栅极区域和源极/漏极区域二者中为全衬底隔离。
附图说明
在附图中，相同标号标识相似元件。未必按比例绘制附图中的元件的尺寸和相对位置。
图1A是现有技术平面FET的图解透视图。
图1B是现有技术FinFET的图解透视图。
图2是示出在形成如本文描述的全隔离FinFET时的基本步骤的高级工艺流程图。
图3是示出在形成如本文描述的全隔离FinFET的工艺中的附加细节的中级工艺流程图。
图4A是示出根据一个实施例的可以用来向硅衬底注入掺杂物并且形成鳍堆叠的工艺步骤序列的工艺流程图。
图4B是图4A中所示工艺流程形成的器件轮廓的侧视图，其中示出组成鳍堆叠的掩盖(blanket)层。
图5A是示出可以用来形成虚设芯棒(mandrel)和氮化硅间隔物的又一工艺步骤序列的工艺流程图。
图5B是图5A中所示工艺流程形成的器件轮廓的侧视图，其中示出完成的牺牲结构。
图6A图示工艺流程图，该工艺流程图示出可以用来使用侧壁图像转移工艺来图案化鳍堆叠的又一工艺步骤序列的工艺流程图。
图6B是图6A中所示工艺流程形成的器件轮廓的侧视图，其中示出完成的多层外延鳍阵列。
图7A是工艺流程图，该工艺流程图示出可以用来为图6B中所示外延鳍阵列提供局部化隔离的又一工艺步骤序列。
图7B是图7A中所示工艺流程形成的器件轮廓的侧视图，其中建立鳍间隔离。
图8A是工艺流程图，该工艺流程图示出可以用来在鳍阵列的任一端上蚀刻和填充隔离沟槽的又一工艺步骤序列。
图8B是图8A中所示工艺流程形成的器件轮廓的侧视图，其中在鳍阵列与邻近区域之间提供横向隔离。
图9A、10A、11A、12A和13A是在其中将沟道和源极/漏极区域与衬底隔离的工艺期间沿着栅极区域中的FinFET器件轮廓的线A-A'切割的侧视图。
图9B、10B、11B、12B和13B是在其中将沟道和源极/漏极区域与衬底隔离的工艺期间沿着源极/漏极区域中的FinFET器件轮廓的线B-B’切割的侧视图。
图9C、10C、11C、12C和13C是如本文描述的两晶体管结构的透视图，这些透视图示出在形成隔离栅极和源极/漏极结构时栅极区域(A-A’)的改变和源极/漏极区域轮廓(B-B’)的改变。
图9D是示出可以用来沉积牺牲栅极和间隔物的又一工艺步骤序列的工艺流程图。
图10D是工艺流程图，该工艺流程图示出示出可以用来制备鳍的用于原位掺杂外延生长的顶层表面的又一工艺步骤序列。
图11D是工艺流程图，该工艺流程图示出可以用来去除底部鳍层以创建空隙的又一工艺步骤序列。
图12D是工艺流程图，该工艺流程图示出可以用来向空隙填充氧化物以隔离鳍与衬底的又一工艺步骤序列。
图13D是工艺流程图，该工艺流程图示出可以用来用可操作金属栅极替换牺牲栅极的又一工艺步骤序列。
具体实施方式
在以下描述中，阐述某些具体细节以便提供对公开的主题内容的各种方面的透彻理解。然而，无这些具体细节仍然可以实现公开的主题内容。在一些实例中，尚未具体描述包括本文公开的主题内容的实施例的公知结构和半导体处理方法以免模糊本公开内容的其它方面的描述。
除非上下文另有要求，贯穿说明书和所附权利要求，字眼“包括(comprise)”及其变化，诸如“包括(comprises)”和“包括(comprising)”将在开放、包含意义上加以解释，也就是解释为“包括但不限于”。
贯穿说明书对“一个实施例”或者“一实施例”的引用意味着结合该实施例描述的具体特征、结构或者特性包含于至少一个实施例中。因此，在贯穿说明书的各处出现短语“在一个实施例中”或者“在一实施例中”未必都指代相同方面。另外，可以在本公开内容的一个或者多个方面中以任何适当方式组合具体特征、结构或者特性。
贯穿说明书对绝缘材料或者半传导材料的引用可以包括除了用来举例说明呈现的晶体管器件的具体实施例的材料之外的各种材料。不应狭义地解释术语“外延硅化合物”使外延生长的结构例如限于Si或者SiGe，但是实际上广义地解释术语“外延硅化合物”覆盖可以从晶体硅表面外延生长的任何化合物。
贯穿说明书对用于沉积氮化硅、二氧化硅、金属或者相似材料的常规薄膜沉积技术的引用包括诸如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、金属有机化学气相沉积(MOCVD)、等离子体增强化学气相沉积(PECVD)、等离子体气相沉积(PVD)、 原子层沉积(ALD)、分子束外延(MBE)、电镀、无电镀等这样的工艺。本文参照这样的工艺的示例描述具体实施例。然而，本公开内容和对某些沉积技术的引用不应限于描述的沉积技术。例如在一些境况中，可以备选地使用PVD来完成引用CVD的描述，或者可以备选地使用无电镀来实现指定电镀的描述。另外，对常规薄膜形成技术的引用可以包括原位生长膜。例如在一些实施例中，可以通过在受热室中使硅表面暴露于氧气或者潮气来实现控制氧化物生长至所需厚度。
贯穿说明书对半导体制作领域已知的用于图案化各种薄膜的常规光刻技术的引用包括涉及到光刻胶的旋涂-曝光-显影工艺序列。这样的光刻序列需要在光刻胶上旋涂、通过图案化的掩模使光刻胶的区域暴露于紫外光并且显影掉光刻胶的暴露(或者备选地未暴露)区域，由此向光刻胶转移正或者负掩模图案。光刻胶掩模然后可以用来将掩模图案蚀刻到一个或者多个下面的膜中。通常，如果后续蚀刻相对浅，则光刻胶掩模有效，这是因为可能在蚀刻工艺期间消耗光刻胶。否则，光刻胶可以用来图案化硬掩模，该硬掩模又可以用来图案化更厚的下面的膜。
贯穿说明书对半导体制作领域已知的用于选择性去除多晶硅、氮化硅、二氧化硅、金属、光刻胶、聚酰亚胺或者相似材料的常规蚀刻技术的引用包括诸如湿法化学蚀刻、反应离子(等离子体)蚀刻(RIE)、清洗、湿法清理、预清理、喷射清理、化学机械平坦化(CMP)等这样的工艺。本文参照这样的工艺的示例描述具体实施例。然而本公开内容和对某些沉积技术的引用不应限于描述的沉积技术。在一些实例中，两种这样的技术可以可互换。例如剥离光刻胶可能需要在湿法化学浴器中浸渍样本或者备选地向样本上直接喷射湿化学剂。
本文参照已经产生的FinFET结构的示例描述具体实施例；然而，本公开内容以及对某些材料、尺度以及处理步骤的细节和排序的引用为举例而不应限于所示公开内容和引用。
在图中，相同标号标识相似特征或者元件。未必按比例绘制图中的特征的尺寸和相对位置。
图1A示出在硅衬底102上构建的常规平面晶体管100。常规平面晶体管的部分包括有源区域104、源极106、漏极108、平面传导沟道110和栅极112。未示出的栅极电介质如本领域熟知的那样电隔离沟道与栅极。有源区域104占据衬底的顶层，该衬底可以用杂质来掺杂以创建具有净负或者净正电荷的阱。在常规平面晶体管100导通时，电流经过平面传导沟道110从源极106流向漏极108。通过施加栅极电压由栅极112控制平面传导沟道中的电流流动。与栅极电压关联的电场具有如果栅极电压超过某个阈值则接通常规平面晶体管100的效果。如果施加的栅极电压降至阈值电压以下，则常规平面晶体管100关断并且电流停止从源极106流向漏极108。由于栅极112仅能从一侧(即从平面传导沟道110的顶部)影响平面传导沟道110，所以向硅衬底102中的电荷泄漏往往在沟道/衬底结处出现。
图1B示出在硅衬底102上构建的常规FinFET器件150。与图1A中所示器件相似，常规FinFET器件150的部分包括有源区域104、源极152、漏极154、传导鳍沟道156和卷绕栅极(wrap-around)158。常规FinFET器件150的有源区域104可以用杂质来掺杂以创建具有净负或者净正电荷的阱。在常规FinFET器件150导通时，电流在卷绕栅极158的控制之下经过高的(tall)传导鳍沟道156从源极152流向漏极154。施加具有超过某个阈值电压值的值的电压接通常规FinFET器件150。如果施加的电压降至阈值电压值以下，则常规FinFET器件150关断，并且电流停止从源极152流向漏极154。由于卷绕栅极158从三侧影响传导鳍沟道156，所以实现对传导鳍沟道156的传导性质的改进控制。这样的改进控制使从传导鳍沟道156向硅衬底102的电荷泄漏虽然未被消除，但是被减少。由于鳍沟道160的载流容量比平面传导沟道110的载流容量大得多，所以常规FinFET器件150的切换特性也比常规平面晶体管100的切换特性有 提高。
可以以22nm和更小的技术节点构造用于如本文描述的全衬底隔离FinFET晶体管的鳍。例如鳍的宽度可以在范围18-22nm内，鳍高度在范围25-100nm内而优选范围50-75nm。在鳍之间的空间可以在与鳍的宽度相同的范围内，例如18-22nm。
对于22nm鳍而言，鳍的节距(即从一个鳍的中心到下一个鳍的中心的距离)将一般在范围40-48nm内并且通常是鳍的宽度的两倍，节距也是从一个空间的中心到下一个空间的中心的距离。因此，对于18nm的鳍宽度，优选36nm的节距，但是也可以使用在范围30-50nm内的节距。具有这些总体尺度和更小尺度的鳍用于如现在将参照图2-13D说明的本实用新型的各种实施例。随着半导体工艺发展，尺度也可以改变以与可用技术匹配。例如鳍根据所需设计特性和可用几何形状可以宽度在范围8-20nm内并且具有在范围10-200nm内的高度。
图2是描述制作工艺300中的基本动作的高级流程图，该制作工艺用于被设计用于防止沟道到衬底泄漏和源极/漏极到衬底泄漏的全隔离FinFET器件。在302，使用侧壁图像转移(SIT)工艺来形成多层半传导鳍阵列。在304，在硅衬底中形成成对的沟槽并且向该对沟槽填充绝缘材料以电隔离半传导鳍与邻近区域。在306，形成牺牲栅极。在308，从半传导鳍的顶层向外横向生长外延层而被原位掺杂。在310，通过插入绝缘层将半传导鳍和原位掺杂层与衬底隔离。在312，用可操作栅极替换牺牲栅极。
图3是描述用于图2中描述的全隔离FinFET器件的更具体制作工艺400的低级流程图。在402，向硅衬底注入并且沉积掩盖层鳍堆叠。掩盖层包括外延生长的双层，即氮化硅和未掺杂硅酸盐玻璃(USG)。在404，通过图案化氮化物和USG膜来形成虚设芯棒结构。在406，虚设芯棒用来执行侧壁图像转移(SIT)工艺以创建半传导鳍阵列，然后去除芯棒。在408，用绝缘材料填充在半传导鳍之间的空间以提供局部化鳍间隔离。在410，蚀刻隔离沟槽并且向隔离 沟槽填充绝缘氧化物。在412，在栅极区域中形成牺牲多晶硅栅极和偏移间隔物，而在414，在源极/漏极区域中从每个鳍的顶层各向同性地生长原位掺杂(ISD)外延层。在416，在栅极区域和源极/漏极区域二者中去除外延生长的双层的底层，从而创建空隙。在418，向空隙填充绝缘材料，诸如氧化物。在420，去除并且用可操作金属栅极替换牺牲多晶硅栅极。
以下参照图4A-13D，每组图通过呈现更全面工艺步骤序列和在完成该步骤序列时产生的对应侧视图来更具体示出来自图3的工艺步骤之一。
图4A和4B更具体图示步骤402，根据一个实施例，在该步骤中向硅衬底注入并且沉积掩盖层鳍堆叠。图4A示出包括步骤502、504、506、508、510和512的工艺步骤序列，可以执行这些步骤以形成图4B中所示掩盖层堆叠514。掩盖层堆叠514分别包括硅衬底516、掩盖外延生长半传导底层518(例如锗化硅(SiGe)或者另一外延硅化合物)、掩盖外延生长半传导顶层520(例如硅或者外延硅化合物)、掩盖氮化硅帽层522以及未掺杂的非晶硅酸盐玻璃(USG)的第一和第二掩盖牺牲层524和526。
在502，硅衬底可以接收阱注入物以分别根据制作的器件是否被设计为N-P-N或者P-N-P晶体管而变成用p型或者n型原子来掺杂。
在504，可以沉积或者生长焊盘氧化物层。在506，可以执行外延预清理步骤以制备硅衬底的用于外延晶体生长的表面。通常，外延预清理步骤使用湿法化学处理(诸如氢氟酸(HF))来去除所有表面氧化物(包括原生氧化物和在504沉积的焊盘氧化物层)。
在508，生长外延半传导底层518。半传导底层518可以由锗化硅制成，其中锗含量希望约为35％，并且厚度希望约为30nm。半传导底层518的锗含量可以范围从约20％到约60％。半传导底层518的厚度可以在范围约20nm-60nm内。此外，在508，通过从锗化硅半传导底层518的顶表面的外延晶体生长形成外延生长的半传导顶 层520。半传导顶层520可以由硅或者锗化硅制成，具有在约25nm-50nm的范围内的厚度。
在510，可以用掩盖氮化硅帽层522对外延半传导顶层520进行加帽。可以沉积氮化硅帽层522以用作具有约40nm的厚度的硬掩模。在512，可以例如使用常规方法(诸如本领域通常用来沉积多晶硅的方法)来分别沉积第一和第二USG牺牲掩盖层524和526。第一USG牺牲掩盖层524希望具有在范围约20nm-40nm内的厚度。第二USG牺牲掩盖层526希望具有在范围约80nm-120nm内的厚度。第一和第二USG牺牲掩盖层可以基本上相同，或者它们可以例如在密度上或者在一个或者多个其它膜性质的改变上有所差别，这可以在后续处理步骤中针对两个USG膜产生不同蚀刻速率。
图5A和5B更具体图示步骤404，在该步骤中形成牺牲芯棒以支撑在非常规侧壁图像转移(SIT)工艺中用作掩模结构的侧壁间隔物。SIT工艺可以对于图案化窄和/或近间距结构尤其有用。图5A示出包括步骤602、604和606的工艺步骤序列，可以执行这些步骤以形成图5B中的牺牲(虚设)芯棒614(示出三个)。每个芯棒614是支撑成对的侧壁间隔物628的图案化的未掺杂的非晶硅酸盐玻璃(USG)结构。在SIT工艺中，将向多层鳍的宽度转移侧壁间隔物628的宽度而不是使用掩模以图案化鳍。所得多层鳍的宽度在一个示例实施例中希望在范围约3-15nm内。此外，芯棒宽度630确定在示例实施例中希望在范围约10-50nm内的鳍间间距。类似地，侧壁间隔物628和芯棒614的均匀性分别确定鳍阵列内的鳍和鳍间距的均匀性。
在602，可以使用常规光刻和蚀刻工艺来图案化未掺杂的非晶硅酸盐玻璃(USG)的掩盖牺牲层526以形成芯棒614。由于常规光刻为半导体处理领域技术人员所熟知，所以在图中未明示，但是将简述它。常规光刻需要在光刻胶上旋涂、通过图案化的掩模使光刻胶的部分暴露于紫外光并且显影掉光刻胶的未暴露部分，由此向光刻胶转移掩模图案。光刻胶掩模然后可以用来将图案蚀刻到一个或 者多个下面的的层中。通常，如果后续蚀刻相对浅，则可以使用光刻胶掩模，这是因为可能在蚀刻工艺期间消耗光刻胶。可以使用这样的光刻胶掩模和对第一USG牺牲层有选择性的湿法蚀刻或者RIE化学剂来图案化第二USG牺牲层526。备选地，可以使用其中可接受部分消耗第一USG牺牲层524的定时蚀刻。
在604，可以使用常规沉积技术在USG结构526之上沉积保形氮化硅层(未示出)。
在606，可以执行掩盖(无掩模)湿法或者干法蚀刻以去除氮化物层的均匀厚度，因此形成成对的侧壁间隔物628。在这样的工艺中，可以使用芯棒614作为蚀刻停止层或者可以对蚀刻工艺进行定时。由于第一USG掩盖牺牲层524和芯棒614均为暂时的，所以可以可接受造成部分消耗这些层的非最优蚀刻选择性。根据使用的蚀刻工艺，侧壁间隔物628可以从芯棒614的顶表面略微或者显著倾斜掉(slope away)。
图6A和6B更具体图示步骤406，在该步骤中通过向掩盖层堆叠514转移侧壁间隔物628的覆盖区(图像)来图案化多层鳍阵列。图6A示出包括步骤702、704、706和708的工艺步骤序列，可以执行这些步骤以形成图6B中的多层鳍阵列714(示出六个)。根据一个实施例，每个多层鳍716包括图案化的外延锗化硅底层718、在图6中示出为由残留的图案化的氮化硅帽722覆盖的图案化的外延硅顶层720。
在702，在形成侧壁间隔物628之后，可以通过使用对氮化硅侧壁间隔物628高度地有选择性的湿法蚀刻或者干法蚀刻来蚀刻USG从而去除虚设芯棒614。用来去除芯棒614的蚀刻剂然后也将往往去除第一USG牺牲层524，除了它在侧壁间隔物628下面受保护之外。
在704，可以执行SIT工艺，在该工艺中在蚀刻下面的的层(524、522、520和518)的全堆叠时在示例实施例中使用剩余10nm以下的侧壁间隔物628作为硬掩模。在侧壁图像转移完成时，如图 6B中所示从硅衬底516竖直地延伸的所得多层鳍716将具有与侧壁间隔物628的覆盖区近似地相同的宽度和均匀性。因此，已经向鳍转移侧壁间隔物的图像。
在706，在鳍形成之后，可以使用常规湿法蚀刻剂(诸如热磷酸或者分别对体硅衬底516以及外延硅底层和顶层718和720有选择性的另一蚀刻剂)来去除覆盖多层鳍716的剩余侧壁间隔物628。
在708，可以例如使用基于HF的化学剂来去除第一USG牺牲层524的作为残留USG帽层(未示出)保留于多层鳍716上面的部分，因此留下包括氮化硅帽722的多层鳍716。
图7A和7B更具体图示步骤408，在该步骤中可以在多层鳍716之间沉积绝缘材料以形成局部地隔离的多层鳍阵列814。图7A示出包括步骤802、804、806、808、810和812的工艺步骤序列，可以执行这些步骤以形成图7B中的局部地隔离的多层鳍阵列814(示出六个鳍)。根据一个实施例，多层鳍716由局部化的鳍间隔离填充材料816和原硅酸四乙酯(TEOS)衍生的氧化物层或者TEOS818分离。
在802，可以向在多层鳍716之间的空间填充局部隔离填充材料816，例如氧化物。
在804，然后可以使用在氮化物帽722上停止的化学机械平坦化(CMP)工艺来平坦化填充的多鳍阵列。
在806，可以使用对下面的外延硅顶层720至少部分地有选择性的湿法化学蚀刻剂来去除氮化硅帽层722。
在808，可以使用对硅有选择性的蚀刻剂(诸如基于HF的湿化学蚀刻)来凹陷局部隔离填充材料816。凹陷的局部隔离填充材料816的最终厚度希望使得凹陷的局部隔离填充材料816的顶表面在位于外延锗化硅底层718内的点处与多层鳍716相交。
在810，可以在多鳍阵列814之上保形地沉积薄TEOS层818(例如少于约10nm厚)。TEOS层818将用作栅极电介质。
在812，可以沉积焊盘氮化物层820以便替换凹陷的填充材料 816并且在多层鳍阵列814的高度上方延伸。可以使用焊盘氮化物层820作为硬掩模以形成隔离沟槽。
图8A和8B更具体图示步骤410，在该步骤中在多鳍阵列814的任一侧上形成绝缘沟槽以隔离多层鳍阵列914与邻近区域。图8A示出包括步骤902、904、906、908、910和912的工艺步骤序列，可以执行这些步骤以形成图8B中所示横向地隔离的鳍阵列914。
在902，可以如以上描述的那样使用常规光刻技术来图案化焊盘氮化物层820，以便覆盖多鳍阵列814并且暴露超出多鳍阵列814的末端以外的区域。
在904，然后可以在去除局部隔离填充材料816和硅的蚀刻工艺期间使用焊盘氮化物层820作为硬掩模以在硅衬底516中创建深沟槽。用来创建隔离沟槽的蚀刻工艺希望是各向异性等离子体蚀刻。
在906，可以向深隔离沟槽填充绝缘体。绝缘体可以例如是二氧化硅，诸如高纵横比工艺(HARPTM)填充材料916。可以使用在从Santa Clara，California的Applied Materials，Inc.可用的专门化的化学气相沉积(CVD)设备上执行的专有工艺来沉积这样的HARPTM填充材料916。
在908，可以使用在焊盘氮化物层920上停止的CMP工艺来平坦化HARPTM填充材料916。
在910，可以使用HF浸渍来凹陷HARPTM填充材料916，继而为在912的氮化物去除步骤(例如热磷酸湿法蚀刻)。在所得示例横向地隔离的鳍阵列914中，如图8B中所示，HARPTM填充材料916的高度在鳍的高度以下、但是在鳍内的两个外延硅层718和720的结上方。
图9A、9B和9C更具体图示步骤412，在该步骤中形成牺牲栅极和间隔物。图9D示出包括步骤1002、1004和1006的工艺步骤序列，可以执行这些步骤以在栅极区域中形成覆盖在横向地隔离的六个鳍的阵列914上面的牺牲栅极1018(图9A)。在图9C中示出所得FinFET阵列1014(示出仅两个鳍)的透视图。
在1002，牺牲栅极1018可以保形地沉积于横向地隔离的鳍阵列914之上，并且与鳍基本上正交地对准。牺牲栅极1018因此与每个多层鳍的三侧邻接。牺牲栅极1018可以根据用来形成常规平面晶体管栅极的技术例如由多晶硅制成。牺牲栅极1018是。在1004，可以沉积掩盖氮化硅硬掩模层1020。牺牲栅极1018和氮化硅硬掩模层1020仅形成于栅极区域中、未形成于源极/漏极区域中。这可以通过沉积掩模沉积材料来实现。或者膜可以掩盖沉积于栅极和源极/漏极区域二者之上，然后从源极和漏极区域被选择性地去除(图9B)，使得牺牲栅极1018和氮化硅硬掩模层1020二者仅保留于栅极区域中(图9A)。
图9B因此基本上是图8B的再现。图9A是如图9C中呈现的透视图1014中所示沿着切割线A-A'在栅极区域中的FinFET阵列的侧视图。图9B是如图9C中呈现的透视图1014中所示沿着切割线B-B’在源极/漏极区域中的FinFET阵列的侧视图。在沿着A-A'形成保形栅极之前，图9B是在图8B中出现的相同结构914。
在1006，可以使用另一常规沉积和图案化(光刻和蚀刻)循环在牺牲栅极结构的任一侧上形成偏移间隔物。间隔物可以例如由氮化硅制成。然而，间隔物在图9C中出现，来自A-A’的截图和来自B-B’的截图均未与间隔物相交，因此它们未出现于图9A或者9B中所示侧视图中。
图10A、10B和10C更具体图示步骤414，在该步骤中从半传导顶层520外延地生长原位掺杂(ISD)层。图10D示出包括步骤1102、1104和1106的工艺步骤序列，可以执行这些步骤以在源极/漏极区域中形成掺杂的鳍阵列1112(图10B)。在图10C中示出掺杂的鳍阵列114的透视图。
在1102，可以使用N2H2气体来完成第一预清理。
在1104，可以完成与本领域已知为在形成硅化镍之前的预清理相似的第二预清理SiCoNi。预清理步骤1102和1104从硅表面去除原生氧化物、杂质等以允许外延晶体生长未受表面污染物阻碍地 发生。
在1106，可以从多层鳍的图案化的外延硅顶层720向外外延地生长晶体硅以形成分面的原位掺杂(ISD)结构1108。可以通过在外延生长期间引入杂质(诸如硼或者磷)来实现原位掺杂。如果贯穿充分长的时间间隔维持外延生长，则从鳍的顶层延伸出的分面的ISD结构1108可以一起生长以形成与凹陷的氧化物816接触的外延层。
图11A、11B和11C更具体图示步骤416，在该步骤中去除传导鳍沟道的底层以在顶部半传导材料与衬底之间创建空隙。图11D示出包括步骤1202和1204的工艺步骤序列，可以执行这些步骤以形成栅极区域空隙1210(图11A)和源极/漏极区域空隙1212(图11B)。在图11C中图示在形成空隙之后的透视图1214。
在1202，可以执行另一SiCoNi预清理以有助于在后续步骤中的更有效的膜去除。
在1204，可以例如使用在盐酸溶液中的浸渍从在栅极区域和源极/漏极区域二者中的鳍去除外延底层718以创建栅极区域空隙1210和源极/漏极区域空隙1212。外延顶层720保持悬置于衬底上方，但是在垂直方向上(即沿着鳍)锚定到栅极结构。
在备选工艺流程中，图10B中所示分面的ISD结构1108的外延生长可以发生于形成栅极区域空隙1210和源极/漏极区域空隙1212之后。
图12A、12B和12C更具体图示步骤418，在该步骤中可以向栅极区域空隙1210和源极/漏极区域空隙1212填充氧化物以物理和电绝缘传导鳍沟道与衬底。图12C示出包括步骤1302、1304、1306和1308的工艺步骤序列，可以执行这些步骤以在栅极区域(图12A)中形成向源极/漏极区域(图12B)中的衬底隔离鳍沟道1312延伸的衬底隔离鳍沟道阵列1310。在图12C中示出全衬底隔离鳍沟道的透视图1310。
在1302，可以通过在栅极和源极/漏极区域二者中从硅衬底516 的表面生长二氧化硅来填充栅极区域空隙1210和源极/漏极区域空隙1212。然后在源极/漏极区域中，可以生长或者沉积附加氧化物至略微在栅极上面的氮化硅间隔物和硬掩模的高度上方的高度。
在1304，可以执行常规退火工艺以在源极/漏极区域中的分面的ISD结构1108内扩散掺杂物。
在1306，可以例如使用其中氮化硅硬掩模层1020可以用作抛光停止层的常规CMP工艺来抛光氧化物。
在1308，可以通过使用各向异性(向下引向)等离子体蚀刻工艺从栅极去除氮化硅硬掩模1020而未去除氮化硅侧壁间隔物，继而为常规湿法化学清理步骤。
图13A、13B和13C更具体图示步骤420，在该步骤中用可操作栅极替换牺牲栅极。这样的工艺被本领域技术人员称为替换金属栅极(RMG)工艺。图13D示出包括步骤1402、1404、1406、1408和1410的工艺步骤序列420，可以执行这些步骤以在栅极区域中形成可操作栅极结构1412(图13A)。在图13C中示出可操作栅极结构1412的透视图1414。
在1402，可以例如使用对氮化硅和二氧化硅有选择性的侵蚀硅的湿化学蚀刻剂来去除牺牲多晶硅栅极。或者可以在相同工艺步骤中使用两部分(two-part)干法蚀刻工艺以去除多晶硅栅极和栅极电介质(1404)。
在1406，可以如图13B中所示回蚀源极/漏极区域中的氧化物1318至与外延顶层720重合的高度。
在1408，可以在栅极区域中的外延顶层720之上保形地沉积具有大于约4.0的高介电常数(k)的高k栅极电介质1418。
在1410，可以在栅极区域中并且也在源极/漏极区域中沉积可操作金属栅极1420作为去往隔离鳍的金属接触层(即外延顶层720)。与牺牲栅极1018相似，可操作金属栅极与每个多层鳍的三侧邻接，使得向栅极施加的电势可以从三个方向中的每个方向影响在鳍内流动的电流。
可以组合以上描述的各种实施例以提供更多实施例。在本说明书中引用的和/或在申请数据表中列举的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开通过引用而完全结合于此。可以如为了运用各种专利、申请和公开的概念而必需的那样修改实施例的方面以提供更多实施例。
将理解虽然本文出于示例的目的而描述本公开内容的具体实施例，但是可以进行各种修改而未脱离本公开内容的精神实质和范围。因而，本公开内容除了受所附权利要求限制之外不受限制。
可以按照以上详述的描述对实施例进行这些和其它改变。一般而言，在所附权利要求中，不应解释使用的术语使权利要求限于在说明书和权利要求中公开的具体实施例，但是应当解释这些术语包括所有可能实施例以及这样的权利要求有权具有的等效含义的完全范围。因而，权利要求未受公开内容限制。

Claims (7)

1.一种在硅衬底上的全隔离FinFET晶体管，其特征在于，所述晶体管包括：
传导鳍沟道阵列，悬置于所述硅衬底之上并且通过绝缘层与所述硅衬底间隔开；
原位掺杂外延层，与所述传导鳍沟道阵列的部分接触，所述原位掺杂外延层悬置于所述硅衬底之上并且通过绝缘层与所述硅衬底间隔开；
保形栅极，覆盖在所述传导鳍沟道阵列上面，所述保形栅极可操作用于响应于施加的电压控制所述传导鳍沟道内的电流流动；以及
成对的绝缘沟槽，与所述传导鳍沟道基本上平行地对准。
2.根据权利要求1所述的FinFET晶体管，其特征在于，所述保形栅极包括具有大于4.0的介电常数的电介质层和包括金属的体栅极材料。
3.根据权利要求1所述的FinFET晶体管，其特征在于，还包括在所述硅衬底内的阱注入物和袋注入物中的一个或者多个注入物。
4.根据权利要求1所述的FinFET晶体管，其特征在于，所述传导鳍沟道阵列包括外延生长的硅材料。
5.根据权利要求1所述的FinFET晶体管，其特征在于，所述绝缘层是氧化物。
6.根据权利要求1所述的FinFET晶体管，其特征在于，所述原位掺杂外延层与所述传导鳍沟道阵列的在所述保形栅极以外的部分接触。
7.一种在硅衬底上形成的电隔离晶体管，其特征在于，所述晶体管包括：
一个或者多个半传导鳍沟道；
掺杂外延层，与所述半传导鳍沟道接触；
保形金属栅极，覆盖在所述一个或者多个半传导鳍沟道上面，所述栅极可操作用于响应于施加的电压控制所述半传导鳍沟道内的电流流动；
用于将所述半传导鳍沟道与邻近区域隔离的装置；以及
用于将所述半传导鳍沟道和所述掺杂外延层与所述硅衬底隔离以便防止向所述硅衬底中的电荷泄漏的装置。
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CN103887172B (zh) * 2012-12-21 2017-09-12 意法半导体公司 全衬底隔离finfet晶体管
CN109300846A (zh) * 2017-07-24 2019-02-01 格芯公司 用于产生表面电荷的包括压电衬垫的finfet装置及其制造方法
CN109300846B (zh) * 2017-07-24 2023-10-27 格芯(美国)集成电路科技有限公司 用于产生表面电荷的包括压电衬垫的finfet装置及其制造方法
CN109585549A (zh) * 2017-09-28 2019-04-05 台湾积体电路制造股份有限公司 FinFET及其形成方法
CN109585549B (zh) * 2017-09-28 2022-05-31 台湾积体电路制造股份有限公司 FinFET及其形成方法
US11404324B2 (en) 2017-09-28 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Fin isolation structures of semiconductor devices
CN111029406A (zh) * 2019-11-14 2020-04-17 中国科学院微电子研究所 一种半导体器件及其制备方法
CN111312818A (zh) * 2019-11-14 2020-06-19 中国科学院微电子研究所 一种半导体器件的制备方法

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US8956942B2 (en) 2015-02-17
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CN103887172A (zh) 2014-06-25
CN107256844A (zh) 2017-10-17
US9520393B2 (en) 2016-12-13
US20140175554A1 (en) 2014-06-26
CN107256844B (zh) 2021-06-25
US9893147B2 (en) 2018-02-13
US20170053981A1 (en) 2017-02-23
US20150108585A1 (en) 2015-04-23

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