CN108987365A - 具有减小的开关节点振铃的三维电源模块 - Google Patents

具有减小的开关节点振铃的三维电源模块 Download PDF

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Publication number
CN108987365A
CN108987365A CN201810832541.9A CN201810832541A CN108987365A CN 108987365 A CN108987365 A CN 108987365A CN 201810832541 A CN201810832541 A CN 201810832541A CN 108987365 A CN108987365 A CN 108987365A
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CN
China
Prior art keywords
tube core
package part
intermediate plate
part according
synchronous
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CN201810832541.9A
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English (en)
Inventor
J·A·赫尔嵩末
O·J·洛佩斯
J·A·浓趣勒
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN108987365A publication Critical patent/CN108987365A/zh
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    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

本申请公开具有减小的开关节点振铃的三维电源模块。同步降压转换器的高频电源模块(800)有漏极向下直接焊接到引脚框架的焊盘(801)的控制管芯(810)；焊盘(801)连接到VIN，且到控制管芯(810)的VIN连接表现消失的阻抗和电感，因此将开关节点电压振铃的幅值和持续时间减小多于90％。因此输入电流从焊盘垂直进入控制管芯端子。控制管芯(810)顶部上的开关节点夹片(840)被设计为具有面积足够大以漏极向下的方式放置同步管芯(820)在控制管芯顶部上；电流继续垂直流过转换器堆叠。同步管芯的有效面积等于或大于控制管芯的有效面积；同步管芯的物理面积等于或大于控制管芯的物理面积。同步管芯(820)的源极端子由设计为充当散热器的夹片(860)连接到地。

Description

具有减小的开关节点振铃的三维电源模块
本申请是分案申请，原申请的申请日为2012年02月07日，申请号为201280007839.7，国际申请号为PCT/US2012/024171，发明名称为“具有减小的开关节点振铃的三维电源模块”。
技术领域
本发明总体涉及半导体器件和工艺的领域，并且更具体涉及具有高效率并且以减小的开关节点振铃工作在高频下的电源模块的系统结构和制造方法。
背景技术
DC-DC电源电路，尤其是开关模式电源电路的类别，在功率开关器件中是受欢迎的系列。特别适合于新兴的输电需求的是同步降压转换器，其具有串联连接的并且由共同的开关节点耦合在一起的两个功率MOS场效应晶体管(FET)。在降压转换器中，控制FET管芯(也称为高边开关)连接在供给电压VIN和LC输出滤波器之间，并且同步(sync)FET管芯(也称为低边开关)连接在LC输出滤波器和地之间(同步FET替换续流二极管(free wheelingdiode)充当同步整流器)。转换器还包括驱动器电路和控制器电路。
输出电路的电感器用作电源电路的能量存储。通常的电感器应是约300到400nH，从而可靠维持恒定输出电压VOUT。
一些功率开关器件用功率MOSFET、驱动器电路、控制器电路构建为分离的管芯。每个管芯通常附连到金属引脚框架的矩形或正方形焊盘，并且该焊盘由作为输出端子的引脚围绕。引脚可以在没有悬臂延伸的情况下成形，并且以四方扁平无引脚(QFN)或小型外壳无引脚(SON)器件的方式布置。源自管芯的电气连接由键合引线提供。这样的组件通常被封装在塑料封装中，并且已封装的部件作为分立构件块用于电源系统的板级组装。
在其他功率开关器件中，功率MOSFET与驱动器和控制器管芯被并排组装在引脚框架焊盘上，该引脚框架焊盘进而在全部四个侧面上由用作器件输出端子的引脚围绕。引脚也可以用QFN或SON形式成形。
在一些近来引入的先进组装中，铜夹用来替换连接线。这些夹片是宽的并且引入较小的寄生电感。
在另一近来发展中，控制FET和同步FET以堆叠的方式被垂直组装在彼此的顶部上，其中该两者中物理面积较大的管芯附连到引脚框架焊盘，并且夹片提供到开关节点和堆叠顶部的连接。在该封装中，同步FET芯片被组装到引脚框架焊盘上，其中源极端子焊接到引脚框架焊盘。控制FET芯片的源极联结到同步管芯的漏极，从而形成开关节点，并且控制FET芯片的漏极连接到输入供给电压VIN。在两个FET之间插入的夹片连接到开关节点。焊盘处于地电位并且用作散热器。在堆叠顶部上的细长夹片将控制FET的漏极端子连接到输入供给电压VIN。
在图1中示出了上一段中描述的典型的转换器，总体标为100。控制FET 110堆叠在同步(sync)FET 120上。控制FET管芯110相对于同步FET管芯120具有较小的面积。QFN金属引脚框架具有矩形扁平焊盘101。引脚102a和102b沿焊盘的两个相对侧面成直线布置。FET管芯的堆叠是源极向下的配置。同步FET 120的源极由焊接层121焊接到引脚框架焊盘101。由焊接层122焊接在同步FET 120的漏极上的第一夹片140具有由焊接层111附连的控制FET110的源极。第一夹片140因此用作转换器的开关节点端子。第二夹片160由焊接层112连接到控制FET 110的漏极。第二夹片160附连到引脚框架的引脚102b，并且因此连接到输入供给电压VIN。该转换器可以高效地工作在500kHz直到1MHz的频率。
图2是图1的同步降压转换器组件的电路图表示。在图2中，栅极210b示作由引线键合连接到引脚，引线键合关联于约1.94nH的寄生电感LGATE(211)和约26mΩ的寄生阻抗RGATE(212)。因为控制FET 210源极向下组装到第一夹片140上，所以源极210a的寄生阻抗RSOURCE(213)几乎为零。因为源极向下组装，所以源极210a的寄生电感也是微小的。
图2进一步列出同步FET 220到引脚框架焊盘101的通常的寄生电感和阻抗。由于源极220a通过焊接连接到焊盘，因此该连接的寄生电阻RSOURCE(224)是微小的(约0.001mΩ)。由于同步FET 220焊接附连到第一夹片140上，因此漏极220c的寄生阻抗RDRAIN(221)几乎为零；漏极220c的寄生电感也很低。栅极220b由引线键合连接到引脚，并且因此关联于约1.54nH的寄生电感LGATE(223)和约22mΩ的寄生阻抗RGATE(222)。
如在图2中示出，转换器的负载电流从开关节点240流过第一夹片140到输出电感器VOUT(270)，该第一夹片140附连到引脚框架的相应引脚。沿第一夹片140，寄生阻抗ROUT(272)约为0.2mΩ，并且寄生电感LOUT(271)约为0.45nH。图2进一步示出从开关节点240连接到引脚框架的相应引脚的控制FET的栅极回路。由于该连接是通过引线键合进行的，因此该连接贡献约1.54nH的寄生电感241和约22mΩ的寄生阻抗242。
发明内容
申请人观察到，在如图1中示出的典型系统的ON循环的初始阶段期间，存在与开关节点电压关联的过多振铃，时间间隔约为50ns，最大值约为25V。该峰值电压可以接近或超过在系统中使用的MOSFET的击穿电压，并且因此对于许多应用，振铃的幅值和持续时间是不可接受的。
在详细分析之后，申请人发现，过多振铃的根本原因与在转换器的输入节点处的过多寄生阻抗和电感关联，这导致能量在其和输出电路之间交换，并且表现为输出节点处的振铃。此外，申请人发现，对输入节点处的寄生电感和阻抗贡献最显著的是将控制FET的漏极连接到输入供给电压VIN的引脚框架端子102b的细长夹片。
申请人进一步发现，即使细长夹片由高导电的材料例如铜制作，其在转换器中也被配置为使得控制FET的漏极和引脚框架端子之间流动的输入电流必须沿夹片的长度(包括颈部部分161)流动，并且流过该夹片的狭窄截面。申请人确定，在这样的转换器中，夹片通常在输入节点处添加600pH的电感和0.5mΩ的阻抗。
申请人通过将转换器的输入端子直接连接到引脚框架焊盘，由此消除源自转换器电路输入节点的与夹片关联的寄生效应，从而解决该问题。
这可以通过以下步骤来实现，例如：用漏极向下FET作为控制FET来构造转换器，并且将漏极端子直接放置在可附连到外部电路板的金属焊盘上，因此输入电流从Vin端子竖直并垂直流动到控制FET的漏极。这得到了几乎没有任何寄生电感或阻抗的电流路径。在控制管芯顶部上的开关节点夹片被设计为具有足够大的面积，从而将同步管芯漏极向下放置在控制管芯顶部上，使得电流继续垂直流过转换器堆叠。同步管芯的源极端子由第二夹片连接到地。该实施例经测试，将开关节点电压振铃的幅值和持续时间减小多于90％。
随后在关联附图的帮助下，将更详细描述本发明的该实施例和其他实施例。
附图说明
图1示出根据现有技术组装的同步降压转换器的截面图，其中大面积的同步FET管芯附连到引脚框架焊盘，并且小面积的控制FET管芯在其顶部上；该小面积的控制FET管芯由细长的夹片连接到引脚。
图2是在图1中示出的同步降压转换器的本申请人的电路图表示。
图3是描绘在如图2中示出的同步降压转换器的启动之后，以时间(以纳秒为单位)为函数的开关节点电压(以伏特为单位)的图。
图4显示以寄生输入电感(以皮亨为单位)为函数的同步降压转换器的开关节点电压振铃的幅值(以伏特为单位)。
图5A、5B和5C显示根据本发明的实施例组装的同步降压转换器模块的结构。
图5A是穿过模块的透明包封的顶视图。
图5B是图5A的模块沿模块切割线的截面图。
图5C是图5A的模块沿垂直于图5B切割线的另一切割线的截面图。
图6是在图5A、5B和5C中示出的同步降压转换器的本申请人的电路图表示。
图7是描绘在如图5A、5B和5C中示出的同步降压转换器的启动之后，以时间(以纳秒为单位)为函数的开关节点电压(以伏特为单位)的图。
图8A、8B和8C显示根据本发明的另一实施例组装的同步降压转换器模块的结构。
图8A是穿过模块的透明包封的顶视图。
图8B是图8A的模块沿模块切割线的截面图。
图8C是图8A的模块沿垂直于图8B切割线的另一切割线的截面图。
图9A、9B和9C显示根据本发明的另一实施例组装的同步降压转换器模块的结构。
图9A是穿过模块的透明包封的顶视图。
图9B是图9A的模块沿模块切割线的截面图。
图9C是图9A的模块沿垂直于图9B切割线的另一切割线的截面图。
图10A、10B和10C显示根据本发明的又一实施例组装的同步降压转换器模块的结构。
图10A是穿过模块的透明包封的顶视图。
图10B是图10A的模块沿模块切割线的截面图。
图10C是图10A的模块沿垂直于图10B切割线的另一切割线的截面图。
具体实施方式
当如在图1中示出的示例同步降压转换器在操作时，已观察到，以时间为函数的开关节点电压VSW的启动如在图3中由仿真波形301描绘。以伏特为单位测量的开关节点电压VSW显示为时间(以纳秒为单位)的函数。如图3示出，电压在被阻尼至12V的最终稳定值之前，通过高达25V的快速偏移(excursion)而周期性地摆动。开关节点电压的这个所谓的振铃行为持续60ns和80ns之间。对于许多转换器应用，开关节点电压的该强烈且长期的振铃是不可接受的。
在详细分析中，申请人发现，开关节点电压的这些振荡的根本原因是在图1中标为160的细长夹片的高寄生电感LIN(600pH，在图2中标为261)和寄生阻抗RIN(0.5mΩ，在图2中标为262)。夹片具有细长的延伸部分，用于将控制输入端子连接到输入供给电压VIN。结果是，从VIN到控制管芯(110)的输入端子的电流横向流过具有寄生电感和阻抗的夹片160的长度。图4示出以寄生电感LIN(以皮亨为单位测量)为函数的接通开关节点电压VSW(以伏特为单位测量)的数据和内插值。在100pH(测量值401)的寄生输入电感LIN下，开关节点电压VSW经历19V以上的偏移。如提到的，在图2的电路中，寄生输入电感LIN可以是600pH。这将导致开关节点电压VSW达到高达25V的偏移。在图4中，将LIN降低到50pH(数据点402)仍导致多于以上的开关节点电压摆动。
图5A、5B和5C示出对上面问题的一个解决方案。在该图中示出的转换器具有输入电流，该输入电流从焊盘501垂直流动到控制FET510的漏极端子，而不经过具有显著寄生阻抗或电感的任何元件。控制FET直接附连到引脚框架焊盘，该引脚框焊盘连接到VIN。控制FET在该转换器中是漏极向下的n沟道MOSFET。因此，输入电流(I)从焊盘垂直进入控制管芯漏极端子；对于焊接附连，输入电流可以在没有阻抗和电感的情况下到达控制管芯的漏极。同步管芯放置在控制管芯的顶部上，并且漏极向下附连到控制管芯的源极。电流因此继续垂直流过转换器堆叠。同步管芯的源极端子由被设计为用作散热器的夹片连接到地。结果是，开关节点电压的振铃减少了90％以上的持续时间和75％以上的幅值(更详细见于图7)。
在穿过透明包封化合物的顶视图中，图5A描绘了针对图5B和图5C的截面的剖面线。转换器500具有同步MOSFET管芯520，其堆叠在控制MOSFET管芯510上。由于导通(ON)状态的电阻RON与有效/有源(active)管芯面积成反比，因此同步降压转换器的占空比确定控制FET相对于同步FET所需的有效面积的比率。在图5A、5B和5C的示例模块中，预期占空比在大部分时间为低(<0.5)。因此控制FET关闭，并且在大部分操作期间不导通；并且同步FET在大部分循环时间导通。为减少降压转换器的导通损耗，PLOSS＝I2RON，使同步FET管芯520的有效面积等于或大于控制FET管芯510的有效面积是有利的。因此，同步管芯520的物理面积也等于或大于控制管芯510的物理面积。
图5A、5B和5C进一步示出带有一般QFN型配置的金属引脚框架，其具有矩形扁平器件组装焊盘(DAP)501，用作源自VIN的输入电流(I)的输入端子。引脚框架的引脚平行于矩形焊盘501的四个侧面布置。分立引脚标为502；其他引脚以组成群：组502a连接到焊盘501；组502b和502c用作到电气接地的端子和到热能(热量)转移的路径；以及组502d用作到开关节点和输出电流的端子。应注意，其他实施例可以具有不同的引脚配置，尤其是为了具体的热量分布需要。
如提到的，在图5A、5B和5C的示例中，控制管芯510的面积等于或小于同步管芯520的面积。由于n型导电沟道管芯的实施例需要将控制管芯漏极向下组装在引脚框架焊盘上，因此小的控制管芯在堆叠组件中需要被垂直安置在大的同步管芯下面。因此，将控制管芯510的源极连接到同步管芯520的漏极的开关夹片540(也称为第一夹片)可以被设计为使得其延伸其顶侧540a的可焊接区域以适应大面积的同步管芯520。一种用于开关夹片540的优选制造方法包括半刻蚀技术，其允许梁状的背脊件(rigid)(支柱)540b形成为从第一夹片540的一侧凸出，从而有助于第一夹片540附连到引脚框架的引脚组502d(见于图5B)。
在带有漏极向下堆叠的FET的转换器组件中，同步管芯520的源极端子被安置在堆叠的顶部上，并且必须电气连接到地。连接第二夹片560被设计为将由操作转换器产生的大部分工作热量传导到衬底中的吸热器。因此，该实施例的第二夹片560具有充当散热器的大金属面积，并且沿相对的夹片侧面优选具有两个细长背脊件(支柱)560a(见于图5C)，以便将热量传导到引脚502b和502c，并且从那里传导到衬底中的吸热器。在带有不同引脚配置的其他实施例中，夹片560可以被设计为具有三个背脊件，用于增强从转换器的热量移除；在其他实施例中，一个背脊件560a可以是足够的。背脊件560a被形成为足够高，使得它们可以被焊接到焊盘501的相对侧面上的引脚组502b和502c。制造带有背脊件560a的第二夹片560的优选方法是应用于金属板材的半刻蚀技术。
堆叠MOSFET优选包封在保护性封装化合物590中，从而形成模块。优选包封方法是模塑技术。在图5B和5C中示出的实施例中，模塑模块的厚度591约为1.5mm。由于如在上面提到的，开关夹片540优选由半刻蚀技术制造，因此将由半刻蚀制备打开的任何空间(例如缝隙590a)用包封化合物填充以便增强包封模块的鲁棒性是有利的。在图5A中，实施例500具有如下的模塑封装横向尺寸：约6mm的长度592、约5mm的宽度593。
图6是如在图5A、5B和5C中示出的示例同步降压转换器的电路图表示。从供给电压VIN(660)流动到控制FET 610的漏极610c的输入电流垂直流过引脚框架焊盘(在图5A、5B和5C中的501)的厚度，从而得到接近零的寄生电感LIN(661)和寄生阻抗RIN(662)。
在图6中进一步示出，栅极610b通过引线键合连接到引脚框架的引脚，并且因此具有约1.94nH的寄生电感LGATE(611)和约26mΩ的寄生阻抗RGATE(612)。因为源极610a直接焊接到充当开关节点640的第一夹片540上，所以控制FET 610的源极610a的寄生阻抗RSOURCE(613)几乎为零；同样，源极610a的任何寄生电感也几乎可忽略。
图6进一步列出与漏极向下同步FET 620连接到开关节点及其源极620a连接到地650有关的寄生效应。沿第二夹片到供给电压VIN的寄生阻抗RSOURCE(624)和寄生电阻不为0，但其对输入电流的影响是可忽略的。由于同步FET 620附连到第一夹片540(开关节点640)上，因此在漏极620c和第一芯片之间的寄生阻抗RDRAIN(621)几乎为零；漏极620c的寄生电感也几乎为零。
栅极620b由引线键合联结到引脚框架的引脚，并且因此具有约1.54nH的寄生电感LGATE(623)和约22mΩ寄生阻抗RGATE(622)。在图6中，转换器的负载电流从开关节点640流过附连到引脚框架的相应引脚的第一夹片(在图5A、5B、5C中的540)，流到输出电感器(在图6中没有示出)和VOUT(670)。沿第一夹片540，寄生阻抗ROUT(672)约为0.2mΩ，并且寄生电感LOUT(671)约为0.45nH。图6进一步示出从开关节点640连接到引脚框架的相应引脚的控制FET的栅极回路。由于该连接通过引线键合进行的，因此该连接贡献约1.54nH的寄生电感641和约22mΩ的寄生阻抗642。
当如在图5A、5B和5C中示出的示例同步降压转换器工作时，以时间为函数的开关节点电压VSW 701的开始的波形可以如在图7中描绘的。如图7示出，电压在其被迅速阻尼到12V的最终稳定值之前，以几个高达16.3V的较小偏移而摆动。电压的该类型的振铃行为持续10ns和15ns之间，并且因此简短且温和。
其他仿真和数据已表明，根据图5A、5B和5C组装的同步降压转换器的效率可以达到89.5％的值，而根据图1组装的转换器的效率仅为88.5％。即，效率损失减小了几乎百分之8。
总体标为800并且在图8A、8B和8C中示出的本发明的另一实施例的特征在于，引脚框架焊盘801的面积被减小到可与控制管芯810的面积相比拟。图8B与图5B的比较说明，由于焊盘金属的量减少，因此可以使用更多的包封化合物890。包封化合物的量增加使模块800对温度偏移和潮湿环境的鲁棒性增加。该措施减小了在化合物和金属之间脱层或化合物折断的风险。
如在图8B中示出，第一夹片840被设计为使得其延伸其顶侧840a的可焊接区域，从而适应大面积的同步管芯820。一种用于第一夹片840的优选制造方法包括半刻蚀技术，其允许梁状的背脊件840b形成为从第一夹片840的一侧凸出，从而有助于第一夹片840附连到引脚框架的引脚组802d。第二夹片860被设计为将在转换器的操作期间产生的大部分工作热量传导到衬底中的吸热器。因此，该实施例的第二夹片860具有充当散热器的大金属面积，并且沿相对夹片侧面优选具有两个细长背脊件860a，以便将热量传导到引脚802b和802c，并且从那里传导到衬底中的吸热器。在其他实施例中，夹片860被设计为具有三个背脊件，用于增强从转换器的热量移除；然而，在其他实施例中，一个背脊件可以是足够的。背脊件860a形成为足够高，使得它们可以被焊接到焊盘801的相对侧面上的引脚组802b和802c。制造带有背脊件860a的第二夹片860的优选方法是应用于金属板材的半刻蚀技术。
总体标为900并且在图9A、9B和9C中示出的本发明的又一实施例包括其面积与在图8中的实施例的焊盘面积相似的引脚框架焊盘901，但在焊盘区域中存在锯齿状凹坑903。通过半刻蚀技术，矩形状凹坑903被形成为具有深度903a以及横向尺寸903b和903c，使得矩形控制管芯910可以放置在该锯齿状凹坑中。同步管芯被标为920。因此，第一夹片940不需要用于附连到引脚框架引脚的凸出背脊件，而是可以保持基本扁平的板件，并且因此支持减小总模块厚度的当前趋势。在带有包封化合物990的模块900中，与在图5中的示例模块的1.5mm的厚度591相比，厚度991仅是1.3mm。在图9A和9C中，第二夹片960被设计为将由操作转换器产生的大部分工作热量传导到衬底中的吸热器。因此，该实施例的第二夹片960具有充当散热器的大金属面积，并且沿相对夹片侧面优选具有两个细长背脊件960a，从而将热量传导到引脚902b和902c，并且从那里传导到衬底中的吸热器。在带有不同引脚配置的其他实施例中，夹片960被设计为具有三个背脊件，用于增强从转换器的热量移除，或在其他实施例中具有一个背脊件。
图10A、10B和10C示出总体标为1000并且针对高占空比操作的另一实施例。实施例1000的特征在于，控制管芯1010和同步管芯1020的面积基本相等。作为例子，在图10B中的横向尺寸1010a和1020a可以每个都是3.5mm。由于n型导电沟道管芯更容易以漏极向下的方式组装在引脚框架焊盘1001上，因此控制管芯1010可以在堆叠组件中垂直安置在同步管芯1020下面。因此，将控制管芯1010的源极连接到同步管芯1020的漏极的开关夹片(第一夹片)1040可以被设计为使得其具有适应同步管芯1020的可焊接表面1040a和适应控制管芯1010的可焊接表面1040c。一种用于开关夹片1040的优选制造方法包括半刻蚀技术，其允许形成适当表面面积和从第一夹片1040的一侧凸出的梁状背脊件(支柱)1040b，从而有助于第一夹片1040附连到引脚框架的引脚组1002d(见于图10B)。在带有漏极向下堆叠FET的转换器组件中，同步管芯1020的源极端子被安置在堆叠的顶部上，并且必须电气连接到地电位。连接第二夹片1060被设计为将由操作转换器产生的大部分工作热量传导到衬底中的吸热器。因此，该实施例的第二夹片1060具有充当散热器的大金属面积，并且沿相对夹片侧面具有两个(或甚至三个)细长背脊件1060a，从而将热量传导到引脚1002b和1002c，并且从那里传导到衬底中的吸热器。
本发明不仅应用于场效应晶体管，而且应用于其他合适功率晶体管。进一步地，通过使第二夹片的顶部表面未包封，使得第二夹片可以优选通过焊接连接到吸热器，以此可以进一步延伸电源模块的高电流容量，并且进一步提高效率。在该配置中，模块可以将它的热量从两个表面散发到吸热器。
本领域技术人员认识到，可以在不背离所要求发明的保护范围的情况下，对已描述实施例做出许多其他修改，而且许多其他实施例是可能的。

Claims (14)

1.一种集成电路封装件即IC封装件，所述IC封装件包含：
引脚框架，所述引脚框架包括管芯焊盘和多个引脚，其中所述管芯焊盘包括凹坑；
所述凹坑中的第一管芯，所述第一管芯包括第一源极和第一漏极，所述第一漏极在所述管芯焊盘上；
所述第一源极上的第一夹片，所述第一夹片将所述第一源极连接到所述多个引脚中的第一引线；
包括第二源极和第二漏极的第二管芯，所述第二漏极在所述第一夹片上并且所述第二漏极连接到所述第一引脚；以及
所述第二源极上的第二夹片，所述第二夹片将所述第二源极连接到所述多个引脚的第二引脚。
2.根据权利要求1所述的IC封装件，其中所述第一管芯是控制场效应晶体管即FET管芯并且所述第二管芯是同步FET管芯。
3.根据权利要求1所述的IC封装件，其中所述第一管芯的物理面积比所述第二管芯的物理面积小。
4.根据权利要求1所述的IC封装件，其中所述第二引脚电连接到接地电压。
5.根据权利要求1所述的IC封装件，其中所述管芯焊盘电连接到输入电压。
6.根据权利要求1所述的IC封装件，其中所述凹坑是矩形凹坑。
7.根据权利要求1所述的IC封装件，进一步包括覆盖所述引脚框架、第一管芯、第二管芯、第一夹片和所述第二夹片的部分的封装化合物。
8.根据权利要求1所述的IC封装件，其中第一管芯包括第一栅极并且所述第二管芯包括第二栅极，所述第一栅极和所述第二栅极电连接到所述多个引脚中的两个引脚。
9.根据权利要求1所述的IC封装件，其中所述第二夹片包括背脊件。
10.根据权利要求1所述的IC封装件，其中所述IC封装件是四方扁平无引脚封装件。
11.根据权利要求1所述的IC封装件，其中从所述IC封装件暴露所述管芯焊盘的一个侧面。
12.根据权利要求1所述的IC封装件，其中所述第一夹片和所述第二夹片是金属的。
13.根据权利要求1所述的IC封装件，其中从所述IC封装件暴露所述第二夹片的一个侧面并且所述第二夹片的一个侧面连接到吸热器。
14.根据权利要求1所述的IC封装件，其中所述IC封装件的厚度小于1.5毫米。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
US8981748B2 (en) * 2011-08-08 2015-03-17 Semiconductor Components Industries, Llc Method of forming a semiconductor power switching device, structure therefor, and power converter
US9589872B2 (en) * 2012-03-28 2017-03-07 Infineon Technologies Americas Corp. Integrated dual power converter package having internal driver IC
US9171784B2 (en) * 2012-03-28 2015-10-27 International Rectifier Corporation Dual power converter package using external driver IC
US20140063744A1 (en) * 2012-09-05 2014-03-06 Texas Instruments Incorporated Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance
JP5966921B2 (ja) * 2012-12-28 2016-08-10 トヨタ自動車株式会社 半導体モジュールの製造方法
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
US9214415B2 (en) 2013-04-11 2015-12-15 Texas Instruments Incorporated Integrating multi-output power converters having vertically stacked semiconductor chips
US9171828B2 (en) * 2014-02-05 2015-10-27 Texas Instruments Incorporated DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
US9355942B2 (en) * 2014-05-15 2016-05-31 Texas Instruments Incorporated Gang clips having distributed-function tie bars
US9515014B2 (en) 2014-10-08 2016-12-06 Infineon Technologies Americas Corp. Power converter package with integrated output inductor
US10103140B2 (en) * 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US11309273B2 (en) 2017-05-19 2022-04-19 Shindengen Electric Manufacturing Co., Ltd. Electronic module
WO2018211680A1 (ja) * 2017-05-19 2018-11-22 新電元工業株式会社 電子モジュール
JP6952042B2 (ja) * 2017-05-19 2021-10-20 新電元工業株式会社 電子モジュール
EP3703119B1 (en) * 2017-10-26 2022-06-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
DE102018207308B4 (de) * 2018-05-09 2020-07-02 Infineon Technologies Ag Halbleiterbauteil mit integriertem shunt-widerstand und verfahren zu dessen herstellung
US20200194347A1 (en) * 2018-12-18 2020-06-18 Alpha And Omega Semiconductor (Cayman) Ltd. Semiconductor package and method of making the same
US11658410B2 (en) 2019-03-12 2023-05-23 Epirus, Inc. Apparatus and method for synchronizing power circuits with coherent RF signals to form a steered composite RF signal
US11211703B2 (en) 2019-03-12 2021-12-28 Epirus, Inc. Systems and methods for dynamic biasing of microwave amplifier
US11616295B2 (en) 2019-03-12 2023-03-28 Epirus, Inc. Systems and methods for adaptive generation of high power electromagnetic radiation and their applications
US12068618B2 (en) 2021-07-01 2024-08-20 Epirus, Inc. Systems and methods for compact directed energy systems
US12003223B2 (en) 2020-06-22 2024-06-04 Epirus, Inc. Systems and methods for modular power amplifiers
US11469722B2 (en) 2020-06-22 2022-10-11 Epirus, Inc. Systems and methods for modular power amplifiers
US20220020671A1 (en) * 2020-07-20 2022-01-20 Electronics And Telecommunications Research Institute Flip-stack type semiconductor package and method of manufacturing the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421262B1 (en) * 2000-02-08 2002-07-16 Vlt Corporation Active rectifier
CN1649146A (zh) * 2004-01-28 2005-08-03 株式会社瑞萨科技 半导体器件
CN1677666A (zh) * 2004-03-31 2005-10-05 株式会社瑞萨科技 半导体器件
CN101140926A (zh) * 2006-09-07 2008-03-12 万国半导体股份有限公司 层迭式双金属氧化物半导体场效应晶体管包
CN101442035A (zh) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
US20100090668A1 (en) * 2008-10-13 2010-04-15 Girdhar Dev A Stacked Field Effect Transistor Configurations
CN101819955A (zh) * 2004-12-20 2010-09-01 半导体元件工业有限责任公司 具有增强散热性的半导体封装结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7598603B2 (en) * 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
US7569920B2 (en) * 2006-05-10 2009-08-04 Infineon Technologies Ag Electronic component having at least one vertical semiconductor power transistor
DE102006034679A1 (de) * 2006-07-24 2008-01-31 Infineon Technologies Ag Halbleitermodul mit Leistungshalbleiterchip und passiven Bauelement sowie Verfahren zur Herstellung desselben
DE102007009521B4 (de) * 2007-02-27 2011-12-15 Infineon Technologies Ag Bauteil und Verfahren zu dessen Herstellung
US7683477B2 (en) * 2007-06-26 2010-03-23 Infineon Technologies Ag Semiconductor device including semiconductor chips having contact elements
US7750445B2 (en) * 2007-09-18 2010-07-06 Fairchild Semiconductor Corporation Stacked synchronous buck converter
US8035221B2 (en) * 2007-11-08 2011-10-11 Intersil Americas, Inc. Clip mount for integrated circuit leadframes
US7696612B2 (en) * 2008-01-28 2010-04-13 Fairchild Semiconductor Corporation Multiphase synchronous buck converter
US8492883B2 (en) * 2008-03-14 2013-07-23 Advanced Semiconductor Engineering, Inc. Semiconductor package having a cavity structure
US20100171543A1 (en) * 2009-01-08 2010-07-08 Ciclon Semiconductor Device Corp. Packaged power switching device
US8680627B2 (en) * 2011-01-14 2014-03-25 International Rectifier Corporation Stacked half-bridge package with a common conductive clip

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421262B1 (en) * 2000-02-08 2002-07-16 Vlt Corporation Active rectifier
CN1649146A (zh) * 2004-01-28 2005-08-03 株式会社瑞萨科技 半导体器件
CN1677666A (zh) * 2004-03-31 2005-10-05 株式会社瑞萨科技 半导体器件
CN101819955A (zh) * 2004-12-20 2010-09-01 半导体元件工业有限责任公司 具有增强散热性的半导体封装结构
CN101140926A (zh) * 2006-09-07 2008-03-12 万国半导体股份有限公司 层迭式双金属氧化物半导体场效应晶体管包
US20100090668A1 (en) * 2008-10-13 2010-04-15 Girdhar Dev A Stacked Field Effect Transistor Configurations
CN101442035A (zh) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法

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