CN108962876B - Pop结构及其形成方法 - Google Patents

Pop结构及其形成方法 Download PDF

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CN108962876B
CN108962876B CN201810603222.0A CN201810603222A CN108962876B CN 108962876 B CN108962876 B CN 108962876B CN 201810603222 A CN201810603222 A CN 201810603222A CN 108962876 B CN108962876 B CN 108962876B
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molding material
die
redistribution structure
package
device die
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CN108962876A (zh
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陈旭贤
陈志华
叶恩祥
吕孟升
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

POP结构及其形成方法。一种器件包括与底部封装件接合的顶部封装件。底部封装件包括模塑材料;在模塑材料中模制的器件管芯;穿透模塑材料的组件通孔(TAV);以及位于器件管芯上方的再分配线。顶部封装件包括封装在其中的分立无源器件。分立无源器件与再分配线电连接。

Description

POP结构及其形成方法
本申请是于2013年05月06日提交的申请号为201310162895.4的名称为“POP结构及其形成方法”的发明专利申请的分案申请。
技术领域
本发明涉及POP结构及其形成方法。
背景技术
在集成电路应用中,越来越多的功能被集成到产品中。例如,可能需要将诸如3G视频元件、WiFi元件、蓝牙元件以及音频/视频元件的不同功能元件集成到一起来形成应用。
在传统的集成方案中,将不同的部件接合至中介层,该中介层进一步接合至封装衬底。例如,在移动应用中,可以使用这种方案接合电源管理集成电路芯片、收发器芯片以及多层陶瓷电容器。所得到的封装件在面积上通常很厚且很大。此外,由于与中介层接合的各种部件通过许多电气连接与中介层连接,因此中介层的电气连接的间距需要非常小,并且有时小至约40nm至50nm。如此小的间距要求中介层使用微凸块(u-凸块),微凸块的形成仍然面临着技术挑战。
发明内容
为了解决现有技术中存在的问题,根据本发明的一方面,提供了一种器件,包括:底部封装件,所述底部封装件包括:模塑材料;在所述模塑材料中模制的第一器件管芯;穿透所述模塑材料的组件通孔(TAV);和位于所述模塑材料上方的第一再分配线;以及顶部封装件,所述顶部封装件包括封装在所述顶部封装件中的分立无源器件,其中所述顶部封装件位于所述底部封装件上方并且与所述底部封装件接合,并且所述分立无源器件与所述再分配线电连接。
在所述的器件中,所述分立无源器件是分立电容器。
所述的器件进一步包括:在所述模塑材料中模制的第二器件管芯,其中所述第一器件管芯和所述第二器件管芯彼此齐平。在一个实施例中,所述第一器件管芯包括第一电连接件,所述第二器件管芯包括第二电连接件,并且所述第一电连接件的端部和所述第二电连接件的端部与所述模塑材料的表面齐平。在另一个实施例中,所述第一器件管芯和所述第二器件管芯选自基本上由电源管理集成电路(PMIC)管芯、收发器(TRX)管芯和基带管芯所组成的组。
所述的器件进一步包括:位于所述模塑材料的与所述第一再分配线相反的面上的第二再分配线,其中所述第二再分配线通过所述TAV与所述第一再分配线电连接。
所述的器件进一步包括:包含在所述顶部封装件中的另一器件管芯,其中所述另一器件管芯与所述底部封装件接合;以及位于所述模塑材料中并且与所述另一器件管芯电连接的另一TAV。
根据本发明的另一方面,提供了一种器件,包括:底部封装件,所述底部封装件包括:模塑材料;在所述模塑材料中模制的第一器件管芯;在所述模塑材料中模制的第二器件管芯,其中所述第一器件管芯和所述第二器件管芯的电连接件的端部与所述模塑材料的表面齐平;穿透所述模塑材料的多个组件通孔(TAV),其中所述第一器件管芯和所述第二器件管芯的电连接件的端部与所述多个TAV的端部齐平;位于所述模塑材料的第一面上的第一再分配层,其中所述第一再分配层包括多条第一再分配线;和位于所述模塑材料的与所述第一面相反的第二面上的第二再分配层,其中所述第二再分配层包括多条第二再分配线;以及位于所述底部封装件上方的顶部封装件,其中所述顶部封装件包括封装在所述顶部封装件中的分立电容器,并且所述分立电容器与所述底部封装件接合。
在所述的器件中,所述顶部封装件进一步包括与所述底部封装件接合的第三器件管芯。
在所述的器件中,所述顶部封装件进一步包括另一模塑材料,并且所述分立电容器在所述另一模塑材料中模制。在一个实施例中,所述另一模塑材料与所述底部封装件接触。
在所述的器件中,所述分立电容器是多层陶瓷电容器(MLCC)。
在所述的器件中,所述第一器件管芯和所述第二器件管芯的电连接件的端部与所述模塑材料的底面齐平。
在所述的器件中,所述第一器件管芯是电源管理集成电路(PMIC)管芯,而所述第二器件管芯是收发器(TRX)管芯。
根据本发明的又一方面,提供了一种方法,包括:形成底部封装件,形成底部封装件的步骤包括:在载具上方放置第一器件管芯和第二器件管芯;在所述载具上方形成多个组件通孔(TAV);在模塑材料中模制所述第一器件管芯、所述第二器件管芯和所述多个TAV;减薄所述模塑材料,其中在所述减薄的步骤之后,通过所述模塑材料暴露出所述多个TAV的顶端以及所述第一器件管芯和所述第二器件管芯的电连接件的顶端;和在所述模塑材料的第一面上形成多条第一再分配线(RDL),其中所述多条第一RDL与所述多个TAV电连接;以及形成顶部封装件,形成顶部封装件的步骤包括:将分立无源器件接合至所述底部封装件。
在所述的方法中,形成所述顶部封装件的步骤进一步包括将第三器件管芯接合至所述底部封装件。
所述的方法进一步包括:在所述模塑材料中模制所述分立无源器件。在一个实施例中,在将所述分立无源器件接合至所述底部封装件的步骤之后,执行模制所述分立无源器件的步骤。
所述的方法进一步包括:实施管芯切割以将所述顶部封装件和所述底部封装件与其他封装件分开。
所述的方法进一步包括:在所述模塑材料的第二面上形成多条第二RDL,其中所述多条第二RDL通过所述多个TAV与所述多条第一RDL电连接。
附图说明
为更充分地理解本实施例及其优点,现在将结合附图所作的如下描述作为参考,其中:
图1至图10是根据一些示例性实施例处于制造堆叠封装(POP)结构的中间阶段的截面图,其中在POP封装件中嵌有器件管芯。
具体实施方式
在下面详细讨论本发明实施例的制造和使用。然而,应该理解,实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅是示例性的,而不用于限制本发明的范围。
根据各个示例性实施例提供了堆叠封装(POP)结构及其形成方法。示出了形成封装结构的中间阶段。论述了实施例的变化。在所有各个附图和示例性实施例中,相同的编号用于表示相同的元件。
图1至图10是根据一些示例性实施例处于制造POP结构的中间阶段的截面图。图1示出载具20以及位于载具20上的粘着层22。载具20可以是玻璃载具、陶瓷载具等。粘着层22可以由诸如紫外线(UV)胶的粘着剂形成。
图2示出器件管芯24和25的放置以及导电柱28的形成。例如通过粘着层22在载具20上方放置器件管芯24和25,并且使其彼此齐平。器件管芯24和25可以是其中包括逻辑晶体管的逻辑器件管芯。例如,在一些示例性实施例中,器件管芯24和25是设计用于移动应用的管芯并且可以包括电源管理集成电路(PMIC)管芯和收发器(TRX)管芯。尽管示出两个管芯24和25,但是在载具20的上方可以放置更多的管芯并且使其彼此齐平。
在整个说明书中,导电柱28被可选地称为组件通孔(Through AssemblyVia,TAV)28。在一些实施例中,预先形成TAV 28,然后将其放置在粘着层22上。在可选的实施例中,TAV 28可以通过镀法形成。可以在放置管芯24和25之前实施镀TAV 28,并且镀TAV 28可以包括在载具20上方形成晶种层(未示出),形成并且图案化光刻胶(未示出),以及在通过光刻胶暴露的晶种层部分上镀TAV 28。然后可以去除光刻胶和被光刻胶覆盖的晶种层部分。然后可以将器件管芯24和25放置在载具20上方。TAV28的材料可以包括铜、铝等。在图2中的所得到的结构中,TAV 28的底端与器件管芯24和25的底面基本上齐平。
在一些示例性实施例中,金属柱26(诸如铜柱)形成为器件管芯24和25的顶部并且与器件管芯24和25中的器件电连接。在一些实施例中,介电层27形成在器件管芯24和25的顶面,其中金属柱26的至少下部位于介电层27中。介电层27的顶面还可以与金属柱26的顶端基本上齐平。可选地,不形成介电层27,并且金属柱26在器件管芯24和25的剩余部分的上方伸出。
参考图3,在器件管芯24和25以及TAV 28上模制模塑材料40。模塑材料40填充器件管芯24和25以及TAV 28之间的间隙并且可以与粘着层22接触。而且,模塑材料40可以填充到金属柱26之间的间隙中。模塑材料40可以包括模塑料、模塑底部填充物、环氧树脂或者树脂。模塑材料40的顶面高于金属柱26和TAV 28的顶端。接下来,实施减薄步骤(其可以是研磨步骤)以减薄模塑材料40直至暴露出金属柱26和TAV 28。所得到的结构在图4中示出。由于减薄步骤,TAV 28的顶端28A与金属柱26的顶端26A基本上齐平并且与模塑材料40的顶面40A基本上齐平。
接下来,参考图5,在模塑材料40上方形成再分配线(RDL)42用于连接金属柱26和TAV 28。RDL 42还可以互连金属柱26和TAV 28。RDL形成在介电层44中。在一些实施例中,通过沉积金属层、图案化金属层并且用介电层44填充RDL 42之间的间隙形成RDL 42。在可选的实施例中,使用镶嵌工艺形成RDL 42和介电层44。RDL 42可以包含金属或者金属合金,包括铝、铜、钨和/或它们的合金。
图5还示出根据一些示例性实施例的电连接件46的形成。连接件46的形成可以包括在RDL 42的暴露部分上放置焊料球,然后回流焊料球。在可选的实施例中,连接件46的形成包括执行镀层步骤以在RDL 42上方形成焊料区,然后回流焊料区。连接件46还可以包括金属柱或者金属柱和焊料盖顶(solder cap),其也可以通过镀法形成。在整个说明书中,包括器件管芯24和25、TAV 28、模塑材料40以及上覆的RDL 42和介电层44的组合结构被称为封装件48,其在该步骤中可以具有晶圆形式。在可选的实施例中,不是在该制造阶段形成电连接件46,而是在封装部件58和60接合之后形成电连接件46,该接合步骤在图9中示出。
参考图6,实施载具交换(carrier switch)。在载具交换工艺中,首先将载具49接合至封装件48,其中载具20和49位于封装件48的相反面上。可以通过粘着剂50将载具49接合至封装件48,粘着剂50可以是UV胶、胶带等。然后通过使粘着层22失去粘着性将载具20从封装件48卸离。然后去除粘着层22。例如,当粘着层22由UV胶形成时,可以将粘着层22暴露于UV光,从而使得粘着层22失去粘着性,并因此可以从封装件48去除载具20和粘着层22。
参考图7,在载具交换之后,暴露出TAV 28的后端28B。在示出的结构中,TAV 28的后端28B与器件管芯24的背面24A和器件管芯25的背面25A齐平。TAV 28的后端28B还可以与模塑材料40的表面40B基本上齐平。在一些实施例中,实施研磨以轻微地研磨器件管芯24和25以及TAV28的背面。作为研磨的结果,TAV 28可以在器件管芯24和25的背面上方略微伸出,或者使TAV 28的端部28B与表面40B、24A和25A齐平。可选地,可以省略研磨步骤。
如图8所示,形成介电层52和RDL 54。在一些实施例中,介电层52由诸如氧化物、氮化物、碳化物、碳氮化物、它们的组合和/或它们的多层的介电材料形成。RDL 54形成在介电层52中并且与TAV 28连接。一些RDL 54可以在器件管芯24和25上方延伸并且与器件管芯24和25对准。因此,RDL 54具有扇入结构。例如,可以将RDL 54的位于器件管芯24和25上方并且与器件管芯24和25对准的部分与RDL 54的位于TAV 28上方并且与TAV 28对准的部分连接。
图9示出封装部件58和60与封装件48的接合。封装部件58和60可以是封装件、器件管芯和/或无源器件等。在一些示例性实施例中,封装部件58是器件管芯,而封装部件60是分立无源器件,其并没有与诸如晶体管的有源器件集成在相同的芯片上。例如,当相应的封装件用于移动应用时,封装部件58可以是基带管芯,而封装部件60是多层陶瓷电容器(MLCC)。例如,可以使用倒装芯片接合通过连接件62来实施接合,其中连接件62可以包含焊料。应该理解,可以将器件管芯24、25和58布置成不同于所示出的示例性实施例。例如,PMIC管芯或者TRX管芯可以是器件管芯58,而基带管芯可以是器件管芯24和25中的一种。
在封装部件58和60接合之后,例如在模塑材料64中模制封装部件58和60。模塑材料64可以与底部封装件48接触。所得到的封装部件58和60与模塑料64因而形成顶部封装件66,其接合至下方的底部封装件48。因此,所得到的结构是POP结构。接下来,从载具49卸下顶部封装件66和底部封装件48。所得到的结构在图10中示出。然后可以将晶圆级封装件48切割成多个POP结构68,其中每一个POP结构68包括与一个底部封装件48接合的一个顶部封装件66。
在这些实施例中,将多个器件管芯连同TAV 28一起嵌入到底部封装件48中。嵌入式底部封装件48的厚度小于典型的封装衬底的厚度,并且小于中介层和封装衬底的合并厚度。因此,与其中器件管芯和封装部件接合至中介层,该中介层进一步接合在封装衬底上的传统结构相比,所得到的POP结构68具有减小的厚度。而且,将器件管芯24和25与封装部件58和60(图10)堆叠起来,而不是接合在同一中介层上(如在传统的结构中)。因此,与传统结构相比,器件管芯24和25以及封装部件58和60占据的总面积减小。
根据实施例,一种器件包括与底部封装件接合的顶部封装件。底部封装件包括模塑材料;在模塑材料中模制的器件管芯;穿透模塑材料的TAV;以及位于器件管芯上方的再分配线。顶部封装件包括封装在其中的分立无源器件。分立无源器件与再分配线电连接。
根据其他实施例,一种器件包括顶部封装件和底部封装件。底部封装件包括模塑材料;在模塑材料中模制的第一器件管芯;以及在模塑材料中模制的第二器件管芯。第一和第二器件管芯的电连接件的端部与模塑材料的表面齐平。底部封装件进一步包括穿透模塑材料的多个TAV,其中第一和第二器件管芯的电连接件的端部与多个TAV的端部齐平。底部封装件进一步包括位于模塑材料的第一面上的第一再分配层,其中第一再分配层包括多条第一再分配线,以及位于模塑材料的与第一面相反的第二面上的第二再分配层,其中第二再分配层包括多条第二再分配线。顶部封装件包括封装在其中的分立电容器,其中分立电容器与底部封装件接合。
根据又一些实施例,一种方法包括形成底部封装件,其包括在载具上方放置第一器件管芯和第二器件管芯;在载具上方形成多个TAV;在模塑材料中模制第一器件管芯、第二器件管芯和多个TAV;以及减薄模塑材料。在减薄步骤之后,通过模塑材料暴露出多个TAV的顶端以及第一器件管芯和第二器件管芯的电连接件的顶端。底部封装件的形成进一步包括在模塑材料的一面上形成多条RDL,其中多条RDL与多个TAV电连接。该方法进一步包括形成顶部封装件,其包括将分立无源器件接合至底部封装件。
尽管已经详细地描述了实施例及其优势,但应该理解,可以在不背离所附权利要求限定的实施例的构思和范围的情况下,进行各种改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解,根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。

Claims (17)

1.一种半导体器件,包括:
底部封装件,包括:
模塑材料;
在所述模塑材料中模制的第一器件管芯,其中,所述第一器件管芯包括第一电连接件,
介电层,形成在所述第一器件管芯上方,其中,至少所述第一电连接件的下部位于所述介电层中,所述模塑材料设置在所述第一电连接件的突出于所述介电层的部分之间的间隙中;
穿透所述模塑材料的组件通孔(TAV),其中,所述组件通孔的顶端突出于所述模塑材料的顶面;和
位于所述模塑材料上方的第一再分配结构,其中,通过所述第一再分配结构将所述组件通孔与所述第一器件管芯电连接,所述第一再分配结构包括彼此堆叠和接触形成的多个水平介电层以及形成在所述多个水平介电层的每个介电层中的金属线;以及
顶部封装件,包括封装在所述顶部封装件中的分立无源器件和电连接至所述分立无源器件的外部电连接件,其中所述顶部封装件位于所述底部封装件上方并且与所述底部封装件接合,并且所述外部电连接件与所述第一再分配结构直接电连接。
2.根据权利要求1所述的器件,其中,所述分立无源器件是分立电容器。
3.根据权利要求1所述的器件,进一步包括:在所述模塑材料中模制的第二器件管芯,其中所述第一器件管芯和所述第二器件管芯彼此齐平。
4.根据权利要求3所述的器件,其中,所述第一器件管芯包括第一金属柱,所述第二器件管芯包括第二金属柱,并且所述第一金属柱的端部和所述第二金属柱的端部与所述模塑材料的表面齐平。
5.根据权利要求3所述的器件,其中,所述第一器件管芯和所述第二器件管芯选自基本上由电源管理集成电路(PMIC)管芯、收发器(TRX)管芯和基带管芯所组成的组。
6.根据权利要求1所述的器件,进一步包括:位于所述模塑材料的与所述第一再分配结构相反的面上的第二再分配结构,其中所述第二再分配结构通过所述组件通孔与所述第一再分配结构电连接。
7.根据权利要求1所述的器件,进一步包括:
包含在所述顶部封装件中的另一器件管芯,其中所述另一器件管芯通过焊料区与所述底部封装件接合,所述焊料区位于所述第一再分配结构的上方;以及
位于所述模塑材料中并且与所述另一器件管芯电连接的另一组件通孔。
8.根据权利要求1所述的器件,其中,所述第一电连接件的底面与所述模塑材料的底面共面。
9.根据权利要求1所述的器件,其中,所述第一电连接件包括竖直边缘。
10.根据权利要求1所述的器件,其中,所述分立无源器件位于所述第一再分配结构上方并且与所述第一再分配结构通过焊料接缝接合,并且其中所述器件还包括位于所述焊料接缝之间的另一模塑材料。
11.一种半导体器件,包括:
底部封装件,包括:
模塑材料;
在所述模塑材料中模制的第一器件管芯;
穿透所述模塑材料的组件通孔(TAV),其中,所述组件通孔的顶端突出于所述模塑材料的顶面;和
位于所述模塑材料下方的第一再分配结构,其中,通过所述第一再分配结构将所述组件通孔与所述第一器件管芯电连接,所述第一再分配结构包括彼此堆叠和接触形成的在水平方向上延伸的第一多个水平介电层以及形成在所述第一多个水平介电层的每个介电层中的金属互连件;以及
顶部封装件,位于所述底部封装件上方并且与所述底部封装件接合,其中所述顶部封装件包括:
另一电器件,电连接至所述第一再分配结构;
外部电连接件,电连接至所述另一电器件;和
另一模塑料,在所述另一模塑料中模制所述另一电器件和所述外部电连接件,其中,所述外部电连接件与位于所述模塑材料上方的第二再分配结构直接接触,所述第二再分配结构包括堆叠形成的第二多个介电层以及形成在所述第二多个介电层的每个介电层中的金属互连件。
12.根据权利要求11所述的器件,其中,所述另一电器件为分立无源器件。
13.根据权利要求11所述的器件,进一步包括:在所述模塑材料中模制的第二器件管芯,其中所述第一器件管芯和所述第二器件管芯彼此齐平。
14.根据权利要求11所述的器件,其中,所述第一器件管芯包括金属柱,并且其中,所述模塑材料设置在所述金属柱之间的间隙中。
15.根据权利要求14所述的器件,其中,所述金属柱的底面与所述模塑材料的底面共面。
16.根据权利要求11所述的器件,其中,所述另一电器件为另一器件管芯,并且其中,所述另一器件管芯通过所述外部电连接件接合所述第二再分配结构。
17.根据权利要求11所述的器件,其中,所述另一电器件位于所述第二再分配结构上方,并且其中,所述外部电连接件包括位于所述另一电器件和所述第二再分配结构之间并且与二者电互连的焊球。
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Families Citing this family (160)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8832283B1 (en) 2010-09-16 2014-09-09 Google Inc. Content provided DNS resolution validation and use
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9941229B2 (en) 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI517343B (zh) * 2014-03-25 2016-01-11 恆勁科技股份有限公司 覆晶堆疊封裝結構及其製作方法
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9754918B2 (en) 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9831214B2 (en) 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9847317B2 (en) * 2014-07-08 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
CN104157619B (zh) * 2014-08-22 2016-09-28 山东华芯半导体有限公司 一种新型PoP堆叠封装结构及其制造方法
US20160095221A1 (en) * 2014-09-27 2016-03-31 Qualcomm Incorporated Integration of electronic elements on the backside of a semiconductor die
US9190367B1 (en) * 2014-10-22 2015-11-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US9420695B2 (en) 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US20160172274A1 (en) * 2014-12-16 2016-06-16 Qualcomm Incorporated System, apparatus, and method for semiconductor package grounds
TWI559488B (zh) * 2014-12-27 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
US20160240457A1 (en) * 2015-02-18 2016-08-18 Altera Corporation Integrated circuit packages with dual-sided stacking structure
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
CN106057786B (zh) * 2015-04-13 2018-11-30 台湾积体电路制造股份有限公司 3d堆叠式芯片封装件
US9553001B2 (en) * 2015-04-28 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a molding layer for semiconductor package
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9627288B2 (en) * 2015-05-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
CN107924899B (zh) * 2015-08-27 2023-05-02 英特尔公司 多管芯封装
US9881850B2 (en) * 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10636773B2 (en) * 2015-09-23 2020-04-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US9704825B2 (en) * 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
CN105261611B (zh) * 2015-10-15 2018-06-26 矽力杰半导体技术(杭州)有限公司 芯片的叠层封装结构及叠层封装方法
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US9837378B2 (en) * 2015-10-23 2017-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Fan-out 3D IC integration structure without substrate and method of making the same
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10483250B2 (en) * 2015-11-04 2019-11-19 Intel Corporation Three-dimensional small form factor system in package architecture
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
CN106876358A (zh) * 2015-12-11 2017-06-20 安世有限公司 电子元件及其制造方法
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9589941B1 (en) * 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US10665579B2 (en) * 2016-02-16 2020-05-26 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
CN107154385A (zh) * 2016-03-04 2017-09-12 讯芯电子科技(中山)有限公司 堆叠封装结构及其制造方法
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
US10777486B2 (en) 2016-03-25 2020-09-15 Intel Corporation Substrate-free system in package design
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
DE102016110862B4 (de) * 2016-06-14 2022-06-30 Snaptrack, Inc. Modul und Verfahren zur Herstellung einer Vielzahl von Modulen
US10109617B2 (en) 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10312193B2 (en) * 2016-08-12 2019-06-04 Qualcomm Incorporated Package comprising switches and filters
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US20180076179A1 (en) * 2016-09-09 2018-03-15 Powertech Technology Inc. Stacked type chip package structure and manufacturing method thereof
US10276548B2 (en) 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US9859245B1 (en) * 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
WO2018063263A1 (en) * 2016-09-29 2018-04-05 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US20180102298A1 (en) * 2016-10-06 2018-04-12 Mediatek Inc. Semiconductor device
US10529666B2 (en) * 2016-11-29 2020-01-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10002852B1 (en) 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US9978731B1 (en) 2016-12-28 2018-05-22 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package module
WO2018125242A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Microelectronic devices designed with 3d stacked ultra thin package modules for high frequency communications
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US10319683B2 (en) 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
TWI653725B (zh) * 2017-02-08 2019-03-11 南茂科技股份有限公司 指紋辨識封裝結構
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10475718B2 (en) * 2017-05-18 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package comprising a dielectric layer with built-in inductor
US20180350708A1 (en) * 2017-06-06 2018-12-06 Powertech Technology Inc. Package structure and manufacturing method thereof
US10943869B2 (en) 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10541228B2 (en) * 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10886263B2 (en) * 2017-09-29 2021-01-05 Advanced Semiconductor Engineering, Inc. Stacked semiconductor package assemblies including double sided redistribution layers
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
CN108063095A (zh) * 2017-12-15 2018-05-22 路军 一种智能融合传感器芯片的封装方法
SG11202004563VA (en) * 2017-12-29 2020-07-29 Intel Corp Patch accomodating embedded dies having different thicknesses
US11430724B2 (en) * 2017-12-30 2022-08-30 Intel Corporation Ultra-thin, hyper-density semiconductor packages
US10388631B1 (en) * 2018-01-29 2019-08-20 Globalfoundries Inc. 3D IC package with RDL interposer and related method
US10510650B2 (en) * 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
KR102491103B1 (ko) 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102395199B1 (ko) 2018-02-22 2022-05-06 삼성전자주식회사 반도체 패키지
US10699980B2 (en) 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10515929B2 (en) 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
CN109300863A (zh) * 2018-09-28 2019-02-01 中国科学院微电子研究所 半导体封装结构以及半导体封装方法
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
KR102513085B1 (ko) * 2018-11-20 2023-03-23 삼성전자주식회사 팬-아웃 반도체 패키지
TWI728561B (zh) * 2018-11-29 2021-05-21 台灣積體電路製造股份有限公司 半導體封裝件以及其製造方法
US11282761B2 (en) 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US20200211968A1 (en) * 2018-12-27 2020-07-02 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN109786271A (zh) * 2018-12-29 2019-05-21 华进半导体封装先导技术研发中心有限公司 一种三维堆叠封装方法及结构
CN111415908B (zh) 2019-01-07 2022-02-22 台达电子企业管理(上海)有限公司 电源模块、芯片嵌入式封装模块及制备方法
CN111415909B (zh) 2019-01-07 2022-08-05 台达电子企业管理(上海)有限公司 多芯片封装功率模块
US11676756B2 (en) 2019-01-07 2023-06-13 Delta Electronics (Shanghai) Co., Ltd. Coupled inductor and power supply module
US11316438B2 (en) 2019-01-07 2022-04-26 Delta Eletronics (Shanghai) Co., Ltd. Power supply module and manufacture method for same
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
CN110600440B (zh) * 2019-05-13 2021-12-14 华为技术有限公司 一种埋入式封装结构及其制备方法、终端
US11380620B2 (en) * 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11417619B2 (en) * 2019-08-22 2022-08-16 Taiwan Semiconductor Manufacturing Company Ltd. Package and manufacturing method thereof
WO2021081855A1 (zh) * 2019-10-30 2021-05-06 华为技术有限公司 芯片堆叠封装结构及其封装方法、电子设备
US11362036B2 (en) * 2020-01-06 2022-06-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11812545B2 (en) 2020-01-08 2023-11-07 Delta Electronics (Shanghai) Co., Ltd Power supply system and electronic device
CN113098234B (zh) * 2020-01-08 2022-11-01 台达电子企业管理(上海)有限公司 供电系统
CN113097190B (zh) 2020-01-08 2024-08-13 台达电子企业管理(上海)有限公司 电源模块及电子装置
US11342316B2 (en) 2020-01-16 2022-05-24 Mediatek Inc. Semiconductor package
US11462418B2 (en) * 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
KR20210109179A (ko) 2020-02-27 2021-09-06 삼성전자주식회사 반도체 패키지
US11948877B2 (en) * 2020-03-31 2024-04-02 Qualcomm Incorporated Hybrid package apparatus and method of fabricating
TWI771974B (zh) * 2020-04-03 2022-07-21 韓商Nepes股份有限公司 半導體封裝件
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
KR20220117032A (ko) 2021-02-16 2022-08-23 삼성전자주식회사 반도체 패키지
CN115148712A (zh) * 2021-03-29 2022-10-04 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN112992956B (zh) * 2021-05-17 2022-02-01 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装方法和电子设备
US11854928B2 (en) * 2021-08-27 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
CN114496988A (zh) * 2022-04-19 2022-05-13 宁波德葳智能科技有限公司 脑电波处理系统的再布线封装结构及其制作方法
CN117410261A (zh) * 2022-07-08 2024-01-16 长鑫存储技术有限公司 半导体封装结构及制备方法
CN115632034A (zh) * 2022-12-20 2023-01-20 珠海妙存科技有限公司 eMMC模组封装结构及其制作方法
CN117316907A (zh) * 2023-11-29 2023-12-29 浙江禾芯集成电路有限公司 一种晶圆级非tsv 3d堆叠封装结构及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200976345Y (zh) * 2006-11-24 2007-11-14 威盛电子股份有限公司 芯片封装结构
US20100140779A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming Same
CN101944495A (zh) * 2009-07-01 2011-01-12 卡西欧计算机株式会社 半导体器件的制造方法
TW201230266A (en) * 2010-11-26 2012-07-16 Cambridge Silicon Radio Ltd Multi-chip package

Family Cites Families (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU1040397A (en) 1996-12-04 1998-06-29 Hitachi Limited Semiconductor device
US6281046B1 (en) 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US20040187297A1 (en) 2003-03-27 2004-09-30 E Touch Corporation Method of fabricating a polymer resistor in an interconnection via
US7164197B2 (en) 2003-06-19 2007-01-16 3M Innovative Properties Company Dielectric composite material
TWI260079B (en) 2004-09-01 2006-08-11 Phoenix Prec Technology Corp Micro-electronic package structure and method for fabricating the same
JPWO2006035528A1 (ja) 2004-09-29 2008-05-15 株式会社村田製作所 スタックモジュール及びその製造方法
US7105920B2 (en) 2004-11-12 2006-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design to improve chip package reliability
US7515434B2 (en) 2004-12-20 2009-04-07 Nortel Networks Limited Technique for enhancing circuit density and performance
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US20080006936A1 (en) 2006-07-10 2008-01-10 Shih-Ping Hsu Superfine-circuit semiconductor package structure
US20080017407A1 (en) 2006-07-24 2008-01-24 Ibiden Co., Ltd. Interposer and electronic device using the same
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US8421244B2 (en) 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
US7514797B2 (en) 2007-05-31 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die wafer level packaging
US7659609B2 (en) 2007-08-31 2010-02-09 Stats Chippac Ltd. Integrated circuit package-in-package system with carrier interposer
US8476769B2 (en) 2007-10-17 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias and methods for forming the same
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US7704796B2 (en) 2008-06-04 2010-04-27 Stats Chippac, Ltd. Semiconductor device and method of forming recessed conductive vias in saw streets
US7741151B2 (en) 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
US8344503B2 (en) 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
JP5147678B2 (ja) 2008-12-24 2013-02-20 新光電気工業株式会社 微細配線パッケージの製造方法
US7863100B2 (en) 2009-03-20 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with layered packaging and method of manufacture thereof
WO2011014409A1 (en) 2009-07-30 2011-02-03 Megica Corporation System-in packages
US9230898B2 (en) 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8803332B2 (en) 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8102599B2 (en) 2009-10-21 2012-01-24 International Business Machines Corporation Fabrication of optical filters integrated with injection molded microlenses
KR101099578B1 (ko) 2009-11-03 2011-12-28 앰코 테크놀로지 코리아 주식회사 재배선 및 tsv를 이용한 적층 칩 패키지
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
TWI436463B (zh) 2009-12-31 2014-05-01 Advanced Semiconductor Eng 半導體封裝結構及其製造方法
US8115260B2 (en) 2010-01-06 2012-02-14 Fairchild Semiconductor Corporation Wafer level stack die package
US8138014B2 (en) 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
JP5423874B2 (ja) 2010-03-18 2014-02-19 日本電気株式会社 半導体素子内蔵基板およびその製造方法
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8183696B2 (en) * 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
JP2011233854A (ja) * 2010-04-26 2011-11-17 Nepes Corp ウェハレベル半導体パッケージ及びその製造方法
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8343810B2 (en) 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
KR101695353B1 (ko) 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8619431B2 (en) * 2010-12-22 2013-12-31 ADL Engineering Inc. Three-dimensional system-in-package package-on-package structure
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
KR101236798B1 (ko) 2011-02-16 2013-02-25 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨 적층형 반도체 패키지 제조 방법
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8883561B2 (en) 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8710668B2 (en) 2011-06-17 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with laser hole and method of manufacture thereof
US20120319295A1 (en) 2011-06-17 2012-12-20 Chi Heejo Integrated circuit packaging system with pads and method of manufacture thereof
US8541884B2 (en) 2011-07-06 2013-09-24 Research Triangle Institute Through-substrate via having a strip-shaped through-hole signal conductor
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US8634221B2 (en) 2011-11-01 2014-01-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8928114B2 (en) 2012-01-17 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8723309B2 (en) 2012-06-14 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via and method of manufacture thereof
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8791016B2 (en) 2012-09-25 2014-07-29 International Business Machines Corporation Through silicon via wafer, contacts and design structures
US9209156B2 (en) 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8957525B2 (en) 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200976345Y (zh) * 2006-11-24 2007-11-14 威盛电子股份有限公司 芯片封装结构
US20100140779A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Package with Semiconductor Core Structure and Method of Forming Same
CN101944495A (zh) * 2009-07-01 2011-01-12 卡西欧计算机株式会社 半导体器件的制造方法
TW201230266A (en) * 2010-11-26 2012-07-16 Cambridge Silicon Radio Ltd Multi-chip package

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