CN108886019A - 用于被堆叠的晶粒的纳米级互连阵列 - Google Patents

用于被堆叠的晶粒的纳米级互连阵列 Download PDF

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Publication number
CN108886019A
CN108886019A CN201780023081.9A CN201780023081A CN108886019A CN 108886019 A CN108886019 A CN 108886019A CN 201780023081 A CN201780023081 A CN 201780023081A CN 108886019 A CN108886019 A CN 108886019A
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insulating layer
microelectronic
nanoscale
array
nanoscale conductors
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CN201780023081.9A
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CN108886019B (zh
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王亮
李奉燮
贝尔格森·哈巴
李相日
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Ying Fansasi Co
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Ying Fansasi Co
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Abstract

本发明提供一种微电子组件，其包括：一绝缘层，其具有成一纳米级间距阵列安置于其中的多个纳米级导体；及一对微电子元件。所述纳米级导体可形成所述微电子元件的接点之间的电气互连，而所述绝缘层可以机械方式将所述微电子元件耦接在一起。

Description

用于被堆叠的晶粒的纳米级互连阵列
技术领域
以下描述是关于集成电路。更特定而言，以下描述是关于安置于绝缘层中且将堆叠式IC晶粒电气互连的纳米级导体的阵列。
背景技术
微电子元件常常包含半导体材料的较薄厚块，诸如硅或砷化镓，通常被称为半导体晶片或晶粒。晶粒通常作为个别、预封装的单元被提供。在一些单元设计中，晶粒被安装至基板或晶片载体，基板或晶片载体接着安装于电路面板(诸如印刷电路板(PCB))上。
主动式电路常常制造于晶粒的第一面(例如，前表面)上。为便于电气连接至主动式电路，晶粒在相同面上设置有接合垫。接合垫典型地成规则阵列围绕晶粒的边缘置放，或针对许多记忆体装置经置放于晶粒中心中。接合垫通常由导电金属(诸如铜或铝)制成，且可是约0.5微米(μm)厚。接合垫可包括单层或多层的金属。接合垫的大小可随装置类型变化，但将常常在一侧上量测为数十微米至数百微米。
诸如半导体晶粒的微电子元件典型地需要至其他电子构件的许多输入连接及输出连接。晶粒或其他可比较装置的输入接点及输出接点通常成实质上覆盖晶粒的表面(通常被被称作“区域阵列”)的栅格状图案而安置，或成可平行于且邻近于晶粒的前表面的每一边缘延伸的细长列而安置，或安置于前表面的中心中。晶粒可设置于促进在制造期间及在将晶粒安装于诸如电路板或其他电路面板的外部基板上期间处置晶粒的封装中。举例而言，许多晶粒设置于适合于表面安装的封装中。已为各种应用提议此种通用类型的多个封装。最一般地，此类封装包括介电质元件，通常被称作形成为介电质上的经电镀或经蚀刻金属结构的具有端子的“晶片载体”。藉由导电特征(诸如沿着晶粒载体延伸的薄迹线)及藉由在晶粒的接点与端子或迹线之间延伸的精细引线或导线，端子典型地连接至晶粒的接点(例如，接合垫)。在表面安装操作中，可将封装置放至电路板上，使得封装上的每一端子与电路板上的对应接触垫对准。焊料或其他接合材料设置于端子与接触垫之间。藉由加热组件以便熔化或“回焊”焊料或以其他方式活化接合材料，可将封装永久地接合在适当的位置。
许多封装包括呈直径典型地介于约0.1mm与约0.8mm(5密耳与30密耳)之间且附接到封装的端子的焊球形式的焊料块。具有自封装的底部表面(例如，与晶粒的前表面相对的表面)突出的焊球阵列的封装通常被称作球栅阵列或“BGA”封装。藉由自焊料形成的薄层或端子区域将被称作端子区域格阵列或“LGA”封装的其他封装紧固至基板。此种类型的封装可是非常紧密的。通常被称作“晶片级封装”的某些封装占据等于或仅略大于并入于封装中的装置的面积的电路板的面积。此比例是有利的，此是因为其降低组件的整体大小且准许在基板上的各种装置之间使用短互连件，此随后限制装置之间的信号传播时间且因此便于以在高速操作组件。
封装式半导体晶粒常常以“堆叠式”配置设置，其中一个封装例如设置于电路板或其他载体上，且另一封装安装于第一封装的顶部上。此等配置可允许将多个不同晶粒安装于电路板上的单个占据面积内，且可藉由在封装之间提供短互连件而更便于高速操作。通常，此互连距离可仅略大于晶粒自身的厚度。对于将在晶粒封装的堆叠内达成的互连，用于机械及电气连接的互连结构可设置于每一晶粒封装(最顶封装除外)的两侧(例如，面)上。此已例如藉由在安装有晶粒的基板的两侧上设置接触垫或端子区域来实现，所述垫藉由导电通孔或类似者经过基板连接。堆叠式晶片配置及互连结构的实例是提供于美国专利申请公开案第2010/0232129号中，所述公开案的揭示内容是以引用的方式并入本文中。
对于实施堆叠式晶粒配置可存在多种挑战。举例而言，一致晶粒置放准确性可具有挑战性，包括难以在晶粒之间对准端子。此可在晶粒的互连端子的间距变得愈来愈精细时变得更复杂。
附图说明
参考附图阐述实施方式。在诸图中，参考数字的最左侧数位识别首次出现所述参考数字的图。在不同图中使用同一参考数字指示类似或相同物件。
对此论述，诸图中所说明的装置及系统展示为具有大量构件。如本文中所描述，装置及/或系统的各种实施可包括更少构件且保持在本发明的范围内。替代地，装置及/或系统的其他实施可包括额外构件或所描述构件的各种组合，且保持在本发明的范围内。
图1是根据一实施的在堆叠的邻近晶粒之间具有互连阵列的三维晶粒堆叠的说明。
图2及图3展示根据实例具体实例的用于形成互连阵列的实例处理步骤。
图4是根据实例具体实例的两个实例互连阵列的说明，第一阵列具有由单种材料组成的纳米级导体，且第二阵列具有由多种材料组成的纳米级导体。
图5展示根据一具体实例的形成孔的纳米级阵列的一实例。
图6展示根据一具体实例的用于形成互连阵列的处理步骤的一实例。
图7是根据实例具体实例的纳米级导体的两个实例集合的说明，第一集合自催化剂层生长，且第二集合在纳米级导体上具有涂层以达成所要属性。
图8至图10展示根据实例具体实例的用于形成纳米级导体及互连阵列的实例处理步骤。
图11及图12是说明根据实例实施的用于形成在堆叠的邻近晶粒之间具有互连阵列的三维晶粒堆叠的实例程序的流程图。
具体实施方式
以下配合图式及本实用新型的较佳实施例，进一步阐述本实用新型为达成预定实用新型目的所采取的技术手段。
概述
揭示一种微电子组件，其包含：一绝缘层，其中安置有多个纳米级导体(例如，导电纳米线)；及至少一对微电子元件的一三维堆叠。所述纳米级导体可形成所述堆叠的邻近微电子元件的端子与接点之间的电气互连，而所述绝缘层可以机械方式将邻近微电子元件耦接在一起。
在各种实施中，纳米级导体配置成具有纳米级间距的阵列。精细间距允许纳米级导体与许多不同类型的微电子元件上的具有多种形状、大小、图案及布局的端子接触。因此，纳米级互连阵列可是通用互连层，其可经应用以互连许多不同微电子元件，而不考虑接触图案或互连层与微电子元件的接点之间的小心对准的需要。
本发明的一个态样提供一种微电子组件，其包括具有一第一表面及与所述第一表面相对的一第二表面的一绝缘层，及成一阵列安置于所述绝缘层内的多个纳米级导体。所述多个纳米级导体自所述绝缘层的所述第一表面延伸至所述第二表面，且所述阵列具有一纳米级间距。在一些具体实例中，所述纳米级导体正交于所述绝缘层的所述第一及所述第二表面而配置，或经类似地配置以最小化所述纳米级导体的长度。
所包括的第一微电子元件具有一第一面及所述第一面处的多个第一元件接点，所述第一元件接点面朝所述绝缘层的所述第一表面且在所述绝缘层的所述第一表面处结合至所述多个纳米级导体。所包括的第二微电子元件具有一第二面及所述第二面处的多个第二元件接点，所述第二元件接点面朝所述绝缘层的所述第二表面且在所述绝缘层的所述第二表面处结合至所述多个纳米级导体。在实施中，所述多个纳米级导体形成所述第一微电子元件的第一元件接点与所述第二微电子元件的第二元件接点之间的电气互连。
在一具体实例中，所述绝缘层包含以机械方式将所述第一微电子元件耦接至所述第二微电子元件的一黏合性聚合物，而所述多个纳米级导体将所述第一微电子元件的元件接点电气耦接至所述第二微电子元件的元件接点。
在另一具体实例中，在堆叠中存在多于两个微电子元件。上述绝缘层是一第一绝缘层，且所述微电子组件进一步包含一第二绝缘层，所述第二绝缘层自与所述第二面相对的一面处的所述第二微电子元件延伸至一第三微电子元件的一第三面。在所述具体实例中，所述第二绝缘层包括成一纳米级间距阵列安置于所述第二绝缘层内的第二多个纳米级导体，所述第二多个纳米级导体延伸至所述第二面及所述第三面且形成所述第二微电子元件的元件接点与所述第三微电子元件的元件接点之间的电气互连。
在一些实施中，纳米级导体由单种导电材料(例如，金、铜、钛、合金、导电碳等)组成。在一个实施中，多个纳米级导体中的每一纳米级导体沿着纳米级导体的长度包含多个区段。多个区段中的邻近区段包含导电材料的不同组成物。举例而言，每一纳米级导体区段可包含不同导电层。在各种实例中，纳米级导体的区段可由铜、金、镍、焊料、锡、铟、其合金或各种其他导电材料或组成物组成。
参考电气及电子构件及变化的载体来论述各种实施及配置。尽管提及了特定构件(亦即，集成电路(IC)晶片晶粒、晶圆、基板、印刷电路板(PCB)、离散构件等)，但此并不意欲是限制性的，而是为了易于论述及便于说明。所论述的技术及装置适用于任何类型或数目个封装、封装式电路或构件、电路(例如，集成电路(IC)、混合电路、ASIC、记忆体装置、处理器等)、电气构件(例如，感测器、电晶体、二极体等)、构件的群组、载体结构(例如，晶圆、基板、面板、板、PCB等)及类似者。此等构件、电路、晶片、结构及类似物中的每一者可被一般称作“微电子元件”。此外，除非规定，否则对特定构件的参考亦适用于其他类型的微电子元件。
在下文使用多个实例来更详细地解释实施。尽管在此处及下文论述了各种实施及实例，但其他实施及实例可藉由组合个别实施及实例的特征及元件而为可能的。
实例纳米级互连阵列
图1说明根据一实施的实例微电子组件100，其包含微电子元件(例如，晶粒102)的三维堆叠及多个互连阵列104，其中互连阵列104安置于邻近晶粒102之间。每一互连阵列104包括绝缘层内的纳米级间距导体，且提供邻近晶粒102的端子与接点之间的电气互连。在一些具体实例中，晶粒102可在晶粒102的顶侧及底侧上具有互连端子，在晶粒102安置于微电子组件100堆叠的中间中时尤其如此。
在各种实施中，互连阵列104可普遍地(作为统一层)应用于多种晶粒102(或其他微电子元件)，此是因为纳米级导体提供电气连接而不需要邻近晶粒102上的端子与接点极佳地对准，只要端子与接点在各别邻近晶粒102上实质上面朝彼此即可。举例而言，第一对邻近晶粒102可包括与第二对邻近晶粒102不同的接触端子的配置，但安置于所述第一对邻近晶粒102之间的第一互连阵列104与安置于第二对邻近晶粒102之间的第二互连阵列104可具有纳米级导体212的相同实体配置。
图2说明根据一实例具体实例的用于形成互连阵列104的实例处理步骤。绝缘二嵌段共聚物层200(包含两种不同聚合物202及204)形成于例如金属基板206上。在一些实施中，薄层208可形成于金属基板206上，其中二嵌段共聚物层200形成于层208上。薄层208可包含导电层，诸如钛、铬、铝、金或类似者。在一些具体实例中，薄层208提供用于在绝缘层200内生长或形成纳米级导体212的催化剂或晶种层(如下文所描述)。
由于用于层200中的不同聚合物(202、204)，二嵌段共聚物层200藉由自组装形成纳米级矩阵图案。举例而言，在一实施中，聚合物包含聚苯乙烯(202)及聚(甲基丙烯酸甲酯)(PMMA)(204)或类似材料。所形成的纳米级矩阵图案一旦经自组装即在两种聚合物(202、204)之间具有纳米级间隔。由于成本节省，二嵌段共聚物层200的自组装可对于(例如)用于形成纳米级图案的微影术较佳。
自层200移除聚合物中的一者(例如，PMMA 204)，从而显露绝缘层200中的纳米级孔210。各种方法可用以移除聚合物204。在一个实例中，使层200曝露于UV辐射(例如，25J/cm2)，且使聚合物204溶解。可用显影剂或类似化学冲洗来冲洗掉聚合物204。举例而言，在以上实例中，UV曝光使PMMA 204域降解且同时交联聚苯乙烯202基质，使得可藉由用乙酸或类似者进行冲洗来移除经降解PMMA 204，从而留下纳米级孔210(聚苯乙烯202在室温下处于固体(玻璃态)状态下)。
纳米级孔210经导电材料填充或涂布以在孔210中形成纳米级导体212。在各种实施中，可经由自下而上的镀敷、脉冲式电沉积、化学气相沉积(CVD)、无电极电镀(液相或气相)或类似者形成纳米级导体212。替代地，可在溶液中以化学方式生长纳米级导体212(例如，将催化剂或晶种层208或金属基板206用作晶种)。在任一情况下，所得结构是互连阵列层104，其包含绝缘聚合物202内的纳米级导体212的阵列。必要时，可抛光或蚀刻层104的暴露表面以使暴露表面准备好转移至晶粒102。
在一实施中，绝缘聚合物202也是黏合剂，其允许互连阵列层104结合至晶圆或堆叠式晶粒102，从而将互连阵列层104黏附(以机械方式耦接)至晶粒102。在所述实施中，纳米级导体212与结合的晶粒102的面上的端子及连接件接触。在一具体实例中，互连阵列层104是使用薄膜转移或类似制程结合至晶粒102，其中互连阵列层104作为统一单层被转移。在一实施中，藉由剥离、抛光、蚀刻或类似技术自互连阵列层104的相对表面移除金属基板206。必要时，此使相对表面准备好结合至另一晶粒102，从而形成微电子组件100，如图1中所展示。
图3说明根据一具体实例的用于形成互连阵列104的替代性实例处理步骤。如图3中所展示，可在绝缘体或半导体层302(例如，二氧化硅、硅等)上形成二嵌段共聚物层200。二嵌段共聚物层200一旦形成即可转移至金属基板206(例如藉由薄膜转移)，且可移除晶圆302。此时处理步骤遵循如参看图2所描述。
图4是根据实例具体实例的两个实例互连阵列104的说明，第一阵列(展示于(A)处)具有由单种导电材料组成的纳米级导体212，且第二阵列(展示于(B)处)具有由多种导电材料组成的纳米级导体212。在各种实施中，纳米级导体212形成为具有纳米级尺寸且在阵列104中按纳米级间隔(例如，数十至数百纳米的直径及间距)间隔开。在一个实例中，具有90nm的直径及约2μm的长度的纳米级导体212(在室温下)具有6.3×10-8Ω·m的电阻率。在其他实例中，纳米级导体212具有较大或较小电阻率。
如图4中(B)处所展示，纳米级导体212可形成为沿着每一纳米级导体212的长度包括多个区段(402至410)。在各种具体实例中，多个区段(402至410)中的邻近区段可包含不同导电材料。举例而言，每一纳米级导体212可包括包含铜或铜合金的一或多个区段(例如，406)、包含镍或镍合金的一或多个区段(例如，404及408)、包含锡或合金合金的一或多个区段(例如，402及410)等。在一实例中，每一纳米级导体212的末端处的区段(例如，402及410)包含焊料或焊料型材料。此可对于互连无现有焊料倒装晶片组件的间距限制的3D堆叠(例如，组件100)中的邻近晶粒102上的具有极精细间距的接触垫是有利的，此是因为区段已提供纳米线焊料，且在邻近晶粒102上的接触垫处不需要焊料。
图5展示根据一具体实例的使用自组装二嵌段共聚物制程来形成由绝缘聚合物202围绕的孔210的纳米级矩阵阵列的实例。如所展示，在此等实例中达成具有72nm及620nm的间距的自组装矩阵。(在图式的底部附注尺度。)在其他实例中，使用所揭示技术，具有更小或更大间距的自组装矩阵也是可能的。
图6展示根据一具体实例的用于形成互连阵列104的处理步骤的另一实例。在具体实例中，在基板302(其可包含塑料、玻璃、金属等)上形成二嵌段共聚物层200。在一个实施中，将一或多个层(602、604)添加至基板302，同时在一或多个层(602、604)上形成二嵌段共聚物层200。在实施中，一个层(602)包含黏合剂，且另一层(604)包含金属(诸如溅镀铝等)。金属层604可辅助生长或形成纳米级导体212(例如，催化剂或晶种层等)，且黏合层602可促进在将互连阵列104转移至晶圆或晶粒102之后移除基板302。可使用刀口、UV曝光、热或类似者来移除黏合层602。可例如使用具有各种气体(Cl2、SiCl4、Cl2/BCl3、Cl2/HBr等)的干式蚀刻来移除金属层604。
图7是根据实例具体实例的纳米级导体212的两个实例集合的说明，第一集合(展示于(A)处)自催化剂层生长，且第二集合(展示于(B)处)在纳米级导体212上具有涂层以达成所要属性。假定图7中所展示的纳米级导体212安置于绝缘层(诸如聚合物202)内以形成互连阵列104，然而，为了清晰起见，未在图7中展示绝缘层。在图7中所展示的实例中，基板302表示模板基板，其视情况涂布有催化剂层(诸如层208或层602)用于生长或形成纳米级导体212。
在各种具体实例中，如图7中所展示，纳米级导体212可涂布有选定材料以达成所要属性。举例而言，必要时，导电纳米级导体212可涂布有绝缘薄膜或涂层，以将一个纳米级导体212与另一纳米级导体隔离。在另一实例中，必要时，导电纳米级导体212可涂布有另一导电材料以改良导电性。此外，由非导电材料组成的纳米级线可涂布有导电材料以提供导电纳米级线(亦即，纳米级导体212)。
在替代具体实例中，纳米级导体212可自例如导电纳米粒子802生长。图8至图10展示根据实例具体实例的用于使用纳米粒子802来形成纳米级导体212及互连阵列104的实例处理步骤。在各种实施中，纳米粒子802可由导电性催化剂材料(诸如金或其他类似金属)组成。
参看图8，将纳米粒子802(催化剂粒子)安置于模板基板302上(视情况仅安置于模板的所要区域上)。纳米级导体212可成图案或阵列自纳米粒子802生长，如上所述。将绝缘层(诸如聚合物层202)添加至纳米级导体212的图案或阵列，从而形成互连阵列104。可抛光互连阵列104的暴露表面，且将互连阵列104结合至晶圆或晶粒102，如上所述。可藉由机械剥离、研磨、蚀刻、镭射剥离或其他制程来移除模板基板302。
参看图9，可使用模板辅助的自组装制程将纳米粒子802安置于模板基板302上。举例而言，凹槽及/或凹点(视情况成所要图案或配置)可配置于基板302的暴露表面上，从而允许纳米粒子802沉降至凹槽及/或凹点中。将绝缘层202(例如，黏合性聚合物涂布等)添加至纳米粒子802的配置，从而在基板302上形成中间层902。而非自纳米粒子802生长纳米线，藉由例如薄膜转移将中间层902作为单独层自基板302转移至晶圆或晶粒102。蚀刻中间层902以曝露纳米粒子802的另一侧，从而形成类似于互连阵列104的互连阵列904，但使用纳米粒子802来替代纳米级导体212的纳米线。
参看图10，图9的制程可经修改以使得绝缘层202是薄层，其在经应用之后曝露纳米粒子802。此在基板302上形成互连阵列904，在使用基板302将互连阵列904转移至晶圆或晶粒102之后(经由机械剥离、研磨、蚀刻、镭射剥离等)将基板移除。
除非另外规定，否则具体提及的构件的替代性构件可用以实施本文中所描述的技术。在各种实施中，本文中所描述的技术可应用于封装式微电子构件102的堆叠或堆叠的群组或类似者。
图11及图12是说明根据各种实施的用于形成包含微电子元件(诸如晶粒102)的三维堆叠的微电子组件100(包括互连阵列104)的实例程序1100及1200的流程图。使用图11及图12的基于文字的流程图说明所描述程序是不意欲为限制性的实例。此外，图1至图10及其各别论述亦以基于图形的流程图形式说明用于形成微电子组件100及/或互连阵列104的实例程序。关于图1至图12所描述的程序中的每一者亦描述对应设备、结构、系统或类似者。图11及图12的区块已参考图1至图10处所展示的配置。
参看图11，在1102处，程序包括在一基板上形成包含一二嵌段共聚物的一绝缘层，所述绝缘层包括一第一聚合物与一第二聚合物的一自组装纳米级矩阵阵列。在一实例中，程序包括在一半导体晶圆上形成所述二嵌段聚合物绝缘层及将所述绝缘层转移至一金属基板以形成所述纳米级导体阵列。在1104处，程序包括自所述纳米级矩阵阵列移除所述第二聚合物以显露所述纳米级矩阵阵列中的多个纳米级孔。举例而言，此可包括使所述二嵌段共聚物曝露于紫外线辐射、溶解所述第二聚合物及以化学方式移除所述第二聚合物以显露所述多个纳米级孔。
在1106处，程序包括用一或多种导电材料填充所述多个纳米级孔以在所述绝缘层内形成多个纳米级导体，所述纳米级导体自所述绝缘层的一第一表面延伸至所述绝缘层的与所述第一表面相对的一第二表面。在一具体实例中，程序包括使用液相或气相无电沉积或使用一脉冲式电沉积而用一或多种导电材料填充所述纳米级矩阵阵列中的所述多个纳米级孔，将催化剂金属颗粒用作用以生长所述纳米级导体的晶种或将一金属层或金属基板用作一晶种而以化学方式在一溶液中在所述纳米级矩阵阵列中的所述多个纳米级孔内生长所述多个纳米级导体。在一实施中，程序包括形成所述多个纳米级导体以沿着每一纳米级导体的长度包括多个区段，其中所述多个区段中的邻近区段包含一不同导电材料。在一个实例中，此包括形成每一纳米级导体的最接近所述绝缘层的所述第一或所述第二表面的一区段，以包含一焊料或焊料型材料。
在1108处，程序包括将所述绝缘层内的所述纳米级导体阵列结合至一第一微电子元件的一第一面处的多个第一元件接点，所述多个第一元件接点面朝所述绝缘层的所述第一表面。在1110处，程序包括自所述绝缘层的所述第二表面移除所述基板。在1112处，程序包括将所述绝缘层内的所述纳米级导体阵列结合至一第二微电子元件的一第二面处的多个第二元件接点，所述多个第二元件接点面朝所述绝缘层的所述第二表面。在1114处，程序包括藉由所述多个纳米级导体形成所述第一微电子元件的所述第一元件接点与所述第二微电子元件的所述第二元件接点之间的电气互连。
参看图12，在1202处，程序包括在一基板上的一绝缘层内形成一纳米级导体阵列，所述纳米级导体自所述绝缘层的一第一表面延伸至所述绝缘层的与所述第一表面相对的一第二表面，所述阵列具有一纳米级间距。在一实施中，程序包括以一第一材料形成所述纳米级导体及以一第二材料涂布所述纳米级导体以获得所要属性，其中至少所述第一材料或所述第二材料是一导电性材料。在一个具体实例中，所述第一材料及所述第二材料中的另一个是非导电性材料。
在1204处，程序包括将所述绝缘层内的所述纳米级导体阵列结合至一第一微电子元件的一第一面处的多个第一元件接点，所述多个第一元件接点面朝所述绝缘层的所述第一表面；程序包括在一单个应用中将所述纳米级导体阵列及所述绝缘层应用于所述第一微电子元件，而不考虑所述纳米级导体与所述第一元件接点的一特定对准。在1206处，程序包括自所述绝缘层的所述第二表面移除所述基板。
在1208处，程序包括将所述绝缘层内的所述纳米级导体阵列结合至一第二微电子元件的一第二面处的多个第二元件接点，所述多个第二元件接点面朝所述绝缘层的所述第二表面。在一具体实例中，此包括将所述第二微电子元件接合至所述绝缘层内的所述纳米级导体阵列，而不考虑所述纳米级导体与所述第二元件接点的一特定对准，程序包括藉由所述绝缘层将所述第一微电子元件以机械方式耦接至所述第二微电子元件，其中所述绝缘层包含一黏合剂。
在1210处，程序包括藉由所述多个纳米级导体形成所述第一微电子元件的所述第一元件接点与所述第二微电子元件的所述第二元件接点之间的电气互连。
微电子组件100或互连阵列104的与所说明或所论述的组态不同的组态可在不同实施的情况下是可能的，且在本发明的范围内。变体可比图1至图12中所展示的实例中所说明具有更少元件，或所述变体可比所展示的实例具有更多或替代性元件。
本文中用来描述程序的次序并不意欲被解释为限制，且可按任何次序组合任何数目个所描述程序区块以实施程序或替代性程序。另外，可自程序删除个别区块而不脱离本文中所描述的标的物的精神及范围。此外，程序可用任何适合的材料或其组合来实施，而不脱离本文中所描述的标的物的范围。在替代性实施中，其他技术可以各种组合包括于程序中，且保持在本发明的范围内。
结论
尽管已以特定针对于结构特征及/或方法行动用语言来描述本发明的实施，但应理解，所述实施未必限于所描述的特定特征或行动。确切而言，将特定特征及行动揭示为实施实例装置及技术的代表性形式。
本文的每一技术方案构成单独具体实例，且组合不同技术方案的具体实例及/或不同具体实例在本发明的范围内，且在查阅本发明之后对于一般熟习此项技术者将显而易见。
以上所述仅是本实用新型的优选实施例而已，并非对本实用新型做任何形式上的限制，虽然本实用新型已以优选实施例揭露如上，然而并非用以限定本实用新型，任何熟悉本专业的技术人员，在不脱离本实用新型技术方案的范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本实用新型技术方案的内容，依据本实用新型的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本实用新型技术方案的范围内。

Claims (24)

1.一种微电子组件，其包含：
绝缘层，其具有第一表面及与所述第一表面相对的第二表面；
多个纳米级导体，其以阵列方式安置于所述绝缘层内，所述多个纳米级导体自所述绝缘层的所述第一表面延伸至所述第二表面，所述阵列具有纳米级间距；
第一微电子元件，其具有第一面及所述第一面处的多个第一元件接点，所述第一元件接点面朝所述绝缘层的所述第一表面且在所述绝缘层的所述第一表面处结合至所述多个纳米级导体；及
第二微电子元件，其具有第二面及所述第二面处的多个第二元件接点，所述第二元件接点面朝所述绝缘层的所述第二表面且在所述绝缘层的所述第二表面处结合至所述多个纳米级导体，所述多个纳米级导体形成所述第一微电子元件的第一元件接点与所述第二微电子元件的第二元件接点之间的电气互连。
2.如权利要求1所述的微电子组件，其中所述绝缘层包含将所述第一微电子元件以机械方式耦接至所述第二微电子元件的黏合剂，而所述多个纳米级导体将所述第一微电子元件的元件接点电气耦接至所述第二微电子元件的元件接点。
3.如权利要求1所述的微电子组件，其中所述绝缘层是第一绝缘层，所述微电子组件其进一步包含第二绝缘层，所述第二绝缘层从与所述第二面相对的面的所述第二微电子元件延伸至第三微电子元件的第三面，所述第二绝缘层包括以纳米级间距阵列方式安置于所述第二绝缘层内的第二多个纳米级导体，所述第二多个纳米级导体从与所述第二面相对的所述面延伸至所述第三面且形成所述第二微电子元件的元件接点与所述第三微电子元件的元件接点之间的电气互连。
4.一种微电子组件，其包含：
绝缘层，其具有第一表面及与所述第一表面相对的第二表面；
多个纳米级导体，其成阵列安置于所述绝缘层内，所述多个纳米级导体自所述绝缘层的所述第一表面延伸至所述第二表面，所述阵列具有纳米级间距；
一或多个第一微电子元件，其具有第一面及所述第一面处的多个第一元件接点，所述第一元件接点面朝所述绝缘层的所述第一表面且在所述绝缘层的所述第一表面处结合至所述多个纳米级导体；及
一或多个第二微电子元件，其具有第二面及所述第二面处的多个第二元件接点，所述第二元件接点面朝所述绝缘层的所述第二表面且在所述绝缘层的所述第二表面处结合至所述多个纳米级导体，所述多个纳米级导体形成所述一或多个第一微电子元件的第一元件接点与所述一或多个第二微电子元件的第二元件接点之间的电气互连。
5.一种微电子互连阵列，其包含：
绝缘层，其具有第一表面及与所述第一表面相对的第二表面；
多个纳米级导体，其成纳米级间距阵列安置于所述绝缘层内，所述多个纳米级导体自所述绝缘层的所述第一表面延伸至所述第二表面，所述多个纳米级导体中的每一纳米级导体沿着所述纳米级导体的长度包含多个区段，所述多个区段中的邻近区段包含导电材料的不同组成物。
6.如权利要求5所述的微电子互连阵列，其进一步包含第一微电子元件及第二微电子元件，且其中所述多个纳米级导体形成所述第一微电子元件的第一电气接点与所述第二微电子元件的第二电气接点之间的电气互连，所述微电子互连阵列安置于所述第一微电子元件与所述第二微电子元件之间，且所述第一微电子元件的所述电气接点及所述第二微电子元件的所述电气接点分别面朝所述绝缘层的所述第一表面及所述第二表面。
7.如权利要求6所述的微电子互连阵列，其进一步包含具有多个第三电气接点的第三微电子元件，所述第三电气接点面朝所述绝缘层的所述第一表面或所述第二表面且在所述绝缘层的所述第一表面或所述第二表面处结合至所述多个纳米级导体，且其中所述多个纳米级导体分别形成所述第三微电子元件的所述第三电气接点与所述第二微电子元件的所述第二电气接点或所述第一微电子元件的所述第一电气接点之间的电气互连。
8.如权利要求6所述的微电子互连阵列，其中所述绝缘层包含将所述第一微电子元件以机械方式耦接至所述第二微电子元件的黏合性聚合物材料。
9.如权利要求5所述的微电子互连阵列，所述多个纳米级导体中的每一纳米级导体包括包含铜或铜合金的一或多个区段、包含镍或镍合金的一或多个区段及包含锡或锡合金的一或多个区段。
10.一种系统，其包含如权利要求5所述的一或多个微电子互连阵列及多个微电子元件的三维堆叠，所述一或多个微电子互连阵列中的微电子互连阵列安置于所述堆叠的邻近微电子元件之间，所述微电子互连阵列形成所述堆叠的所述邻近微电子元件的接触端子之间的电气互连。
11.如权利要求10所述的系统，其中第一对邻近微电子元件包括与第二对邻近微电子元件不同的接触端子的配置，且其中安置于所述第一对邻近微电子元件之间的微电子互连阵列与安置于所述第二对邻近微电子元件之间的另一微电子互连阵列具有纳米级导体的相同实体配置。
12.一种制造微电子组件的方法，其包含：
在基板上形成包含二嵌段共聚物的绝缘层，所述绝缘层包括第一聚合物与第二聚合物的自组装纳米级矩阵阵列；
自所述纳米级矩阵阵列移除所述第二聚合物以显露所述纳米级矩阵阵列中的多个纳米级孔；
用一或多种导电材料填充所述多个纳米级孔以在所述绝缘层内形成多个纳米级导体，所述纳米级导体自所述绝缘层的第一表面延伸至所述绝缘层的与所述第一表面相对的第二表面；
将所述绝缘层内的所述纳米级导体阵列结合至第一微电子元件的第一面处的多个第一元件接点，所述多个第一元件接点面朝所述绝缘层的所述第一表面；
自所述绝缘层的所述第二表面移除所述基板；
将所述绝缘层内的所述纳米级导体阵列结合至第二微电子元件的第二面处的多个第二元件接点，所述多个第二元件接点面朝所述绝缘层的所述第二表面；
藉由所述多个纳米级导体形成所述第一微电子元件的所述第一元件接点与所述第二微电子元件的所述第二元件接点之间的电气互连。
13.如权利要求12所述的方法，其进一步包含使所述二嵌段共聚物曝露于紫外线辐射、溶解所述第二聚合物及以化学方式移除所述第二聚合物以显露所述多个纳米级孔。
14.如权利要求12所述的方法，其进一步包含使用液相或气相无电沉积或使用脉冲式电沉积而用一或多种导电材料填充所述纳米级矩阵阵列中的所述多个纳米级孔。
15.如权利要求12所述的方法，其进一步包含将催化剂金属颗粒用作用以生长所述纳米级导体的晶种或将金属层或金属基板用作晶种而以化学方式在溶液中的所述纳米级矩阵阵列中的所述多个纳米级孔内生长所述多个纳米级导体。
16.如权利要求12所述的方法，其进一步包含在半导体晶圆上形成所述二嵌段聚合物绝缘层及将所述绝缘层转移至金属基板以形成所述纳米级导体阵列。
17.如权利要求12所述的方法，其进一步包含形成所述多个纳米级导体以沿着每一纳米级导体的长度包括多个区段，其中所述多个区段中的邻近区段包含不同导电材料。
18.如权利要求17所述的方法，其进一步包含形成每一纳米级导体的最接近所述绝缘层的所述第一或所述第二表面的区段以包含焊料或焊料型材料。
19.一种制造微电子组件的方法，其包含：
在基板上的绝缘层内形成纳米级导体阵列，所述纳米级导体自所述绝缘层的第一表面延伸至所述绝缘层的与所述第一表面相对的第二表面，所述阵列具有纳米级间距；
将所述绝缘层内的所述纳米级导体阵列结合至第一微电子元件的第一面处的多个第一元件接点，所述多个第一元件接点面朝所述绝缘层的所述第一表面；
自所述绝缘层的所述第二表面移除所述基板；
将所述绝缘层内的所述纳米级导体阵列结合至第二微电子元件的第二面处的多个第二元件接点，所述多个第二元件接点面朝所述绝缘层的所述第二表面；
藉由所述多个纳米级导体形成所述第一微电子元件的所述第一元件接点与所述第二微电子元件的所述第二元件接点之间的电气互连。
20.如权利要求19所述的方法，其进一步包含以第一材料形成所述纳米级导体及以第二材料涂布所述纳米级导体以获得所要属性，其中至少所述第一材料或所述第二材料是导电性材料。
21.如权利要求20所述的方法，其中所述第一材料及所述第二材料中的另一个是非导电性材料。
22.如权利要求19所述的方法，其进一步包含在单个应用中将所述纳米级导体阵列及所述绝缘层应用于所述第一微电子元件，而不考虑所述纳米级导体与所述第一元件接点的特定对准。
23.如权利要求19所述的方法，其进一步包含将所述第二微电子元件接合至所述绝缘层内的所述纳米级导体阵列，而不考虑所述纳米级导体与所述第二元件接点的特定对准。
24.如权利要求19所述的方法，其进一步包含藉由所述绝缘层将所述第一微电子元件以机械方式耦接至所述第二微电子元件，所述绝缘层包含黏合剂。
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