CN108807283A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

Info

Publication number
CN108807283A
CN108807283A CN201710992220.0A CN201710992220A CN108807283A CN 108807283 A CN108807283 A CN 108807283A CN 201710992220 A CN201710992220 A CN 201710992220A CN 108807283 A CN108807283 A CN 108807283A
Authority
CN
China
Prior art keywords
substrate
back side
reinforcer
back surface
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710992220.0A
Other languages
English (en)
Other versions
CN108807283B (zh
Inventor
叶庭聿
陈伟铭
孙翊强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108807283A publication Critical patent/CN108807283A/zh
Application granted granted Critical
Publication of CN108807283B publication Critical patent/CN108807283B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本公开公开一种半导体封装结构。所述半导体封装结构包括：衬底，其具有前表面及背表面；中介层上覆芯片结构，其安装于所述衬底的所述前表面上；背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述中介层上覆芯片结构的突部；及多个导电凸块，其安装于所述衬底的所述背表面上。

Description

半导体封装结构
技术领域
本发明实施例涉及半导体封装结构。
背景技术
在集成电路的封装(特定来说倒装芯片封装)中，归因于不同材料及不同封装组件之间的热膨胀系数(CTE)的失配而产生翘曲及应力。翘曲及应力是封装结构的可靠性的改进中的主要关注。
出于在阅读以下详细描述之后将变得明显的这些原因及其它原因，存在对克服上文论述的问题的经改进倒装芯片封装的需要。
发明内容
根据本发明的实施例，一种半导体封装结构，其包含：衬底，其具有前表面及背表面；中介层上覆芯片结构，其安装于所述衬底的所述前表面上；背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述中介层上覆芯片结构的突部；及多个导电凸块，其安装于所述衬底的所述背表面上。
根据本发明的实施例，一种半导体封装结构，其包含：衬底，其具有前表面及背表面；第一半导体结构，其安装于所述衬底的所述前表面上；第二半导体结构，其安装于所述衬底的所述前表面上；前侧加强件，其安装于所述衬底的所述前表面上方且大体上沿所述衬底的四个边缘安装；第一背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述第一半导体结构的突部；第二背侧加强件，其从所述背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述第二半导体结构的突部；及多个导电凸块，其安装于所述衬底的所述背表面上。
根据本发明的实施例，一种半导体封装结构，其包含：衬底，其具有前表面及背表面；半导体结构，其安装于所述衬底的所述前表面上；背侧加强件，其包括四边形环部分及平板部分，所述背侧加强件安装于所述衬底的所述背表面上方；及多个导电凸块，其安装于所述衬底的所述背表面上。
附图说明
在结合附图阅读时，可自以下详细描述最优选地理解本公开的方面。应注意，根据产业中的标准实践，各个装置未按比例绘制。实际上，为了清楚论述，可任意增大或减小各个装置的尺寸。
图1是根据本公开的一项实施例的半成品封装结构的剖面图，其展示安装到衬底的背侧的背侧加强件；
图2说明图1的封装结构的顶表面透视图和背表面透视图；
图3是根据本公开的一项实施例的半成品封装结构的剖面图，其展示安装到衬底的背侧的两个背侧加强件；
图4说明图3的封装结构的顶表面透视图和背表面透视图；
图5是根据本公开的另一实施例的半成品封装结构的剖面图，其展示安装到衬底的背侧的背侧加强件；及
图6说明图5的封装结构的顶表面透视图及背表面透视图。
具体实施方式
下列公开内容提供用于实施本公开的不同装置的许多不同实施例或实例。下文描述组件及布置的特定实例以简化本公开。当然，这些仅为实例且不旨在限制。举例来说，在下列描述中的第一装置形成于第二装置上方或上可包括其中所述第一装置及所述第二装置经形成为直接接触的实施例，且还可包括其中额外装置可形成在所述第一装置与所述第二装置之间，使得所述第一装置及所述第二装置可不直接接触的实施例。另外，本公开可在各个实例中重复参考数字及/或字母。此重复是用于简单及清楚的目的且本身并不指示所论述的各种实施例及/或配置之间的关系。
此外，为便于描述，可在本文中使用空间相对术语(例如“在……下方”、“在……下”、“下”、“在……上”、“上”及类似术语)以描述如图中所说明的一个元件或装置与另一(若干)元件或装置的关系。空间相对术语旨在涵盖除在图中描绘的定向以外，装置在使用或操作中的不同定向。设备可经另外定向(旋转90度或以其它定向)，且因此可同样解释本文中所使用的空间相对描述词。
虽然阐述本公开的广泛范围的数值范围及参数为近似值，但已尽可能精确地报告特定实例中所阐述的数值。然而，任何数值固有地含有必然由各自试验测量中所发现的标准差引起的某些误差。又，如本文中使用，术语“大约”大体上意谓在给定值或范围的10％、5％、1％或0.5％内。替代地，当由所属领域的一半技术人员考虑时，术语“大约”意谓在平均值的可接受标准误差内。除了在操作/工作实例中外，或除非另有明确指定，否则所有数值范围、数量、值及百分比(例如材料数量、持续时间、温度、操作条件、数量比及本文公开的其类似物的数值范围、数量、值及百分比)应理解为在所有例项中被术语“大约”修饰。因此，除非相反地指示，否则本公开及随附发明申请专利范围中阐述的数值参数是可视需要变化的近似值。最起码，应至少鉴于所报告的有效数位的个数且通过应用普通舍位技术解释各数值参数。范围可在本文中表达为从一个端点到另一端点或在两个端点之间。除非另有指定，否则本文公开的所有范围包括所述端点。
在微电子行业内，承载集成电路的半导体装置(例如单芯片、三维(3D)IC、结构上覆芯片(衬底上覆芯片(CoS)或晶片上覆芯片(CoW)))通常安装于提供从半导体装置到封装之外部的电连接的封装载体(例如衬底、电路板或引线框)上。在被称为半导体装置安装的一个此封组装置中，半导体装置包括电连接到衬底上的导电接触件(称作焊料凸块)的相应区域阵列的导电接触件(称作接垫)的区域阵列。通常，焊料凸块与接垫配准且应用回焊工艺以产生半导体装置与衬底之间的焊料接合点形式的电连接。半导体装置安装的工艺导致半导体装置与衬底之间的空间或间隙。
半导体装置及衬底通常由具有失配的热膨胀系数(CTE)的不同材料形成。因此，半导体装置及衬底在加热时经受明显不同尺寸改变，此产生半导体装置与衬底之间的电连接中大的热致应力。如果未补偿，那么热膨胀的差异可导致半导体装置的性能的劣化、对焊料接合点的损坏或封装破裂。随半导体装置的尺寸增大，半导体装置与衬底之间的热膨胀系数的失配的效应变得更明显。在堆叠裸片封装中，裸片层压板与封装之间的热膨胀系数的失配可甚至比单裸片封装中更大。堆叠裸片封装中的破裂机制可从焊料接合点损坏偏移到裸片损坏。
为改进半导体装置封装组合件中的电连接的可靠性，在微电子产业中通常使用囊封材料或底胶填充来填充半导体装置与衬底之间的间隙。底胶填充通过减小在热循环(例如，温度改变)期间或当半导体装置及衬底具有大温度差时由电连接经受的应力而增大封装的疲劳寿命并改进电连接的可靠性。
为进一步提高封装组合件的刚性，通常在封装组合件中采用前侧加强件。前侧加强件(有时也称为“前侧画框”)是由材料(例如具有大体上相同于在其中心具有窗的封装衬底的尺寸的金属)制成的刚性四边形环状结构。前侧加强件附接于衬底的前侧上且围绕半导体装置来约束衬底以便防止其可由封装组合件、可靠性测试或现场操作期间的热循环引起的翘曲或相对于半导体装置的其它移动。
图1是根据本公开的一项实施例的半成品封装结构200的剖面图，其展示安装到衬底20的背表面202的背侧加强件4。半成品封装结构200包括通过粘着剂3安装到前表面201的前侧加强件2。在示范性实施例中，半导体结构30可包括晶片上覆芯片(CoW)结构。CoW结构也称为硅衬底上覆芯片结构或中介层上覆芯片结构。CoW结构经安装到衬底20(例如印刷电路板(PCB)或多层模块)的前表面201，且一同形成衬底上覆CoW(CoWoS)结构200。然而，这并非本公开的限制。在一些实施例中，半导体结构30可为单芯片、三维(3D)IC或任何其它半导体组件(例如无源组件)。
参考图1，其描绘通过晶片上覆芯片工艺而堆叠有成型芯片47的中介层70(例如晶片)。本文中的中介层70可由(例如)硅或例如陶瓷、玻璃、塑料、树脂或环氧树脂的其它适合材料制成。成型芯片47可包括囊封于模塑料49中的几个裸片10。裸片10经选取并放在一起用于某些功能且包括(例如)微处理器装置，所述微处理装置具有：编程存储器，例如FLASH或EEPROM装置；及微处理器，其具有特定应用处理器，例如用于传感器应用的基带收发器、图形处理器、高速缓存存储器装置、存储器管理装置及模/数转换器。各裸片10可具有多个终端12，所述多个终端12指代导电垫或接垫。凸块下金属(UBM)14经沉积为邻近终端12且由介电层13支撑。
中介层70包括从中介层70的上表面延伸到底表面的贯穿中介层通路(TIV)33。重布层(RDL)35可形成于中介层70之上表面上方。RDL 35包括介电层及与TIV 33耦合的经图案化导体以便产生电连接。导电垫37形成于RDL 35与成型芯片47之间的介电层38中。使用多个导电凸块15来通过UBM 39及导电垫37将裸片10耦合到TIV 33。
在中介层70的底表面处，多个导电垫51耦合到TIV 33。UBM 63与导电垫51电连接，其中UBM 63被聚合物层52围绕并支撑。导电凸块65经放置为邻近于UBM 63，其中导电凸块65可通过受控倒迭芯片连接(C4)凸块实施。中介层70通过使导电凸块65与衬底20的导电垫73接触而连接到衬底20。底胶层74填充于中介层70与衬底20之间以加强封装结构10且进一步保护半导体结构30免受挠曲损坏影响。一组焊球60经布置于衬底20的背表面202处。在一些实施例中，封装结构200进一步包括放置于半导体结构30上方并固定到前侧加强件2的顶部的散热器。
前侧加强件2可为具有大体上相同于衬底20的尺寸的平坦结构且其中具有开口以暴露半导体结构30。前侧加强件2的一个目的是约束衬底20以便防止其可由封装组合件、可靠性测试或现场操作期间的热循环引起的翘曲或相对于半导体结构30的其它移动。此移动可由半导体结构30及衬底材料的不同热膨胀系数(CTE)引起。然而，如上文提及，甚至在封装10中使用前侧加强件2的情况下，封装10仍可在一定程度上遭受翘曲。归因于裸片及衬底材料的不同热膨胀系数，衬底易于翘曲，衬底通常弯曲成凸形状。前侧加强件2可在一定程度上减小此翘曲，例如可减轻约25％至约45％的翘曲。
由于甚至在封装结构10中使用前侧加强件2的情况下，封装仍在一定程度上遭受翘曲。特定来说，前侧加强件2相对于衬底20作为整体设计而非侧重于半导体结构30的区域。半导体结构30的区域周围的翘曲及应力可导致性能劣化或封装破裂。因而，采用背侧加强件4以强化封装结构200。背侧加强件4通过粘着剂6安装到背表面202。粘着剂6可包括相同或类似于粘着剂3的(若干)材料，而背侧加强件4的(若干)材料可相同于或可不同于加强件2。背侧加强件4由刚性但挠性的材料形成。在一项示范性实施例中，背侧加强件4包括例如纯铜(C1100)、黄铜或不锈钢的金属。然而，这并非本公开的限制。在一些实施例中，背侧加强件4可包括铝或铜钨。在另一实施例中，背侧加强件4可包括陶瓷材料。在又另一实施例中，背侧加强件4可包括含硅材料。在又另一实施例中，背侧加强件4可包括复合物合金。在又另一实施例中，背侧加强件4可包括塑料材料。
背侧加强件4的尺寸根据半导体结构30的尺寸确定。为便于理解，图2说明图2的封装结构200的顶表面透视图和背表面透视图。图2的左侧展示顶表面透视图且右侧展示背表面透视图。如从顶表面透视图可见，前侧加强件2(顶表面透视图中具有深色的部分)是大体上沿衬底20的四个边缘放置的四边形环状结构。具体地，前侧加强件2可不精确沿衬底20的四个边缘形成并与其重叠而是从衬底20的四个边缘向内回缩达预定距离。然而，前侧加强件2的尺寸仍与如可在图3和4中展示的后续实施例中更清楚识别的衬底20的尺寸相关。另一方面，背侧加强件4(背表面透视图中具有深色的部分)具有其与半导体结构30相关的位置及尺寸。半导体结构30在背表面透视图中依虚线说明。根据示范性实施例，当从背表面透视图观看时，背侧加强件4是与半导体结构30的至少四个边缘的突部重叠的四边形环状结构。换句话说，背侧加强件4的外部或外四边形环(即，背侧加强件4的外边缘401与依虚线的半导体结构30的边缘之间的深色部分)不与半导体结构30的突部重叠；且背侧加强件4的内部或内四边形环(即，依虚线的半导体结构30的边缘与背侧加强件4的内边缘402之间的深色部分)与半导体结构30的突部重叠。
相较于前侧加强件2，背侧加强件4具有其与半导体结构30相关的位置及尺寸，此有助于减小特定来说至半导体结构30周围的倒装芯片区域的封装翘曲。保留给背侧加强件4的较大空间允许背侧加强件4具有用于减轻半导体结构30周围的封装翘曲的较宽宽度及较强架构。然而，焊球60可能被迫以不同于原始布置的方式布置且可具有衬底20中的更复杂布线。焊球60的总数目也可被牺牲。在示范性实施例中，背侧加强件4的外四边形环具有至少占据用于放置焊球60的一个行或一个列的空间的宽度。另一方面，背侧加强件4的内四边形环也具有至少占据用于放置焊球60的一个行或一个列的空间的宽度。然而，这并非本公开的限制。在一些实施例中，背侧加强件4的外四边形环或内四边形环的宽度可小于此尺寸。
在示范性实施例中，外四边形环的宽度大体上相同于内四边形环的宽度。即，外四边形环的宽度大体上是背侧加强件环4的宽度的50％，且内四边形环的宽度大体上也是背侧加强件环4的宽度的50％。然而，这并非本公开的限制。
在示范性实施例中，背侧加强件4的内边缘402内的空间仍可用于放置焊球60。因此，本公开可具有侧重于倒装芯片区域的经改进封装翘曲而不损失太多焊球60空间。加强件4的尺寸的需求是加强件4的高度限于相对低于焊球60的高度。以此方式，封装结构200可通过焊球60组装到另一衬底而不被背侧加强件4卡住。另一衬底可为所属领域的技术人员已知的印刷接线板(有时也称为印刷电路板)或多层模块。
图3是根据本公开的一项实施例的半成品封装结构300的剖面图，其展示安装到衬底20的背表面202的两个背侧加强件4a及4b。图3中类似于图1中的类似装置的装置为简单及清楚起见而类似地编号。背侧加强件4a及4b可通过粘着剂6a及6b安装到背表面202。背侧加强件4a及4b可包括相同或类似于加强件4的(若干)材料；且粘着剂6a及6b可包括相同或类似于粘着剂6的(若干)材料。
封装结构300包括两个半导体结构30a及30b。半导体结构30a及30b的各者可包括晶片上覆芯片(CoW)结构。在一些实施例中，半导体结构30a及30b的各者可为单芯片、三维(3D)IC或任何其它半导体组件(例如无源组件)。背侧加强件4a及4b分别对应于半导体结构30a及30b，且背侧加强件4a及4b的尺寸根据半导体结构30a及30b的各者的尺寸确定。为便于理解，图4说明图3的封装结构300的顶表面透视图和背表面透视图。图4的左侧展示顶表面透视图且右侧展示背表面透视图。如从顶表面透视图可见，前侧加强件2(顶表面透视图中具有深色的部分)是大体上沿衬底20的四个边缘放置的四边形环状结构，所述四边形环状结构与图2中展示的封装结构200的前侧加强件布置无差异，尽管封装结构300具有两个倒装芯片且封装结构200仅具有一个倒装芯片。这是因为前侧加强件2的尺寸与衬底20而非衬底20上的芯片的尺寸相关。
另一方面，背侧加强件4a及4b(背表面透视图中具有深色的两个部分)具有其分别与半导体结构30a及30b相关的位置及尺寸。半导体结构30a及30b在背表面透视图中依虚线说明。根据示范性实施例，当从背表面透视图观看时，背侧加强件4a及4b是分别与半导体结构30a及30b的各者的四个边缘的至少一突部重叠的两个四边形环状结构。换句话说，背侧加强件4a的外部或外四边形环(即，背侧加强件4a的外边缘401a与依虚线的半导体结构30a的边缘之间的深色部分)不与半导体结构30a的突部重叠；且背侧加强件4a的内部或内四边形环(即，依虚线的半导体结构30a的边缘与背侧加强件4a的内边缘402a之间的深色部分)与半导体结构30a的突部重叠。背侧加强件4b的外部或外四边形环(即，背侧加强件4b的外边缘401b与依虚线的半导体结构30b的边缘之间的深色部分)不与半导体结构30b的突部重叠；且背侧加强件4b的内部或内四边形环(即，依虚线的半导体结构30b的边缘与背侧加强件4b的内边缘402b之间的深色部分)与半导体结构30b的突部重叠。
相较于前侧加强件2，背侧加强件4a具有其与半导体结构30a相关的位置及尺寸；及背侧加强件4b具有其与半导体结构30b相关的位置及尺寸。减小特定来说到半导体结构30a及30b周围的区域的封装翘曲是有帮助的。封装结构200的加强件4的布置的概念可用于加强件4a及4b。因此为简洁起见此处省略进一步细节。
图5是根据本公开的另一实施例的半成品封装结构400的剖面图，其展示安装到衬底20的背表面202的背侧加强件4c。图5中类似于图1和3中的类似装置的装置为简单及清楚起见而类似地编号。背侧加强件4c可通过粘着剂6安装到背表面202。背侧加强件4c可包括相同或类似于加强件4的(若干)材料。
封装结构400具有相同于封装结构200的前侧布置，其中仅半导体结构30被前侧加强件2围绕。但是背侧加强件4c具有不同于封装结构200的背侧加强件4的结构。背侧加强件4c经配置为从衬底20的背表面202覆盖整个半导体结构30的突部且与其重叠的盖结构。背侧加强件4c包括平板部分及从所述平板部分突出的四边形环部分，且背侧加强件4c通过四边形环部分及粘着剂6固定到衬底20的背表面202。
背侧加强件4c的尺寸根据半导体结构30的尺寸确定。为便于理解，图6说明图5的封装结构400的顶表面透视图和背表面透视图。图6的左侧展示顶表面透视图且右侧展示背表面透视图。如从顶表面透视图可见，前侧加强件2(顶表面透视图中具有深色的部分)是大体上沿如上文参考图2中展示的左侧顶表面透视图提及的衬底20的四个边缘放置的四边形环状结构。背侧加强件4c(背表面透视图中具有深色的部分)具有其与半导体结构30相关的位置及尺寸。半导体结构30在背表面透视图中依虚线说明。根据示范性实施例，当从背表面透视图观看时，背侧加强件4c的四边形环部分是介于如图6中指示的外环401c与内环402c之间。平板部分覆盖外环401c内的整个深色部分。背侧加强件4c的四边形环部分是与半导体结构30的四个边缘的至少一突部重叠的四边形环状结构。换句话说，背侧加强件4c的外部或四边形环部分的外四边形环(即，背侧加强件4c的外边缘401c与依虚线的半导体结构30的边缘之间的深色部分)不与半导体结构30的突部重叠；及背侧加强件4c的内部或四边形环部分的内四边形环(即，依虚线的半导体结构30的边缘与背侧加强件4c的内边缘402c之间的深色部分)与半导体结构30的突部重叠。
相较于背侧加强件4，背侧加强件4c进一步包括平板部分，可通过所述平板部分改进总体背侧加强件4c的刚性。封装结构200的加强件4的布置的概念可用于加强件4c的四边形环部分。因此为简洁起见此处省略进一步细节。但是因为内边缘402c内的区域无法再用于容纳焊球60，所以进一步牺牲焊球60的总数目。因而，盖结构与衬底20之间的空间可用于包括一些无源芯片组件以根据本实施例完全利用空间。无源芯片组件指代例如拥有特定电特性且不易集成到半导体结构30中的电阻器、电容器或电感器。在集成电路芯片中形成所有所需电阻器、电容器或电感器可能是不经济的。出于此原因，如图5和6中展示，无源芯片组件7与半导体结构30组合。为了说明，无源芯片组件7经附接到内边缘402c内的衬底20的背表面202。衬底20与背侧4c的盖结构之间的空间的高度应至少大于无源芯片组件7的高度。
类似于加强件4、4a及4b，加强件4c的高度限于相对低于焊球60的高度。以此方式，封装结构200可通过焊球60组装到另一衬底而不被背侧加强件4c卡住。另一衬底可为所属领域的技术人员已知的印刷接线板(有时也称为印刷电路板)或多层模块。
本公开的上文描述的背侧加强件能够进一步减小封装翘曲，尤其针对倒装芯片定位的裸片区域而非总体衬底。背侧加强件可进一步减小裸片区域的翘曲。例如，针对已具有前侧加强件的封装结构，可进一步通过背侧加强件减小裸片区域处约12.5％的翘曲。在一些实施例中，因为一些焊球空间现保留给背侧加强件，所以可能牺牲焊球的总数目的约10％。概念可不仅限于封装结构，而也可应用于具有大尺寸的所述封装。
本公开的一些实施例提供一种半导体封装结构，其包括：衬底，其具有前表面及背表面；中介层上覆芯片结构，其安装于所述衬底的所述前表面上；背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述中介层上覆芯片结构的突部；及多个导电凸块，其安装于所述衬底的所述背表面上。
本公开的一些实施例提供一种半导体封装结构，其包括：衬底，其具有前表面及背表面；第一半导体结构，其安装于所述衬底的所述前表面上；第二半导体结构，其安装于所述衬底的所述前表面上；前侧加强件，其安装于所述衬底的所述前表面上方且大体上沿所述衬底的四个边缘安装；第一背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述第一半导体结构的突部；第二背侧加强件，其从所述背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述第二半导体结构的突部；及多个导电凸块，其安装于所述衬底的所述背表面上。
本公开的一些实施例提供一种半导体封装结构，其包括：衬底，其具有前表面及背表面；半导体结构，其安装于所述衬底的所述前表面上；背侧加强件，其包括四边形环部分和平板部分，所述背侧加强件安装于所述衬底的所述背表面上方；及多个导电凸块，其安装于所述衬底的所述背表面上。
前文概述数项实施例的特征，使得所属领域的技术人员可更优选地理解本公开的方面。所属领域的技术人员应明白，其可容易将本公开用作设计或修改用于实行本文中介绍的实施例的相同目的及/或达成相同优点的其它程序及结构的基础。所属领域的技术人员也应认识到，这些等效构造并未脱离本公开的精神及范围，且其可在不脱离本公开的精神及范围的情况下在本文中进行各种改变、置换及更改。
符号说明
2 前侧加强件
3 粘着剂
4 背侧加强件
4a 背侧加强件
4b 背侧加强件
4c 背侧加强件
6 粘着剂
6a 粘着剂
6b 粘着剂
7 无源芯片组件
10 裸片/封装结构
12 终端
13 介电层
14 凸块下金属(UBM)
15 导电凸块
20 衬底
30 半导体结构
30a 半导体结构
30b 半导体结构
33 贯穿中介层通路(TIV)
35 重布层(RDL)
37 导电垫
38 介电层
39 凸块下金属(UBM)
47 成型芯片
49 模塑料
51 导电垫
52 聚合物层
60 焊球
63 凸块下金属(UBM)
65 导电凸块
70 中介层
73 导电垫
74 底胶层
200 半成品封装结构/衬底上覆CoW(CoWoS)结构
201 前表面
202 背表面
300 封装结构
400 半成品封装结构
401 背侧加强件4的外边缘
401a 背侧加强件4a的外边缘
401b 背侧加强件4b的外边缘
401c 外环
402 背侧加强件4的内边缘
402a 背侧加强件4a的内边缘
402b 背侧加强件4b的内边缘
402c 内环

Claims (1)

1.一种半导体封装结构，其包含：
衬底，其具有前表面和背表面；
中介层上覆芯片结构，其安装于所述衬底的所述前表面上；
背侧加强件，其从背表面透视图看，安装于所述衬底的所述背表面上方且围绕所述中介层上覆芯片结构的突部；及
多个导电凸块，其安装于所述衬底的所述背表面上。
CN201710992220.0A 2017-04-28 2017-10-23 半导体封装结构 Active CN108807283B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/581,667 US9899305B1 (en) 2017-04-28 2017-04-28 Semiconductor package structure
US15/581,667 2017-04-28

Publications (2)

Publication Number Publication Date
CN108807283A true CN108807283A (zh) 2018-11-13
CN108807283B CN108807283B (zh) 2021-12-28

Family

ID=61189115

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710992220.0A Active CN108807283B (zh) 2017-04-28 2017-10-23 半导体封装结构

Country Status (3)

Country Link
US (1) US9899305B1 (zh)
CN (1) CN108807283B (zh)
TW (1) TWI745418B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111799177A (zh) * 2020-07-14 2020-10-20 通富微电子股份有限公司技术研发分公司 半导体器件的制备方法
CN111952256A (zh) * 2019-05-15 2020-11-17 联发科技股份有限公司 电子封装
CN112713131A (zh) * 2019-10-27 2021-04-27 台湾积体电路制造股份有限公司 半导体器件、包含半导体器件的电子器件以及其制造方法
CN114724967A (zh) * 2022-06-08 2022-07-08 江苏芯德半导体科技有限公司 一种具有tsv的异构芯片封装结构的封装方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018113414A (ja) * 2017-01-13 2018-07-19 新光電気工業株式会社 半導体装置とその製造方法
US11569156B2 (en) * 2019-10-27 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, electronic device including the same, and manufacturing method thereof
KR20210068891A (ko) * 2019-12-02 2021-06-10 삼성전자주식회사 인터포저, 및 이를 가지는 반도체 패키지
US11462418B2 (en) 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11393763B2 (en) * 2020-05-28 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (info) package structure and method
KR20220009534A (ko) * 2020-07-15 2022-01-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US11552029B2 (en) 2020-09-04 2023-01-10 Micron Technology, Inc. Semiconductor devices with reinforced substrates
KR20220076894A (ko) * 2020-12-01 2022-06-08 삼성전자주식회사 지지 부재를 갖는 반도체 패키지
US20220230969A1 (en) * 2021-01-15 2022-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11450622B2 (en) * 2021-01-20 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
CN115332213A (zh) 2021-05-11 2022-11-11 财团法人工业技术研究院 封装载板及其制作方法与芯片封装结构
TWI844801B (zh) * 2021-05-11 2024-06-11 財團法人工業技術研究院 封裝載板及其製作方法與晶片封裝結構
KR20220162991A (ko) 2021-06-02 2022-12-09 삼성전자주식회사 반도체 장치
KR20220166644A (ko) 2021-06-10 2022-12-19 삼성전자주식회사 보강 구조물을 가지는 반도체 패키지
CN114899185B (zh) * 2022-07-12 2022-12-02 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法
US12040321B2 (en) * 2022-09-20 2024-07-16 Advanced Semiconductor Engineering, Inc. Optical device including an optical component an electrical component, assembly structure including an optical component an electrical component and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582395A (zh) * 2008-05-15 2009-11-18 新光电气工业株式会社 布线基板
CN102163590A (zh) * 2011-03-09 2011-08-24 中国科学院上海微系统与信息技术研究所 基于埋置式基板的三维多芯片封装模块及方法
CN103594444A (zh) * 2012-08-14 2014-02-19 钰桥半导体股份有限公司 在中介层及无芯基板之间具有双重连接通道的半导体组件
US20150136838A1 (en) * 2012-06-05 2015-05-21 International Business Machines Corporation Method for shaping a laminate substrate
US20150200186A1 (en) * 2014-01-15 2015-07-16 Jin-woo Park Electronic device, semiconductor package, and method of manufacturing the same
TWM512216U (zh) * 2015-02-17 2015-11-11 Advanced Semiconductor Eng 半導體基板結構與半導體封裝結構

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886408A (en) * 1994-09-08 1999-03-23 Fujitsu Limited Multi-chip semiconductor device
US6497943B1 (en) * 2000-02-14 2002-12-24 International Business Machines Corporation Surface metal balancing to reduce chip carrier flexing
TWI300261B (en) * 2003-07-02 2008-08-21 Advanced Semiconductor Eng Chip package structur
US7332807B2 (en) * 2005-12-30 2008-02-19 Intel Corporation Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same
US7592697B2 (en) * 2007-08-27 2009-09-22 Intel Corporation Microelectronic package and method of cooling same
JP5005603B2 (ja) * 2008-04-03 2012-08-22 新光電気工業株式会社 半導体装置及びその製造方法
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
JP5625340B2 (ja) * 2009-12-07 2014-11-19 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8299633B2 (en) * 2009-12-21 2012-10-30 Advanced Micro Devices, Inc. Semiconductor chip device with solder diffusion protection
TWI398943B (zh) * 2010-08-25 2013-06-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US8472190B2 (en) * 2010-09-24 2013-06-25 Ati Technologies Ulc Stacked semiconductor chip device with thermal management
KR101584471B1 (ko) * 2011-12-16 2016-01-22 인텔 코포레이션 마이크로일렉트로닉 다이용 패키지, 패키지를 구비한 마이크로일렉트로닉 조립체, 마이크로일렉트로닉 시스템, 및 마이크로일렉트로닉 패키지의 다이 응력 감소 방법
US8981555B2 (en) * 2011-12-21 2015-03-17 Intel Corporation Ridged integrated heat spreader
US8816495B2 (en) * 2012-02-16 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structures and formation methods of packages with heat sinks
US8704353B2 (en) * 2012-03-30 2014-04-22 Advanced Micro Devices, Inc. Thermal management of stacked semiconductor chips with electrically non-functional interconnects
US20130277855A1 (en) * 2012-04-24 2013-10-24 Terry (Teckgyu) Kang High density 3d package
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US8796072B2 (en) * 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US10032696B2 (en) * 2012-12-21 2018-07-24 Nvidia Corporation Chip package using interposer substrate with through-silicon vias
US9082743B2 (en) * 2013-08-02 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat dissipation structures
US9076754B2 (en) * 2013-08-02 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat sinks attached to heat dissipating rings
US9543274B2 (en) * 2015-01-26 2017-01-10 Micron Technology, Inc. Semiconductor device packages with improved thermal management and related methods
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US10008439B2 (en) * 2015-07-09 2018-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Thin recon interposer package without TSV for fine input/output pitch fan-out
US9761571B2 (en) * 2015-09-17 2017-09-12 Deca Technologies Inc. Thermally enhanced fully molded fan-out module
US9893042B2 (en) * 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582395A (zh) * 2008-05-15 2009-11-18 新光电气工业株式会社 布线基板
CN102163590A (zh) * 2011-03-09 2011-08-24 中国科学院上海微系统与信息技术研究所 基于埋置式基板的三维多芯片封装模块及方法
US20150136838A1 (en) * 2012-06-05 2015-05-21 International Business Machines Corporation Method for shaping a laminate substrate
CN103594444A (zh) * 2012-08-14 2014-02-19 钰桥半导体股份有限公司 在中介层及无芯基板之间具有双重连接通道的半导体组件
US20150200186A1 (en) * 2014-01-15 2015-07-16 Jin-woo Park Electronic device, semiconductor package, and method of manufacturing the same
TWM512216U (zh) * 2015-02-17 2015-11-11 Advanced Semiconductor Eng 半導體基板結構與半導體封裝結構

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952256A (zh) * 2019-05-15 2020-11-17 联发科技股份有限公司 电子封装
CN111952256B (zh) * 2019-05-15 2023-02-07 联发科技股份有限公司 电子封装
US11830820B2 (en) 2019-05-15 2023-11-28 Mediatek Inc. Electronic package with rotated semiconductor die
CN112713131A (zh) * 2019-10-27 2021-04-27 台湾积体电路制造股份有限公司 半导体器件、包含半导体器件的电子器件以及其制造方法
CN111799177A (zh) * 2020-07-14 2020-10-20 通富微电子股份有限公司技术研发分公司 半导体器件的制备方法
CN111799177B (zh) * 2020-07-14 2023-09-29 通富微电科技(南通)有限公司 半导体器件的制备方法
CN114724967A (zh) * 2022-06-08 2022-07-08 江苏芯德半导体科技有限公司 一种具有tsv的异构芯片封装结构的封装方法

Also Published As

Publication number Publication date
TW201839931A (zh) 2018-11-01
TWI745418B (zh) 2021-11-11
CN108807283B (zh) 2021-12-28
US9899305B1 (en) 2018-02-20

Similar Documents

Publication Publication Date Title
CN108807283A (zh) 半导体封装结构
US7935569B2 (en) Components, methods and assemblies for stacked packages
US7564140B2 (en) Semiconductor package and substrate structure thereof
TW560019B (en) Enhanced die-down ball grid array and method for making the same
US5018005A (en) Thin, molded, surface mount electronic device
US7259448B2 (en) Die-up ball grid array package with a heat spreader and method for making the same
US7245008B2 (en) Ball grid array package, stacked semiconductor package and method for manufacturing the same
JP5095012B2 (ja) 挿入層上に配置されたコンデンサーを有するｉｃパッケージ
US6835598B2 (en) Stacked semiconductor module and method of manufacturing the same
US7745918B1 (en) Package in package (PiP)
CN101276794A (zh) 具有支座的挠性电路电子封装
CN103579137A (zh) 可靠的表面安装整体功率模块
CN106505045A (zh) 具有可路由囊封的传导衬底的半导体封装及方法
US6825556B2 (en) Integrated circuit package design with non-orthogonal die cut out
EP3138126A1 (en) Electronic assembly comprising a carrier structure made from a printed circuit board
US20230187383A1 (en) Semiconductor device and manufacturing method thereof
US8779566B2 (en) Flexible routing for high current module application
GB2396963A (en) Semiconductor packaging structure
US7154171B1 (en) Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
CN113906556A (zh) 一种芯片封装结构以及电路结构
US6825066B2 (en) Stiffener design
EP1283547A1 (en) Packaging process for semiconductor package
KR19980030912A (ko) 칩 스케일 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant