CN111952256A - 电子封装 - Google Patents

电子封装 Download PDF

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Publication number
CN111952256A
CN111952256A CN202010332486.4A CN202010332486A CN111952256A CN 111952256 A CN111952256 A CN 111952256A CN 202010332486 A CN202010332486 A CN 202010332486A CN 111952256 A CN111952256 A CN 111952256A
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China
Prior art keywords
package
package substrate
chip
top surface
high speed
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Granted
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CN202010332486.4A
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CN111952256B (zh
Inventor
苏耀群
徐志荣
林仪柔
彭逸轩
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MediaTek Inc
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MediaTek Inc
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Priority to CN202310021282.2A priority Critical patent/CN115985861A/zh
Publication of CN111952256A publication Critical patent/CN111952256A/zh
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Abstract

本发明公开一种电子封装，包括：矩形的封装基板；芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述芯片封装相对于所述封装基板在垂直于所述顶表面的垂直轴上方具有通过旋转偏移角；以及金属环，安装在所述封装基板的顶表面上。这样使芯片封装相应位置的焊盘连接到封装基板上的焊球的连接线路的距离更短，从而减少信号扭曲，并且可以显著改善电子封装的信号延迟以及SerDes电路的电性能。

Description

电子封装
技术领域
本发明涉及电子技术领域，尤其涉及一种电子封装。
背景技术
通常，数据通讯网络(data communication network)包括多个通信设备以及用于将通信设备互连或联网的连接基础设施(infrastructure)或媒介(medium)。通信设备可以包括嵌入式控制器。通信设备可以与配置为以每秒千兆位(Gigabit-per-second，Gbps)数据速率(例如56Gbps或112Gbps)运转的高速模拟串行(serial)数据接口(interface)或端口(port)连接。串行数据接口根据已知的数据传输标准进行配置。连接基础设施能够与此类高速模拟串行数据接口进行相互联络。
电子系统中高速串行通信链路的使用持续增长。如本领域中已知的，高速数据链接(data link)通过传输线(transmission line)将数据从一个位置传输到另一位置。这些数据链接可以包括以并行(parallel)格式接收数据并将数据转换为串行格式以进行高速传输的串行器/解串器(即Serializer/Deserializer，SerDes)数据链接。SerDes数据链接可以是通信系统中底板(backplane)的一部分。
然而，包含SerDes电路的用于高数据通讯应用的先前技术芯片封装通常遭受由于信号扭曲(signal skew)或信号延迟(signal delay)引起的所谓的SerDes损耗(loss)，这反过来又使芯片封装的电性能恶化。
发明内容
有鉴于此，本发明提供一种电子封装，减少信号扭曲或信号延迟，改善芯片封装的电性能。
根据本发明的第一方面，公开一种电子封装，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述芯片封装相对于所述封装基板在垂直于所述顶表面的垂直轴上方具有通过旋转偏移角；以及
金属环，安装在所述封装基板的顶表面上。
根据本发明的第一方面，公开一种电子封装，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述第一高速接口电路芯片在垂直于所述顶表面的垂直轴上方通过旋转偏移角相对于所述封装基板旋转；以及
金属环，安装在封装基板顶表面上。
根据本发明的第一方面，公开一种电子封装，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述第一高速接口电路芯片在垂直于顶表面的垂直轴上方通过旋转偏移角相对于所述封装基板旋转；
金属环，安装在所述封装基板的顶面上；以及
至少一个去耦电容器，位于所述封装基板的角部，其中，所述去耦电容器相对于封装基板在垂直于顶表面的垂直轴上方通过旋转偏移角旋转。
本发明的电子封装由于所述芯片封装相对于所述封装基板在垂直于所述顶表面的垂直轴上方具有通过旋转偏移角，从而使芯片封装相应位置的焊盘连接到封装基板上的焊球的连接线路的距离更短，从而减少信号扭曲，并且可以显著改善电子封装的信号延迟以及SerDes电路的电性能。
附图说明
图1是根据本发明的一个实施例的半导体电子封装的俯视立体图。
图2是图1的虚线I-I’的示意剖视图。
图3是根据本发明一个实施例的半导体电子封装的透视图。
图4是在封装基板上具有金属环和旋转的半导体晶粒的电子封装的示意性俯视图。
图5是沿图4中的虚线II-II’截取的示意性剖视图。
图6是示出根据本发明另一实施例的具有金属盖的电子封装的示意性截面图。
图7是具有金属环和旋转的半导体晶粒的电子封装的示意性顶视图，示出了根据本发明的另一实施例的在金属环与芯片封装之间的三角形区域内布置有更多的去耦电容器。
图8是具有金属环和旋转的半导体晶粒的电子封装的示意性俯视图，示出了根据本发明的另一实施例的一些芯片布置在金属环与芯片封装之间的三角形区域内。
图9是根据本发明的另一个实施例的具有用于弯曲控制的延伸的金属环的电子封装的示意性顶视图。
具体实施方式
在本发明实施例的以下详细描述中，参考了作为本发明的一部分的附图，并且其中通过图示的方式示出了可以实践本发明的特定优选实施例。足够详细地描述了这些实施例以使本领域技术人员能够实践它们，并且应该理解，可以利用其他实施例，并且可以在不脱离本发明的精神和范围的情况下进行机械，结构和程序上的改变。因此，以下详细描述不应被视为具有限制意义，并且本发明的实施例的范围仅由所附权利要求限定。
应当理解，尽管本实施例可以使用术语第一，第二，第三，主要，次要等来描述各种元件，部件，区域，层和/或部分，但是这些元件，部件，区域，层和/或部分不应受这些术语的限制。这些术语仅用于将一个元件，组件，区域，层或部分与另一个元件，组件，区域，层或部分区分开。因此，在不脱离本发明构思的教导的情况下，下面讨论的第一或主要元件，组件，区域，层或部分可以称为第二或次要元件，组件，区域，层或部分。
本实施例可以使用空间相对术语，例如“在…之下”，“在…下方”，“下方”，“在…下面”，“在…之上”，“上方”，“在…上面”等，以便于描述图中一个元素或特征与另一个元素或特征的关系。应当理解，除了图中所示的方向取向之外，空间相对术语旨在包括使用或操作中的装置的不同取向。例如，如果图中的设备被翻转，则描述为在其他元件或特征“在…下方”或“在…之下”或“下方”的元件将被定向在其他元件或特征“在…之上”或“上方”。因此，示例性术语“在…下方”和“下方”可以包括上方和下方的方向。装置可以以其他方式定向(旋转90度或在其他方位)，并且相应地解释本文使用的空间相对描述符。另外，还应理解，当层被称为在两个层“之间”时，它可以是两个层之间的唯一层，或者也可以存在一个或多个中间层。
这里使用的术语仅用于描述特定实施例的目的，并不旨在限制本发明构思。如这里所使用的，单数形式“一”，“一个”和“该”，“所述”旨在也包括复数形式，除非上下文另有明确说明。将进一步理解，当在本说明书中使用时，术语“包括”和/或“包含”指定所述特征，整体，步骤，操作，元件和/或组件的存在，但不排除存在或者添加一个或多个其他特征，整体，步骤，操作，元素，组件和/或其组合。如这里所使用的，术语“和/或”包括一个或多个相关所列项目的任何和所有组合，并且可以缩写为“/”。
应当理解，当元件或层被称为“在…上”，“连接到”，“耦合到”或“邻接”另一个元件或层时，它可以直接在另一个元件或层的上方，直接连接，直接耦合或直接邻接于另一个元件或层，或者可以在元件或层与另一个元件或层之间存在中间元件或层。相反，当元件被称为“直接在......上”，“直接连接到”，“直接耦合到”或“直接邻接”另一元件或层时，不存在中间元件或层。
串行器/解串器(SerDes)是高速通信中常用的一对功能块(functional block)，用于补偿有限的输入/输出。这些功能块在每个方向上在串行数据(serial data)和并行接口(parallel interface)之间转换数据。术语“SerDes”通常是指在各种技术和应用程序中使用的接口。SerDes的主要用途是在单条线(single line)或差分对(differential pair)上提供数据传输，以最大程度地减少I/O引脚和互连的数量。SerDes数据传输的实现可在各种通信系统和设备中使用，例如移动设备，桌面计算机和服务器，计算机网络和电信网络。
本发明所公开的电子封装配置为以每秒千兆位元(Gbps，或每秒千兆位元)数据速率运行，能够减少信号扭曲，从而改善芯片封装的电性能，该芯片封装适用于包括但不限于以下各项在内的高数据速率通信应用：超大型数据中心，超高性能网络交换机，路由器或计算应用程序以及4G和5G服务提供商(回程(backhaul))基础设施，AI(ArtificialIntelligence，人工智能)深度学习应用程序以及新颖的计算应用程序。
请参考图1至图3。图1为根据本发明的一实施例的电子封装的俯视图。图2是沿图1中的虚线I-I’截取的示意性截面图。图3是根据本发明的一个实施例的电子封装的透视图。
如图1至图3所示，根据一个实施例，电子封装1包括芯片封装10，该芯片封装10以倒装芯片(flip-chip)的方式安装在封装基板20的顶表面201上并且可以通过凸块30接合到顶表面201。从上方看时，芯片封装10和封装基板20都可以具有矩形形状(分别具有正方形或长方形形状)。例如，芯片封装10和封装基板20都可以具有正方形形状，该正方形形状具有相等长度的四个侧面。芯片封装10具有四个侧面10a、10b、10c、10d。封装基板20具有四个顶点
Figure BDA0002465458640000041
和在四个顶点
Figure BDA0002465458640000042
之间的四个侧面
Figure BDA0002465458640000043
如图1所示，封装基板20的顶表面201可以通过在二维平面(平行于顶表面201)中的两个正交轴(参考X和Y轴)划分成四个90度象限
Figure BDA0002465458640000045
Figure BDA0002465458640000044
象限Q1和Q3在对角在线彼此相对。象限Q2和Q4在对角在线彼此相对。通过图1至图3，示出了与顶表面201或X-Y平面正交的参考Z轴。
根据一个实施例，封装基板20可以是有机基板，其包括层压的有机材料或芯200，例如环氧树脂等。如图2所示，一个或多个焊球230可以布置在封装基板20的底表面202上。芯片封装10通过多个焊点或凸块30安装在封装基板20的顶表面201上。底部填充物40可以分配以填充芯片封装10和封装基板20之间的间隙(或支座(standoff))。封装基板20可以包括多层迹线，例如迹线211和221。
在图2中，迹线211可以在设置在封装基板20的多层迹线的最顶层中。通常，迹线211可以覆盖有保护层280，例如阻焊剂等，但不限于此。凸块30与例如位于迹线211的一个远程处的对应的凸块焊盘210接合并对准(或对齐，可以指凸块30与凸块焊盘210在俯视方向上至少部分地重叠)。迹线211朝向顶点A处的拐角或朝向围绕该拐角的两个相邻侧面20a和20b延伸。
用于电连接相应的凸块焊盘210的迹线211通常设置在本实施例的象限Q2内。迹线211电耦合到连接焊盘212，也就是说凸块焊盘210通过迹线211连接到连接焊盘212。可以设置电镀通孔(plated through hole，PTH)213以将连接焊盘212电连接到封装基板20的底表面202处的焊球焊盘214。焊球230焊在焊球焊盘214上，以进一步与系统板或印刷电路板(printed circuit board，PCB)连接。
为了简单起见，如图1所示，仅示出在象限Q2内的迹线和焊球布置。在图1中未明确示出焊球230。然而，可以理解，由于连接焊盘212与焊球焊盘214对齐(例如完全对齐或有错开的对齐，例如有部分重叠而有部分未重叠)，因此连接焊盘212与焊球230对齐(例如至少部分地对齐)，因此，图1中每个连接焊盘212的位置通常代表每个焊球230的位置(也就是说，每个连接焊盘212的下方均可以设有相应的焊球230)。可以理解，在其他实施例中，象限Q2中所示的上述配置可以用于其他象限Q1，Q3和Q4。
如图1和图3所示，芯片封装10和封装基板20可以具有相同的中心点CP，因此芯片封装具有相对于封装基板20成角度偏移的同心构造。例如，芯片封装10相对于封装基板20在Z轴上方旋转大约45度的旋转偏移角θ(也就是说，芯片封装10的对角线相对于封装基板20的对角线之间具有大约45度的夹角，当然也可以是其他角度，例如30到75度等)，其中旋转偏移角θ是参考Y轴与芯片封装10的侧面10b或10d方向之间的夹角。根据一个实施例，芯片封装10的四个侧面10a至10d中的任何一个都不与封装基板20的四个侧面20a至20d中的任何一个平行。
旋转芯片封装10，使得其一侧10a直接面对封装基板20的顶点A处的一个拐角(也即面对顶点A处的角)。封装基板20的两个侧面20a和20b在顶点A处接合。这两个侧面20a和20b定义了90度象限Q2的边界。
根据一个实施例，芯片封装10包括第一高速接口电路晶粒11，其可以以至少1000Mbps的高速数据传输速率在高于500MHz的频率下运转。如图2所示，第一高速接口电路芯片11可以封装在模塑料50内。根据一个实施例，第一高速接口电路芯片11包括第一串行器/解串器(SerDes)电路块110，位于紧靠侧面10a的附近，侧面10a直接面向封装基板20的顶点A的拐角。
根据一个实施例，如图1所示，第一高速接口电路晶粒11包括直接面对封装基板20的顶点A处的拐角的第一边缘11a，垂直于第一边缘11a并连接到第一边缘11a的第二边缘11b，垂直于第一边缘11a并连接到第一边缘11a的第三边缘11c。根据一个实施例，第一边缘11a与芯片封装10的侧面10a平行，第二边缘11b与芯片封装10的侧面10d平行，并且第三边缘11c与侧面10b平行。第二边缘11b和第三边缘11c与在顶点A和顶点C之间延伸的对角线DL平行。
根据一个实施例，如图1所示，第一排输入/输出(input/output，I/O)焊盘111a沿着第一边缘11a布置，第二排I/O焊盘111b沿着第二边缘11b布置，第三排I/O焊盘111c沿第三边缘11c设置。可以理解，这些I/O焊盘111设置在第一高速接口电路芯片11的底部。
根据一个实施例，可以在第一高速接口电路晶粒11和封装基板20的顶表面201之间提供重分布层(redistribution layer，RDL)结构100，以将I/O焊盘111分散开。在本领域中已知的RDL结构100可以由介电层和介电层中的互连结构组成，以将高速接口电路芯片11的I/O焊盘电连接到形成在凸块30上的相应的凸块焊盘101。根据一个实施例，芯片封装10可以是扇出芯片级封装(fan-out wafer level package，FOWLP)。
根据一个实施例，第一高速接口电路晶粒11的第一SerDes电路块110，边缘11a至11c，I/O焊盘排111a至111c(第一排I/O焊盘111a，第二排I/O焊盘111b，第三排I/O焊盘111c)通常设置在示例性象限Q2内。可以理解，芯片封装10倒装，芯片封装10的有源表面(active surface)以倒装芯片的方式安装在封装基板20的顶表面201上。
如图1所示，根据一个实施例，沿着在顶点A处接合的两个侧面20a和20b布置第一组焊球P1(焊球未在图1中明确示出，但与连接焊盘212a对齐，例如设置在连接焊盘212a的下方)。在封装基板20的顶表面201上的象限Q2内，布置在第一高速接口电路晶粒11的第一边缘11a处的第一排I/O焊盘111a分别通过迹线211a电连接到第一组焊球P1。
根据一个实施例，第二组焊球P2(焊球未在图1中明确示出，但与连接焊盘212b对齐，例如设置在连接焊盘212b的下方)沿着与顶点A处的拐角相邻的侧面20a布置。在封装基板20的顶表面201上的象限Q2内，第二排I/O焊盘111b分别通过迹线211b电连接到第二组焊球P2。
根据一个实施例，第三组焊球P3(焊球未在图1中明确示出，但与连接焊盘212c对准)沿着与顶点A处的拐角相邻的侧面20b布置。在封装基板20的顶面201上的象限Q2内，第三排I/O焊盘111c分别通过迹线211c电连接到第三组焊球P3。
根据一个实施例，如图2所示，芯片封装10还可以包括在第一高速接口电路晶粒11附近的第二高速接口电路晶粒12。第二高速接口电路晶粒12可以是包括SerDes电路块120，并且可以在封装基板20的顶表面201的象限Q4中具有类似的迹线和球形布置。第一高速接口电路晶粒11可以通过RDL结构100电连接到第二高速接口电路芯片12。例如，第一高速接口电路芯片11的I/O焊盘111d通过RDL结构100中的互联机103电连接到第二高速接口电路芯片12的I/O焊盘121d。在象限Q4中，第二高速接口电路晶粒12上的I/O焊盘可以采用与第一高速接口电路晶粒11相类似的迹线布置，从而降低从晶粒到焊球之间的迹线长度或线路长度。
使用本发明是有利的，因为通过提供旋转的芯片封装配置，封装基板上的相应迹线和焊球布置集中在四个象限Q1至Q4中的一个之内，这样使得最大信号长度减少14.3％。(例如，对于
Figure BDA0002465458640000061
的封装基板，最大信号长度从约35mm减少至约30mm)，并且迹线长度差(最大长度减去最小长度的差值)从20mm显著减小至13mm。因此，可以减少信号扭曲，并且可以显著改善电子封装的信号延迟以及SerDes电路的电性能(例如，提高18％或-0.5dB左右)。
值得注意的是，尽管在说明性实施例中使用了大约45度的旋转偏移角θ，但是在其他实施例中，电子封装1中的旋转晶粒设计不限于该角度。例如，在一些实施例中，旋转偏移角θ可以在30度和75度之间的范围内。
图4和图5示出了在封装基板上具有金属环和旋转的半导体晶粒的电子封装，其中，相似的层，元件或区域由相似的数字和标注表示。如图4和图5所示，根据一个实施例的电子封装1a可以包括金属环(或金属框架)60，该金属环60通过粘合剂层610粘附到封装基板20的顶表面201。在实施例中，金属环60可以是铜环，但不限于此。根据一些实施例，封装基板20具有矩形形状并且具有四个角。
如前所述，芯片封装10包括安装在封装基板20的顶表面201上的第一高速接口电路晶粒11和设置在第一高速接口电路芯片11附近的第二高速接口电路晶粒12。芯片封装10，第一高速接口电路芯片11和第二高速接口电路芯片12相对于封装基板20在垂直轴(图5中的Z轴)上方旋转。通过旋转偏移角θ垂直于顶表面201。
如图4中的虚线所示，封装基板20上的旋转芯片封装10可以在电子封装1a的四个角中的每个角处的三角形区域T中提供一些空间，以用于改善翘曲控制或电气性能。其中，在电子封装的四个角中的每个角处的区域未必一定是三角形的，可以是其他形状，或开放的区域，因此可称为在金属环和旋转的芯片封装的侧面之间的区域。其中，在图4所示的实施例中，当旋转偏移角为45度时，芯片封装10的拐角处距离金属环60的距离几乎是最小的，因此在电子封装的四个角中的每个角处的区域位置或面积较大(或者三角形区域T的面积较大)，因此可以方便在该区域布置元器件，例如布置更多的电容器等等；或者金属环60可以在该区域上具有延伸的结构(例如如下图9所示)，这样可以使金属环具有更大的覆盖面积，从而进一步防止封装的翘曲和开裂等问题，提高封装的机械强度。另外，旋转偏移角也可以为其他角度，例如上述提到的30-75度，这可以根据芯片封装10的大小和形状以及封装基板20的大小和形状来共同确定，当然可以调整旋转偏移角以使在电子封装的四个角中的每个角处的区域位置或面积较大(或者三角形区域T的面积较大)。此外图4中虚线所示的三角形区域T仅是为了示意，并非实际的元器件的划线。
应该理解，如图6所示，在一些实施例中，金属环60可以用覆盖芯片封装10的顶表面的金属盖60a代替。在图6中，电子封装1b的模塑料50可以抛光直到暴露出第一高速接口电路芯片11和第二高速接口电路芯片12的顶表面。金属盖60a可以与第一高速接口电路芯片11和第二高速接口电路芯片12的暴露的顶表面热接触。金属盖60a可以是一体的结构，以加强封装的机械强度，更好的防止翘曲。
根据一些实施例，如图7所示，金属环60和芯片封装10之间的三角形区域T可用于在四个角中的每个角落的三角形区域T中容纳更多的去耦电容器(decoupling capacitor)70。因此，电子封装1c在封装的拐角处包括更多的去耦电容器，从而改善了电性能，例如配电网络(power distribution network，PDN)的性能。
根据一些实施例，至少一个去耦电容器70可以设置在封装基板1c的拐角处(或角落处或角部)，其中，去耦电容器70相对于封装基板20在垂直于顶表面201的垂直轴(图5中的Z轴)的上方旋转偏移角θ。也就是说，去耦电容器70可以与芯片封装10具有相同的旋转角度，以方便布线连接以及充分利用到电子封装角落处的区域。
根据一些实施例，如图8所示，金属环60和芯片封装10之间的三角形区域T可以用于容纳更多的芯片80或更大尺寸的芯片。布置在三角形区域T内的芯片80可以旋转或不旋转，例如一个或一些芯片80可以与芯片封装10具有相同的旋转角度，另一个或另一些芯片80相对于封装基板20未旋转。通过在电子封装1d中提供这样的配置，多芯片模块可以更大并且更对称，从而导致更好的封装翘曲控制和改善的电性能。模块可以是模制型(molding-type，其可具有或不具有功能)封装，以平衡热膨胀系数(coefficient of thermalexpansion，CTE)不匹配并改善封装翘曲。
根据一些实施例，如图9所示，金属环90可包括在金属环90和芯片封装10之间的三角形区域T(如图4或图9中的虚线所示)内的延伸部分90a，该延伸部分90a与金属环90可以是一体结构或整体结构。封装翘曲控制由于在电子封装1f的四个角处竖立的较宽的环形脚而得到改进。根据本发明的上述方式，通过将芯片封装10进行旋转而使得在电子封装的角落位置处留出了空置区域，这样可以设置该延伸部分90a，从而在没有明显加宽金属环90的侧面宽度的情况下，增加金属环90的覆盖面积，从而进一步防止封装的翘曲和开裂等问题，提高封装的机械强度；同时本发明的上述方式在电子封装有限的空间中扩展了金属环的结构和安装方式，提高了空间利用率，相比先前技术以低成本的方式降低了封装翘曲的可能性，加强了封装强度(先前技术中可能需要增加金属环的侧面宽度来提高封装强度，然而这受到电子封装空间的限制，并且影响基板走线设计)。金属环可以控制常规大尺寸芯片封装的共面性(coplanarity)和翘曲，并且本实施例中通过将芯片封装10进行旋转，不仅优化了基板走线设计，基板标记(例如条形码，基准标记等)，而且还优化了基板拐角处的金属环/盖的足宽设计，具有较佳的应用优势。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (14)

1.一种电子封装，其特征在于，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述芯片封装相对于所述封装基板在垂直于所述顶表面的垂直轴上方具有通过旋转偏移角；以及
金属环，安装在所述封装基板的顶表面上。
2.如权利要求1所述的电子封装，其特征在于，所述旋转偏移角在30度至75度之间；或者，所述旋转偏移角为45度。
3.如权利要求1所述的电子封装，其特征在于，所述封装基板的顶表面通过在二维平面中的两个正交轴而划分为四个象限，所述第一高速接口电路晶粒包括直接面对所述封装基板的顶点的第一边缘，其中，沿着所述第一边缘布置有第一排输入/输出焊盘。
4.如权利要求3所述的电子封装，其特征在于，所述第一高速接口电路晶粒包括与所述第一边缘垂直的第二边缘，其中，沿着所述第二边缘布置有第二排输入/输出焊盘。
5.如权利要求4所述的电子封装，其特征在于，第一组焊球沿着在所述封装基板的所述顶点处连接的两侧布置，并且其中，所述第一排输入/输出焊盘分别通过封装基板顶表面上四个象限之一内的第一迹线电连接到所述第一组焊球。
6.如权利要求5所述的电子封装，其特征在于，第二组焊球沿着在所述封装基板的所述顶点处接合的所述两侧之一布置，并且其中，所述第二排输入/输出焊盘分别通过在所述封装基板的顶表面上的四个象限之一内的第二迹线电连接到所述第二排焊球。
7.如权利要求1所述的电子封装，其特征在于，所述第一高速接口电路晶粒包括第一串行器/解串器电路块。
8.如权利要求1所述的电子封装，其特征在于，还包括：靠近所述第一高速接口电路晶粒的第二高速接口电路晶粒，所述第二高速接口电路晶粒包括第二串行器/解串器电路块。
9.如权利要求8所述的电子封装，其特征在于，所述第一高速接口电路晶粒通过重分布层结构电连接至所述第二高速接口电路晶粒。
10.如权利要求1所述的电子封装，其特征在于，还包括：电容器，设置在金属环和旋转的芯片封装的侧面之间的区域内；或/和，还包括：芯片，设置在金属环和旋转的芯片封装的侧面之间的区域内。
11.如权利要求10所述的电子封装，其特征在于，所述芯片相对于所述封装基板为旋转的或不旋转的。
12.如权利要求1所述的电子封装，其特征在于，所述金属环包括延伸部分，所述延伸部分设置在所述金属环与旋转的芯片封装的侧面之间的区域内。
13.一种电子封装，其特征在于，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述第一高速接口电路芯片在垂直于所述顶表面的垂直轴上方通过旋转偏移角相对于所述封装基板旋转；以及
金属环，安装在封装基板顶表面上。
14.一种电子封装，其特征在于，包括：
矩形的封装基板；
芯片封装，包括第一高速接口电路芯片，所述芯片封装安装在所述封装基板的顶表面上，其中所述第一高速接口电路芯片在垂直于顶表面的垂直轴上方通过旋转偏移角相对于所述封装基板旋转；
金属环，安装在所述封装基板的顶面上；以及
至少一个去耦电容器，位于所述封装基板的角部，其中，所述去耦电容器相对于封装基板在垂直于顶表面的垂直轴上方通过旋转偏移角旋转。
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