CN108807264A - 形成钨支柱的方法 - Google Patents
形成钨支柱的方法 Download PDFInfo
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- CN108807264A CN108807264A CN201810410364.5A CN201810410364A CN108807264A CN 108807264 A CN108807264 A CN 108807264A CN 201810410364 A CN201810410364 A CN 201810410364A CN 108807264 A CN108807264 A CN 108807264A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 229910052721 tungsten Inorganic materials 0.000 title claims description 64
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims description 63
- 239000010937 tungsten Substances 0.000 title claims description 63
- 239000000758 substrate Substances 0.000 claims description 82
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 16
- 239000000376 reactant Substances 0.000 claims description 13
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- OUUQCZGPVNCOIJ-UHFFFAOYSA-N hydroperoxyl Chemical compound O[O] OUUQCZGPVNCOIJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000003672 processing method Methods 0.000 claims description 6
- 238000000197 pyrolysis Methods 0.000 claims description 6
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 125000001246 bromo group Chemical group Br* 0.000 claims description 2
- 150000001335 aliphatic alkanes Chemical class 0.000 claims 1
- 230000002035 prolonged effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 239000002243 precursor Substances 0.000 abstract description 2
- 239000012528 membrane Substances 0.000 abstract 2
- 210000002381 plasma Anatomy 0.000 description 22
- 238000012545 processing Methods 0.000 description 19
- 229910052732 germanium Inorganic materials 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 239000003795 chemical substances by application Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000012546 transfer Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
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- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000012495 reaction gas Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- -1 tungsten halogen compound Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 239000002019 doping agent Substances 0.000 description 3
- 229910000078 germane Inorganic materials 0.000 description 3
- 238000000746 purification Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229910000077 silane Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- AEOGRWUNSVGMMJ-UHFFFAOYSA-N trimethylgermane Chemical compound C[GeH](C)C AEOGRWUNSVGMMJ-UHFFFAOYSA-N 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- YLAFGLJNWFUJLU-UHFFFAOYSA-N $l^{2}-germane;$l^{3}-germane Chemical compound [GeH2].[GeH2].[GeH2].[GeH3].[GeH3] YLAFGLJNWFUJLU-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000219289 Silene Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- LUXIMSHPDKSEDK-UHFFFAOYSA-N bis(disilanyl)silane Chemical compound [SiH3][SiH2][SiH2][SiH2][SiH3] LUXIMSHPDKSEDK-UHFFFAOYSA-N 0.000 description 1
- 229910052918 calcium silicate Inorganic materials 0.000 description 1
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- LICVGLCXGGVLPA-UHFFFAOYSA-N disilanyl(disilanylsilyl)silane Chemical compound [SiH3][SiH2][SiH2][SiH2][SiH2][SiH3] LICVGLCXGGVLPA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
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- 238000010438 heat treatment Methods 0.000 description 1
- 230000033444 hydroxylation Effects 0.000 description 1
- 238000005805 hydroxylation reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 230000001788 irregular Effects 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
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- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229940094989 trimethylsilane Drugs 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
描述了形成自对准图案的方法。在图案化膜上沉积膜材料以填充和覆盖由所述图案化膜形成的特征。使所述膜材料凹入到低于所述图案化膜的顶部的水平。通过暴露于金属前驱物来将所述凹入膜转化为金属膜,接着所述金属膜体积膨胀。
Description
技术领域
本公开内容总体上涉及沉积和处理薄膜的方法。特别地,本公开内容涉及用于填充基板中的沟槽的工艺。
背景技术
半导体工业正在快速开发具有越来越小的晶体管尺寸的芯片以获得每单位面积更多的功能。随着器件尺寸不断缩小,在器件之间的间隙/空间也在不断缩小,这提高了使器件彼此物理隔离的难度。用高质量的介电材料对在器件之间的通常为不规则形状的高深宽比沟槽/空间/间隙进行填充正成为对用现有方法(包括间隙填充,硬掩模和间隔器应用)的实现方式的不断增加的挑战。选择性沉积方法典型地包括在基板上沉积掩模材料并将掩模材料图案化以形成图案化掩模。基板的区域可以随后在对掩模图案化后透过图案化的掩模而被暴露。可以将图案化的掩模从基板去除以暴露基板的未经注入的区域,并且可以将材料选择性地沉积在所述基板的选定区域上。
本领域中需要用于具有较小临界尺寸的芯片设计的新的方法。另外,一直需要用于硬掩模和间隔器应用的高质量的金属氧化物膜以及在基板上形成图案化膜的方法。
发明内容
本公开内容的一个或多个实施方式针对处理方法,所述处理方法包括向基板表面提供图案化膜,所述图案化膜形成至少一个特征。所述至少一个特征从所述图案化膜的顶表面向底表面延伸一定深度。所述至少一个特征具有由第一侧壁和第二侧壁限定的宽度。在所述图案化膜上沉积膜以填充所述至少一个特征并在所述图案化膜的顶表面上方延伸。使所述膜凹入来使膜的顶部降低到等于或低于所述图案化膜的顶表面的高度以形成凹入膜。将所述凹入膜转化为钨膜。使所述钨膜膨胀以形成从所述至少一个特征延伸的支柱。
本公开内容的另外实施方式针对处理方法,所述处理方法包括向基板表面提供图案化膜,所述图案化膜形成至少一个特征。所述至少一个特征从顶表面向底表面延伸一定深度并且具有由第一侧壁和第二侧壁限定的宽度。将所述基板表面暴露于包含甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种的硅前驱物,来通过热解在所述基板表面上沉积非晶硅膜以填充所述至少一个特征并在基板表面上方延伸。用氢等离子体或氢自由基蚀刻所述非晶硅膜,使所述非晶硅膜凹入来使所述膜的顶部降低到等于或低于所述图案化膜的顶表面的高度以形成凹入非晶硅膜。将所述凹入非晶硅膜暴露于钨前驱物来与所述凹入非晶硅膜反应以将大体上整个的凹入非晶硅膜都转化为钨膜。使所述钨膜氧化来使钨膜膨胀以形成从所述至少一个特征大体上笔直地向上延伸的钨支柱。
本公开内容的进一步实施方式针对处理方法,所述处理方法包括向基板表面提供图案化膜,所述图案化膜形成至少一个特征。所述至少一个特征从顶表面向底表面延伸一定深度并且具有由第一侧壁和第二侧壁限定的宽度。将所述基板表面暴露于包含甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种的硅前驱物,来通过热解在所述基板表面上沉积非晶硅膜以填充所述至少一个特征并在所述图案化膜的顶表面上方延伸。所述热解在没有硅共反应物的情况下、并且在不用等离子体的情况下在范围为约300℃至约550℃的温度下或在用等离子体的情况下在范围为约-100℃至约50℃的温度下进行。用氢等离子体或氢自由基蚀刻所述非晶硅膜,使所述非晶硅膜凹入来使所述膜的顶部降低到等于或低于所述图案化膜的顶表面的高度以形成凹入非晶硅膜。在范围为约300℃至约550℃的温度下将所述凹入非晶硅膜暴露于包含WF6的钨前驱物,来与所述凹入非晶硅膜反应以将大体上整个的凹入非晶硅膜都转化为钨膜。使所述钨膜氧化来使钨膜膨胀以形成从所述至少一个特征大体上笔直地向上延伸的钨支柱。
附图说明
以使得可详细理解本公开内容的上述记载的特征的方式,可以通过参考实施方式对在上文简要概述的本公开内容作更特定的描述,实施方式中的一些示出在附图中。然而,需要注意的是,附图仅示出了本公开内容的典型实施方式,并且因此不被视为限制本公开内容的范围,因为本公开内容可允许其他等效实施方式。
图1示出根据本公开内容的一个或多个实施方式的基板特征的剖视图;和
图2A至2E示出根据本公开内容的一个或多个实施方式的填隙工艺的示意性剖视图。
具体实施方式
在描述本公开内容的若干示例性实施方式前,应当理解,本公开内容不限于以下描述中阐述的构造或工艺步骤的细节。本公开内容能够具有其他实施方式并能够以各种方式来实践或实施。
如本文所用的“基板”是指在制造工艺期间在执行膜处理的基板上形成的任何基板或材料表面。例如,可执行处理的基板表面包括材料,诸如硅、氧化硅、应变硅、绝缘体上硅(SOI))、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石,以及任何其他材料,诸如金属、金属氮化物、金属合金和其他导电材料,这取决于应用。基板包括但不限于半导体晶片。基板可暴露于预处理工艺以将基板表面抛光、蚀刻、还原、氧化、羟化、退火、UV固化、E射束固化和/或烘烤。除了直接在基板本身的表面上的膜处理之外,本公开内容中,所公开的膜处理步骤中的任一者也可在基板上形成的下层上执行,如下文所更详细公开的,并且术语“基板表面”旨在包括如上下文指示的此类下层。因此,例如,在膜/层或部分膜/层已被沉积在基板表面上时,新沉积膜/层的暴露表面变为基板表面。
本公开内容的一个或多个实施方式针对用于沉积金属氧化物膜以用于任何共形、非共形和/或低至高深宽比自对准图案化或间隙/沟槽/空隙填充应用的方法。本公开内容的实施方式有利地提供了用于在具有小尺寸的高深宽比(AR)结构中沉积膜(例如,金属氧化物膜)的方法。本公开内容的一些实施方式有利地提供了填充间隙而不在间隙中形成接缝的方法。本公开内容的一个或多个实施方式有利地提供了形成自对准图案的方法。
图1示出了具有特征110的基板100的部分剖视图。附图出于说明目的而示出了具有单个特征的基板;然而,本领域的技术人员将理解,可以有多于一个特征。特征110的形状可以是任何合适的形状,包括但不限于沟槽和圆柱形的通孔。在特定实施方式中,特征110是沟槽。如就此所用的,术语“特征”表示任何有意的表面不规则处。特征的合适实例包括但不限于具有一个顶部、两个侧壁和一个底部的沟槽、具有一个顶部和从表面向上延伸的两个侧壁的尖峰、以及具有从表面向下延伸的侧壁和敞开底部的通孔。特征或沟槽可以具有任何合适的深宽比(特征的深度与特征的宽度的比率)。在一些实施方式中,该深宽比大于或等于约5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。
基板100具有顶表面120。所述至少一个特征110在顶表面120中形成开口。特征110从顶表面120延伸深度D而到达底表面112。特征110具有第一侧壁114和第二侧壁116,二者限定特征110的宽度W。由侧壁和底部形成的敞开区域也被称为间隙。虽然特征110被示出为形成在单个部件基板100中的沟槽,但是本领域的技术人员将认识到,特征110可由基板100上的图案化膜形成。图2A示出了特征110被形成为由图案化膜130形成或在图案化膜130内形成的沟槽或通孔的实施方式。
现在参照图2A至2C,描述了本公开内容的示例性实施方式。提供基板100来在具有或不具有图案化膜130形成在其上的情况下处理。如就此所用的,术语“提供”表示基板放置到某个位置或环境中用以进一步处理。在一些实施方式中,图案化膜130形成在基板100上以提供所述至少一个特征110。在一些实施方式中,基板100被提供为已有图案化膜130存在。
如图2A所示,图案化膜可以是与基板100不同的材料,使得存在第一表面132和不同于第一表面132的第二表面134。特征110形成在图案化膜130中,使得特征110的底部112提供第一表面132和侧壁114、116,并且特征110的顶表面120提供第二表面134。图案化膜130可以是任何合适的材料。一些实施方式的图案化膜130包括低k电介质(例如,SiOC)。图案化膜130可经选择以与后续的处理条件相容。
在图2B中,在基板100表面上沉积或形成膜140以填充特征110并在图案化膜130的顶表面120上方延伸。膜140可以是由任何合适工艺形成的任何合适的膜,所述任何合适工艺包括但不限于化学气相沉积、等离子体增强化学气相沉积、原子层沉积、等离子体增强原子层沉积和/或物理气相沉积。在一些实施方式中,膜140通过原子层沉积或等离子体增强原子层沉积形成。
在一些实施方式中,前驱物与惰性气体、载体气体和/或稀释气体一起流入容纳基板100的处理腔室中。前驱物可化学吸附到基板100或图案化膜130以在基板或图案化膜上留下化学吸附的前驱物。共反应物可然后流入处理腔室以与化学吸附的前驱物反应以沉积膜140。在一些实施方式中,前驱物与共反应物一起流入处理腔室。前驱物和共反应物可以气相进行反应并且形成沉积到基板或图案化膜上以使膜140生长的物质。
在一些实施方式中,膜140通过前驱物的热解来沉积。在一些实施方式中,所述热解不包括与前驱物反应的共反应物来沉积膜140。例如,硅前驱物可暴露于基板以在基板100上和特征110内沉积或形成膜140。
在一些实施方式中,膜140包含非晶硅。在一个或多个实施方式中,膜140基本上由非晶硅组成。如就此所用的,术语“基本上由......组成”是指膜以摩尔计大于或等于约95%、98%或99%的非晶硅。
形成非晶硅膜可通过任何合适的技术来完成。在一些实施方式中,通过在没有共反应物或大体上没有共反应物的情况下热解硅前驱物来形成非晶硅膜。如就此所用的,术语“大体上没有共反应物”是指与硅前驱物反应的任何物质或吸附的前驱物分子以小于或等于约50%、40%、30%、20%、10%或5%的化学计量的量存在用于进行反应。
在一些实施方式中,使用甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种沉积非晶硅膜。在一些实施方式中,可使用更高价硅烷(例如,大于或等于5、6、7、8、9或10个硅原子)来沉积非晶硅膜。
在一些实施方式中,通过共形沉积工艺沉积非晶硅膜,其中硅前驱物在足以促进前驱物热解的温度和压力下暴露于基板100和任何图案化膜130。在一些实施方式中,在沉积期间的温度在约300℃至约550℃的范围内或在约350℃至约500℃的范围内。在一些实施方式中,在沉积期间的压力在约10T至约600T的范围内,或在约50T至约500T的范围内,或在约100T至约400T的范围内。通过共形沉积工艺对非晶硅膜的沉积可以在有等离子体暴露或没有等离子体暴露的情况下进行。在一些实施方式中,共形沉积工艺在没有等离子体暴露的情况下进行。
在一些实施方式中,非晶硅膜通过可流动膜沉积工艺沉积。在可流动膜沉积工艺期间的温度可以在约-100℃至约50℃的范围内,或在约-50℃至约25℃的范围内。在一些实施方式中,可流动膜沉积工艺在约1T至约10T范围内的压力下进行。在一个或多个实施方式中,可流动膜沉积工艺包括使用具有范围为约10W至约200W的功率的RF等离子体的等离子体暴露。所述等离子体可以是导电耦合等离子体(CCP)或电感耦合等离子体(ICP)。
如图2C所示,在沉积后,膜140凹入以形成具有顶部141的凹入膜145。顶部141被降低到等于或低于图案化膜130的顶表面120的高度。在一些实施方式中,凹入膜145具有与图案化膜130的顶表面120大体上共面的顶部141。如以此方式所用的,术语“大体上共面的”表示顶部141在距图案化膜130的顶表面内。在一些实施方式中,凹入膜145的顶部141在图案化膜130的高度的约20%至约98%的范围内。在一些实施方式中,凹入膜145的顶部141在图案化膜130的高度的约30%至约95%或约40%至约90%或约50%至约85%的范围内。
使膜140凹入以形成凹入膜145可通过任何合适的技术来完成。在一些实施方式中,使膜140凹入包括蚀刻膜140。在一些实施方式中,蚀刻包括反应离子蚀刻(RIE)工艺。在一些实施方式中,RIE使用溴基蚀刻剂。在一个或多个实施方式中,蚀刻膜140包括将膜140暴露于氢等离子体或氢自由基。氢等离子体可以是远程等离子体或直接等离子体,并且可以是CCP或ICP。氢自由基可通过任何合适的手段来产生,包括等离子体产生或通过使蚀刻剂流过热丝以产生自由基。
凹入膜145被转化成钨膜150,如图2D所示。凹入膜的转化可通过任何合适的反应来完成。在一些实施方式中,凹入膜是通过暴露于钨前驱物而转化成钨膜。钨前驱物可以是例如可与凹入膜反应以用钨原子换取硅原子的钨卤化物。
在一些实施方式中,钨前驱物包含WF6。在一些实施方式中,暴露于钨前驱物在范围为约300℃至约550℃的温度和范围为约10T至约100T范围的压力下进行。钨前驱物可与可作为稀释气体、载体气体或惰性气体(例如,氩)或反应气体(例如,H2)的其他气体共流。在一些实施方式中,钨前驱物与促进钨前驱物与凹入膜反应的反应气体共流。
在示例性实施方式中,凹入膜145包含非晶硅或基本上由非晶硅组成,并且钨前驱物包含WF6。钨前驱物在约550℃的温度和约20托的压力下被暴露于非晶硅膜。
在一些实施方式中,大体上整个的凹入膜都转化成钨。如就此所用的,术语“大体上整个的”表示大于或等于约95%、98%或99%的凹入膜被转化成钨。用于转化大体上整个的凹入膜的时间量取决于例如温度、压力、膜组成、膜厚度和钨前驱物。在一些实施方式中,在550℃和20托下,的非晶硅可以在少于约4分钟的时间内被转化为钨。
在将凹入膜145转化为钨150后,钨膜150的顶部151的高度可与凹入膜的高度相同或不同。钨膜150相对于凹入膜的高度取决于例如膜中存在的物质和该物质的原子半径。在一些实施方式中,钨膜150的高度使得膜150的顶部151等于或低于图案化膜130的顶表面120。
如图2E所示,钨膜150可膨胀来引起钨膜150的体积膨胀以形成从顶表面120延伸的钨支柱155。一些实施方式的钨支柱155从表面120笔直向上延伸。膜150的膨胀可以在约10%至约1000%的范围内,或在约50%至约800%的范围内,或在约100%至约700%的范围内。在一些实施方式中,膜130膨胀大于或等于约150%、200%、250%、300%或350%的量。在一些实施方式中,膜150膨胀在约300%至约400%的范围内的量。在一些实施方式中,钨支柱155具有的高度比钨膜150大等于或大于钨膜150的高度的约50%、60%、70%、80%、90%、100%、125%、150%、175%或200%。
在一些实施方式中,膜150通过暴露于硅化剂或硅化条件而膨胀以将金属或含金属的膜转化为金属硅化物膜。硅化剂可以是任何合适的硅化剂,包括但不限于甲硅烷、乙硅烷、丙硅烯、丁硅烷、戊硅烷、己硅烷、三甲基硅烷、具有三甲基硅烷取代基的化合物和它们的组合。在一些实施方式中,硅化条件包括热硅化、等离子体增强硅化、远程等离子体硅化、微波和射频(例如,ICP、CCP)。
在一些实施方式中,膜150通过暴露于锗化剂或锗化条件而膨胀以将金属或含金属的膜转化为金属锗化物膜。锗化剂可以是任何合适的锗化剂,包括但不限于甲锗烷、乙锗烷、丙锗烯、丁锗烷、戊锗烷、己锗烷、三甲基锗烷、具有三甲基锗烷取代基的化合物和它们的组合。在一些实施方式中,锗化条件包括热锗化、等离子体增强锗化、远程等离子体锗化、微波和射频(例如,ICP、CCP)。
如图2E所示,在膨胀期间,在特征的顶部维持特征形状的保形度,使得膜150从特征110笔直向上生长。如就此所用的,“笔直向上”表示膨胀的膜或支柱155的侧面与特征110的侧壁114、116是大体上共面的。表面与侧壁114共面,其中在侧壁114与表面的接合处形成的角度为±10°。
在一些实施方式中,钨膜150在膨胀前掺杂有掺杂剂。掺杂剂可在钨膜150形成的同时结合到钨膜150中,或与膜沉积顺序地在单独工艺中结合到钨膜150中。例如,可以在进行钨膜150的沉积之后,在相同的工艺腔室或不同的工艺腔室中以单独工艺用掺杂剂掺杂钨膜150。
根据一个或多个实施方式,基板在形成层之前和/或之后经受处理。此处理可在相同腔室中或在一个或多个单独的处理腔室中执行。在一些实施方式中,基板从第一腔室移动到单独的第二腔室,用以进一步处理。基板可直接地从第一腔室移动到单独的处理腔室,或基板可从第一腔室移动到一个或多个传送腔室,并然后移动到单独的处理腔室。因此,处理设备可以包括与传送站相连通的多个腔室。此种设备可被称为“组合工具”或“组合系统”等等。
一般地,组合工具是包括多个腔室的模块化系统,这些腔室执行各种功能,包括基板定中心和取向、脱气、退火、沉积和/或蚀刻。根据一个或多个实施方式,组合工具包括至少一个第一腔室以及中央传送腔室。中央传送腔室可以容置机器人,所述机器人能使基板穿梭于各处理腔室和负载锁定腔室之间以及在各处理腔室和各负载锁定腔室中穿梭。传送腔室典型地维持在真空条件下并且提供中间平台,中间平台用于使基板从一个腔室穿梭到另一个腔室和/或穿梭到定位在组合工具的前端的负载锁定腔室。可适用于本发明的两个熟知的组合工具是和二者均可得自加利福尼亚州圣克拉拉应用材料公司(Applied Materials,Inc.,of Santa Clara,Calif.)。然而,腔室的准确布置和组合可出于执行如本文所述的工艺的特定步骤的目的而更改。其他可用的处理腔室包括但不限于循环层沉积(CLD;Cyclical Layer Deposition)、原子层沉积(ALD;Atomic LayerDeposition)、化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、预清洁、化学清洁、热处理(诸如RTP)、等离子体氮化、脱气、取向、羟化和其他基板工艺。通过在组合工具上的腔室中执行工艺,可避免具有大气杂质的基板的表面污染,而无需在沉积后续膜之前氧化。
根据一个或多个实施方式,基板持续在真空或者说是“负载锁定”状况下,并且当从一个腔室移动到下一腔室时不暴露于环境空气。传送腔室因此在真空下并在真空压力下被“抽气”。惰性气体可以存在于处理腔室或传送腔室中。在一些实施方式中,惰性气体用作净化气体以将一些或所有的反应物去除。根据一个或多个实施方式,在沉积腔室的出口处注入净化气体以防止反应物从沉积腔室移动到传送腔室和/或另外的处理腔室。由此,惰性气流在腔室出口处形成气帘。
基板可以在单个基板沉积腔室中进行处理,在单个基板沉积腔室中,在另一基板进行处理前装载、处理和卸载单个基板。基板也可类似于传送机系统以连续方式进行处理,其中多个基板被分别地装载到腔室的第一部分中,移动通过腔室,并且从腔室的第二部分卸载。腔室和相关联的传送机系统的形状可以形成笔直路径或弯曲路径。另外,处理腔室也可以是转盘(carousel),其中多个基板围绕中心轴线移动并且在整个转盘路径中都暴露于沉积、蚀刻、退火、清洁等工艺。
在处理工艺期间,可加热或冷却基板。这种加热或冷却可通过任何合适的手段来完成,包括但不限于改变基板支撑件的温度和使加热气体或冷却气体流向基板表面。在一些实施方式中,基板支撑件包括加热器/冷却器,所述加热器/冷却器可被控制从而以传导方式改变基板温度。在一个或多个实施方式中,所用气体(反应气体或惰性气体)被加热或冷却以使基板温度局部改变。在一些实施方式中,加热器/冷却器邻近基板表面定位在腔室内,从而以对流方式改变基板温度。
基板也可在处理期间静止或旋转。旋转的基板可连续地或以分立步骤进行旋转。例如,基板可以在整个工艺中一直旋转,或基板可在暴露于不同的反应气体或净化气体的操作之间小幅度地旋转。在处理期间旋转基板(连续地或逐步地)可有助于通过使例如气流几何形状的局部变化的效应最小化来产生更均匀的沉积或蚀刻。
在本说明书全文中提到“一个实施方式”、“某些实施方式”、“一个或多个实施方式”或“实施方式”表示,结合实施方式描述的特定特征、结构、材料或特性包括在本公开内容的至少一个实施方式中。因此,本说明书全文各处出现短语诸如“在一个或多个实施方式中”、“在某些实施方式中”、“在一个实施方式中”或“在实施方式中”不一定指本公开内容的同一实施方式。此外,特定特征、结构、材料或特性可以任何合适的方式结合在一个或多个实施方式中。
虽然本公开内容在本文中已经参考特定实施方式来进行描述,但应理解,这些实施方式仅说明了本公开内容的原理和应用。本领域的技术人员将会清楚,在不背离本公开内容的精神和范围的情况下,可对本公开内容的方法和设备做出各种修改和变化。因此,本公开内容将旨在包括在所附的权利要求书和它们的等效物的范围内的修改和变化。
Claims (20)
1.一种处理方法,所述处理方法包括:
向基板表面提供图案化膜,所述图案化膜形成至少一个特征,所述至少一个特征从所述图案化膜的顶表面向底表面延伸一定深度,所述至少一个特征具有由第一侧壁和第二侧壁限定的宽度;
在所述图案化膜上沉积膜以填充所述至少一个特征并在所述图案化膜的所述顶表面上方延伸;
使所述膜凹入来使所述膜的顶部降低到等于或低于所述图案化膜的所述顶表面的高度以形成凹入膜;
将所述凹入膜转化为钨膜;和
使所述钨膜膨胀以形成从所述至少一个特征延伸的支柱。
2.如权利要求1所述的方法,其中所述膜包含非晶硅。
3.如权利要求2所述的方法,其中沉积所述膜包括将所述基板暴露于包含甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种的前驱物。
4.如权利要求3所述的方法,其中沉积所述膜在范围为约300℃至约550℃的温度下进行。
5.如权利要求4所述的方法,其中沉积所述膜在范围为约10T至约600T的压力下进行。
6.如权利要求5所述的方法,其中沉积所述膜在没有所述前驱物的共反应物的情况下进行。
7.如权利要求3所述的方法,其中沉积所述膜在范围为约-100℃至约50℃的温度下进行。
8.如权利要求7所述的方法,其中沉积所述膜在范围为约1T至约10T的压力下进行。
9.如权利要求8所述的方法,其中沉积所述膜用具有范围为约10W至约200W的功率的RF等离子体进行。
10.如权利要求9所述的方法,其中沉积所述膜在没有所述前驱物的共反应物的情况下进行。
11.如权利要求1所述的方法,其中使所述膜凹入包括蚀刻所述膜。
12.如权利要求11所述的方法,其中蚀刻所述膜包括使用溴基蚀刻剂的反应离子蚀刻工艺。
13.如权利要求11所述的方法,其中使所述膜凹入包括将所述膜暴露于氢等离子体或氢自由基。
14.如权利要求1所述的方法,其中将所述凹入膜转化为钨膜包括将所述凹入膜暴露于WF6。
15.如权利要求14所述的方法,其中暴露于WF6在范围为约300℃至约550℃的温度和范围为约10T至约100T的压力下进行。
16.如权利要求15所述的方法,其中大体上整个的所述凹入膜都转化为钨。
17.如权利要求1所述的方法,其中使所述钨膜膨胀包括使所述钨膜氧化。
18.如权利要求17所述的方法,其中所述支柱从所述特征大体上笔直地向上延伸。
19.一种处理方法,所述处理方法包括:
向基板表面提供图案化膜,所述图案化膜形成至少一个特征,所述至少一个特征从顶表面向底表面延伸一定深度,所述至少一个特征具有由第一侧壁和第二侧壁限定的宽度;
将所述基板表面暴露于包含甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种的硅前驱物,来通过热解在所述基板表面上沉积非晶硅膜以填充所述至少一个特征并在所述基板表面上方延伸;
用氢等离子体或氢自由基蚀刻所述非晶硅膜,使所述非晶硅膜凹入来使所述膜的顶部降低到等于或低于所述图案化膜的所述顶表面的高度以形成凹入非晶硅膜;
将所述凹入非晶硅膜暴露于钨前驱物来与所述凹入非晶硅膜反应,以将大体上整个的所述凹入非晶硅膜都转化为钨膜;和
使所述钨膜氧化来使所述钨膜膨胀以形成从所述至少一个特征大体上笔直地向上延伸的钨支柱。
20.一种处理方法,所述处理方法包括:
向基板表面提供图案化膜,所述图案化膜形成至少一个特征,所述至少一个特征从顶表面向底表面延伸一定深度,所述至少一个特征具有由第一侧壁和第二侧壁限定的宽度;
将所述基板表面暴露于包含甲硅烷、乙硅烷、丙硅烷或丁硅烷中的一种或多种的硅前驱物,来通过热解在所述基板表面上沉积非晶硅膜以填充所述至少一个特征并在所述图案化膜的所述顶表面上方延伸,所述热解在没有硅共反应物的情况下、并且在不用等离子体的情况下在范围为约300℃至约550℃的温度下或在用等离子体的情况下在范围为约-100℃至约50℃的温度下进行;
用氢等离子体或氢自由基蚀刻所述非晶硅膜,使所述非晶硅膜凹入来使所述膜的顶部降低到等于或低于所述图案化膜的所述顶表面的高度以形成凹入非晶硅膜;
在范围为约300℃至约550℃的温度下将所述凹入非晶硅膜暴露于包含WF6的钨前驱物,来与所述凹入非晶硅膜反应以将大体上整个的所述凹入非晶硅膜都转化为钨膜;和
使所述钨膜氧化来使所述钨膜膨胀,以形成从所述至少一个特征大体上笔直地向上延伸的钨支柱。
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Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4948755A (en) * | 1987-10-08 | 1990-08-14 | Standard Microsystems Corporation | Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition |
US6040242A (en) * | 1996-02-28 | 2000-03-21 | Nec Corporation | Method of manufacturing a contact plug |
TW406370B (en) * | 1998-12-19 | 2000-09-21 | Vanguard Int Semiconduct Corp | Process of PECVD tungsten and tungsten compound deposition |
US20010012224A1 (en) * | 1995-12-22 | 2001-08-09 | Schuegaraf Klaus F. | Rugged metal electrodes for metal-insulator-metal capacitors |
US20010031539A1 (en) * | 1999-02-19 | 2001-10-18 | Stefan Uhlenbrock | Solutions of metal-comprising materials, and methods of making solutions of metal-comprising materials |
US20020105084A1 (en) * | 1998-09-03 | 2002-08-08 | Weimin Li | Low dielectric constant material for integrated circuit fabrication |
CN1396647A (zh) * | 2001-06-21 | 2003-02-12 | 联华电子股份有限公司 | 一种具有高抗张强度阻障层的形成方法 |
US6987961B1 (en) * | 2004-06-28 | 2006-01-17 | Neomagic Corp. | Ethernet emulation using a shared mailbox between two processors in a feature phone |
US20060051959A1 (en) * | 2004-09-09 | 2006-03-09 | International Business Machines Corporation | Dual silicide via contact structure and process |
CN1813345A (zh) * | 2003-02-17 | 2006-08-02 | 阿尔齐默股份有限公司 | 表面涂布的方法、用该方法在微电子器件中制造互连的方法,以及集成电路 |
US20070026671A1 (en) * | 2005-07-13 | 2007-02-01 | Samsung Electronics Co., Ltd. | Method of forming low resistance tungsten films |
CN101924062A (zh) * | 2009-05-26 | 2010-12-22 | 旺宏电子股份有限公司 | 一种存储器装置及用于制造一集成电路装置的方法 |
US20120299072A1 (en) * | 2011-05-24 | 2012-11-29 | Wan-Don Kim | Semiconductor device having metal plug and method of forming the same |
CN104051335A (zh) * | 2013-03-15 | 2014-09-17 | 格罗方德半导体公司 | 形成导电铜结构的阻障层的方法 |
CN105336662A (zh) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US9484251B1 (en) * | 2015-10-30 | 2016-11-01 | Lam Research Corporation | Contact integration for reduced interface and series contact resistance |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62298110A (ja) * | 1986-06-18 | 1987-12-25 | Matsushita Electric Ind Co Ltd | 半導体集積回路の製造方法 |
JPH0290518A (ja) * | 1988-09-28 | 1990-03-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH06112155A (ja) * | 1992-09-25 | 1994-04-22 | Matsushita Electron Corp | コンタクトプラグ形成方法 |
JPH0794491A (ja) * | 1993-09-22 | 1995-04-07 | Hiroshi Nagayoshi | ドライエッチング方法およびドライエッチング処理装置 |
JP3014019B2 (ja) * | 1993-11-26 | 2000-02-28 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH0837145A (ja) * | 1994-07-26 | 1996-02-06 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US5872052A (en) * | 1996-02-12 | 1999-02-16 | Micron Technology, Inc. | Planarization using plasma oxidized amorphous silicon |
KR100304962B1 (ko) * | 1998-11-24 | 2001-10-20 | 김영환 | 텅스텐비트라인형성방법 |
KR100351238B1 (ko) * | 1999-09-14 | 2002-09-09 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조 방법 |
TW457684B (en) * | 2000-10-11 | 2001-10-01 | Promos Technologies Inc | Manufacturing method of tungsten plug |
WO2002080244A2 (en) * | 2001-02-12 | 2002-10-10 | Asm America, Inc. | Improved process for deposition of semiconductor films |
US7540920B2 (en) * | 2002-10-18 | 2009-06-02 | Applied Materials, Inc. | Silicon-containing layer deposition with silicon compounds |
KR100680946B1 (ko) * | 2004-04-28 | 2007-02-08 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 플러그 형성방법 |
TWI234288B (en) * | 2004-07-27 | 2005-06-11 | Au Optronics Corp | Method for fabricating a thin film transistor and related circuits |
KR101534678B1 (ko) | 2009-02-12 | 2015-07-08 | 삼성전자주식회사 | 텅스텐 콘택 플러그를 산소 분위기에서 rta 처리하고, rto 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법 |
US8575753B2 (en) | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
US8535760B2 (en) * | 2009-09-11 | 2013-09-17 | Air Products And Chemicals, Inc. | Additives to silane for thin film silicon photovoltaic devices |
JP5511308B2 (ja) * | 2009-10-26 | 2014-06-04 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5696530B2 (ja) * | 2010-05-01 | 2015-04-08 | 東京エレクトロン株式会社 | 薄膜の形成方法及び成膜装置 |
US8048782B1 (en) * | 2010-08-12 | 2011-11-01 | Ovshinsky Innovation Llc | Plasma deposition of amorphous semiconductors at microwave frequencies |
KR102064627B1 (ko) * | 2012-03-27 | 2020-01-09 | 노벨러스 시스템즈, 인코포레이티드 | 텅스텐 피처 충진 |
JP6297884B2 (ja) * | 2014-03-28 | 2018-03-20 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
US9716097B2 (en) * | 2015-01-14 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Techniques to avoid or limit implant punch through in split gate flash memory devices |
JP6078604B2 (ja) * | 2015-09-24 | 2017-02-08 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理方法、基板処理装置およびガス供給系 |
TWI687978B (zh) | 2016-11-08 | 2020-03-11 | 美商應用材料股份有限公司 | 用於圖案化應用之由下而上的柱體之幾何控制 |
-
2018
- 2018-05-02 KR KR1020180050715A patent/KR20180122297A/ko not_active Application Discontinuation
- 2018-05-02 JP JP2018088620A patent/JP2018199863A/ja active Pending
- 2018-05-02 CN CN201810410364.5A patent/CN108807264B/zh active Active
- 2018-05-02 TW TW110135272A patent/TWI780922B/zh active
- 2018-05-02 CN CN202311135956.8A patent/CN116978862A/zh active Pending
- 2018-05-02 TW TW107114805A patent/TWI757478B/zh active
- 2018-05-02 US US15/969,119 patent/US10784107B2/en active Active
-
2020
- 2020-09-22 US US17/028,984 patent/US20210013038A1/en not_active Abandoned
-
2022
- 2022-11-22 JP JP2022186147A patent/JP2023029868A/ja active Pending
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4948755A (en) * | 1987-10-08 | 1990-08-14 | Standard Microsystems Corporation | Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition |
US20010012224A1 (en) * | 1995-12-22 | 2001-08-09 | Schuegaraf Klaus F. | Rugged metal electrodes for metal-insulator-metal capacitors |
US6040242A (en) * | 1996-02-28 | 2000-03-21 | Nec Corporation | Method of manufacturing a contact plug |
US20020105084A1 (en) * | 1998-09-03 | 2002-08-08 | Weimin Li | Low dielectric constant material for integrated circuit fabrication |
TW406370B (en) * | 1998-12-19 | 2000-09-21 | Vanguard Int Semiconduct Corp | Process of PECVD tungsten and tungsten compound deposition |
US20010031539A1 (en) * | 1999-02-19 | 2001-10-18 | Stefan Uhlenbrock | Solutions of metal-comprising materials, and methods of making solutions of metal-comprising materials |
CN1396647A (zh) * | 2001-06-21 | 2003-02-12 | 联华电子股份有限公司 | 一种具有高抗张强度阻障层的形成方法 |
CN1813345A (zh) * | 2003-02-17 | 2006-08-02 | 阿尔齐默股份有限公司 | 表面涂布的方法、用该方法在微电子器件中制造互连的方法,以及集成电路 |
US6987961B1 (en) * | 2004-06-28 | 2006-01-17 | Neomagic Corp. | Ethernet emulation using a shared mailbox between two processors in a feature phone |
US20060051959A1 (en) * | 2004-09-09 | 2006-03-09 | International Business Machines Corporation | Dual silicide via contact structure and process |
US20070026671A1 (en) * | 2005-07-13 | 2007-02-01 | Samsung Electronics Co., Ltd. | Method of forming low resistance tungsten films |
CN101924062A (zh) * | 2009-05-26 | 2010-12-22 | 旺宏电子股份有限公司 | 一种存储器装置及用于制造一集成电路装置的方法 |
US20120299072A1 (en) * | 2011-05-24 | 2012-11-29 | Wan-Don Kim | Semiconductor device having metal plug and method of forming the same |
CN104051335A (zh) * | 2013-03-15 | 2014-09-17 | 格罗方德半导体公司 | 形成导电铜结构的阻障层的方法 |
CN105336662A (zh) * | 2014-05-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US9484251B1 (en) * | 2015-10-30 | 2016-11-01 | Lam Research Corporation | Contact integration for reduced interface and series contact resistance |
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CN108807264B (zh) | 2023-09-12 |
TW202207278A (zh) | 2022-02-16 |
TW201843708A (zh) | 2018-12-16 |
JP2018199863A (ja) | 2018-12-20 |
TWI757478B (zh) | 2022-03-11 |
CN116978862A (zh) | 2023-10-31 |
US20180323068A1 (en) | 2018-11-08 |
KR20180122297A (ko) | 2018-11-12 |
US20210013038A1 (en) | 2021-01-14 |
TWI780922B (zh) | 2022-10-11 |
JP2023029868A (ja) | 2023-03-07 |
US10784107B2 (en) | 2020-09-22 |
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