CN1087751A - 在集成电路中形成隔离的方法和结构 - Google Patents
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Abstract
在集成电路中形成电隔离的方法和结构。利用
氮化硅场氧化掩模(18)之下的热生长二氧化硅和化
学汽相淀积的二氧化硅叠层(14)实现无缺陷的场氧
化隔离。该二氧化硅的叠层(14)形成在硅衬底(12)
上,然后再在其上淀积一层氮化硅。继而将氮化硅光
刻成型,以形成在硅衬底(12)上限定隔离区(22)的场
氧化掩模(18)。在硅衬底(12)的隔离区(22)上生长场
氧化物(34),接着除去场氧化掩模(18)。
Description
本发明涉及半导体器件,更具体地说,涉及在半导体集成电路中形成电隔离结构的工艺过程。
硅的局部氧化(LOCOS)是硅集成电路中最常用的隔离技术。遗憾的是,LOCOS本身具有大的场氧化侵蚀(field oxide enuroachment),这妨碍该技术被用于需要高的器件封装密度的先进的集成电路。在标准的LOCOS工艺中,在硅片表面热生长一薄层衬垫氧化物(pad oxide)。然后在衬垫氧化物上淀积一氮化硅层。在此氮化硅层上制作光刻图形,并进行腐蚀,以限定出隔离区和有源区。再在隔离区生长场氧化物,而用氮化硅层的图形作掩模防止有源区上发生氧化过程。然而,进行场氧化之后得到的有源区的面积比实际想要的、由氮化硅层的图形所限定的面积要小。这是因为氧通过衬垫氧化物层在氮化硅图形掩模之下横向扩散,并与其下的硅表面反应而造成的。因此,场氧化不仅形成在隔离区域内,还侵蚀了邻近的有源区域。结果被限制了有源区的尺寸,所以用标准的LOCOS隔离不能获得具有高的器件封装密度的集成电路。
为了减少场氧化物的侵蚀,已提出了几种与LOCOS类似的隔离技术。一种方法是在氮化硅氧化掩模之下切割衬垫氧化层,以形成一凹槽。之后,用共形的多晶硅层填满此凹槽。在场氧化期间,填满多晶硅的凹槽起扩散壁垒的作用,从而防止氧从氮化硅氧化掩模之下传输到硅表面。遗憾的是,填满多晶硅的凹槽不是一个理想的扩散壁垒。因此,在氧化掩模边缘部分的硅表面上仍然发生氧化,结果,有源区仍然受到场氧化物的侵蚀。
第二种方法中用氮化硅的共形层来填满凹槽,其后进行各向异性腐蚀以在填满氮化硅的凹槽旁边形成一侧壁阻挡层。在形成场氧化物期间,填满氮化硅的凹槽以及氮化硅侧壁阻挡层两者均起到扩散壁垒的作用,防止氧传输到氧化掩模的边缘部分之下的硅表面处。但是,使用这种方法很难均匀地控制场氧化侵蚀。侧壁阻挡层的形成工艺需要相对于下面的氧化掩模有选择地腐蚀氮化硅。而在这些隔离方案中以用氮化硅作氧化掩模为主。因此,由于氮化硅腐蚀速率及阻挡层厚度的差异,使氮化硅氧化掩膜受到不均匀的腐蚀,导致在晶片内以及晶片与晶片间氧化掩膜的厚度是不均匀的。由于场氧化侵蚀强烈地依赖于氧化掩模的厚度,因此导致对有源区的侵蚀也在晶片内以及晶片与晶片之间各有不同。此外,侧壁阻挡层形成工艺也减小了隔离区的几何尺寸。因此,已知在几何尺寸小的隔离区中发生的场氧化物变薄的现象由于氮化硅侧壁阻挡层的存在而加重了。所以,使用这种隔离技术时,器件的尺寸由于场氧化层变薄而进一步受到限制。因此,对于一种隔离工艺而言,需要有效和可重复地降低场氧化侵蚀和尽量减少场氧化层变薄的现象。
本发明克服了现有的隔离工艺中存在的上述问题。在本发明的一个实施例中,通过提供一半导体衬底形成一集成电路器件。在该衬底上形成第一缓冲层,在第一缓冲层上形成一掩模层。将掩模层刻出图形以形成一个缓冲层的暴露部分,并限定出衬底的隔离区。刻图形工序在衬底上还留下一部分掩模层。腐蚀缓冲层被暴露出的部分,以在留下的那部分掩模层边缘部分之下形成凹槽。该腐蚀工序也形成了一部分暴露出的衬底,并在衬底上留下了缓冲层的保留部分。在衬底暴露部分之上形成第二缓冲层。在留下的那部分掩模层及第二缓冲层上形成氮化物层。该氮化物层充满凹槽。氧化该氮化物层以形成一氧化层,并在衬底的隔离区形成电隔离。
从下面结合附图的详细说明可以更清楚地理解本发明的这些和其它特征,以及优点。指出这一点是重要的,即,图例不一定是按比例画的,本发明可能还有其它的没有在此作具体图示的实施例。
图1至图7用截面图的形式说明本发明一个实施例的工艺步骤,在这几个图中,相同的参考号表示同一个或相应的部件。
图1至图7为本发明在集成电路中形成电隔离结构的一个实施例的工序步骤的剖面图。图1所示为集成电路结构的一部分10,包括半导体衬底12、第一缓冲层14和掩模层16。衬底12最好是单晶硅,也可以是绝缘体上的硅,或在蓝宝石上的硅等。最好将衬底12热氧化,以形成第一缓冲层14,其厚度范围为5-100毫微米。第一缓冲层14也可以是化学汽相淀积的二氧化硅,或热氧化生长和化学汽相淀积的二氧化硅的叠层。第一缓冲层14形成之后,在其上形成掩模层16。掩模层16最好是化学汽相淀积的氮化硅,其厚度可以在50-300毫微米的范围内。掩模层16也可以是覆盖在多晶硅或氮氧化合物之类的其它材料上的氮化硅的叠层。
图2中,用常规的光刻成形和腐蚀技术,使掩模层16形成图形,留下掩模层16的保留部分18覆盖在衬底12上。该成形工序还暴露出缓冲层14的一部分20,限定出衬底12的隔离区22。此外,在该成形工序之后,可以用扩散或注入步骤对隔离区22进行掺杂。
如图3所示,有选择并各向同性地腐蚀缓冲层14的暴露出的部分20,以在保留部分18的边缘部分之下形成凹槽24。该腐蚀工序在衬底12上留下了缓冲层14的保留部分25,并形成了衬底12的暴露部分26。最好用湿式腐蚀剂,如氢氟酸,来腐蚀暴露出的部分20,形成凹槽24。也可以用其它常规的各向同性的腐蚀技术,如汽相腐蚀或化学下游等离子体腐蚀(chemical downstream plasma etching),来腐蚀暴露部分20。
按图4中的工序继续形成第二缓冲层28,覆盖在衬底12的暴露部分26上。缓冲层28最好是厚度小于25毫微米的二氧化硅,这是暴露部分26再次氧化而形成的。缓冲层28也可以是通过对暴露部分26进行氮化而形成的氮化硅或氮氧化硅层。例如,可以通过在含氮气氛(如氨或一氧化氮)中对暴露部分26快速退火来形成氮化硅或氮氧化硅。它们也可以通过在含氮气氛(如氨或一氧化氮)中用炉子对暴露部分26退火而形成。
在图5中,在保留部分18和第二缓冲层28上形成氮化物层30。如图5所示,氮化物层30填满了凹槽24。氮化物层30最好是厚度小于30毫微米的化学汽相淀积的氮化硅层,也可以是经过氮化而形成氮化物或氮氧化物的二氧化硅薄层或化学汽相淀积的氮氧化物薄层。例如,可以用化学汽相淀积法淀积一薄层二氧化硅,然后在氨气或一氧化氮气氛中进行快速退火,从而形成氮化物层30。此外,氮化物层30可以是等离子体淀积的氮化硅或氮氧化硅。
氮化物层30形成之后进行热氧化,如图6所示,在衬底12的绝缘区22内生长厚的电隔离氧化物34。在氧化过程中,氮化物层30完全被氧化形成了氧化层32。该氧化工序最好在氮和水蒸汽存在的情况下,在约900~1200℃的炉子中进行。
其后,用氢氟酸除去保留部分18之上的氧化层32。也可以其它常规的干法腐蚀或湿法腐蚀技术去除氧化层32,再如图7所示那样除去保留部分18和25。在一较佳实施例中,保留部分18用磷酸去除,保留部分25用氢氟酸去除。其它通用的干法或湿法腐蚀技术也可用于除去保留部分18或25。半导体器件可以形成在由隔离氧化物34分隔开的有源区36内。
上面的描述及图例说明了本发明的许多优点。其一是使用氮化硅充满凹槽,与多晶硅不同,氮化硅是良好的氧化壁垒。因此,将氧化掩模边缘部分之下的硅表面的氧化减至最小,结果,减小了场氧化对有源区的侵蚀。此外,在氧化氮化物层30时,光刻成形的氮化硅氧化掩模被致密化。因此,该工艺不需要单独的使氮化硅氧化掩模致密化的步骤。而且,通过穿透在衬底的隔离区之上的氮化硅层的氧化能够生长电学性能上可靠的场氧化物,尽管这不是十分明显的。出乎意料的是,氮化硅层的氧化均匀地发生,结果是形成了无针孔的场氧化物。因此不需要在形成场氧化物之前腐蚀氮化硅膜,其结果是能够在晶片内以及不同的晶片间均匀地控制对有源区的场氧化物侵蚀。
很显然,本发明提供了一种完全满足前面所述的需要和优点的形成氧化物隔离的方法。虽然已结合具体的实施例描述了本发明,但本发明并不局限于这些说明性的实施例。本领域的普通技术人员将认识到在不偏离本发明构思的情况下,可以进行许多改型和变更。例如,可以在形成缓冲层28之前在衬底12上开槽。而且,虽然图2中没有图示,缓冲层20也可以在光刻成形工序中被腐蚀。此外,大家都知道,也可以用富硅的氮氧化物和富硅的氮化硅作氮化物层30。已知改变这些膜中的硅浓度可改变它们的物理特性,如膜应力等。对于本发明这些物理特性可进行最优化。因此,本发明包括所附权利要求书范围内的所有变更和改型。
Claims (10)
1、一种在集成电路中形成隔离结构(34)的方法,其特征在于下列步骤:
提供一具有一主表面的半导体衬底(12);
形成覆盖在半导体衬底(12)主表面上的热生长和淀积的二氧化硅的叠层(14);
形成覆盖在叠层(14)上的氧化掩模层(16);
对氧化掩模层(16)进行光刻成形,留下氧化掩模层(16)的保留部分(18)覆盖在半导体衬底(12)上,限定出半导体衬底(12)的隔离区(22);
在半导体衬底(12)的隔离区(22)形成电隔离结构(34);
除去氧化掩模层(16)的保留部分(18)。
2、如权利要求1的方法,其中,形成氧化掩模层(16)的步骤的特征是淀积一层氮化硅层。
3、如权利要求2的方法,其特征在于:
在淀积氮化硅层之前先在叠层(14)上淀积一层多晶硅层。
4、如权利要求1的方法,其特征在于还包括下列步骤:
在氧化掩模层(16)的保留部分(18)的边缘部位之下形成凹槽(24);以及
在氧化掩模层(16)的保留部分(18)和隔离区(22)之上形成氮化硅层,该氮化硅层填满凹槽。
5、如权利要求的方法,其中,形成电隔离结构(34)的步骤的进一步特征是氧化隔离区(22)之下的半导体衬底(12)的一部分。
6、如权利要求1的方法,其中,除去氧化掩模层(16)的保留部分(18)的步骤的进一步特征是用干法腐蚀除去保留部分(18)。
7、如权利要求1的方法,其中,除去氧化掩膜层(16)的保留部分(18)的步骤的进一步特征是用湿法腐蚀除去保留部分(18)。
8、一种在集成电路中形成电隔离结构(34)的方法,其特征在于下列步骤:
提供具有一主表面的半导体衬底(12);
在半导体衬底(12)的主表面上生长第一层热生长二氧化硅;
在第一层热生长二氧化硅上淀积第二层二氧化硅;
在第二层二氧化硅上形成氮化硅层(16);
使氮化硅层(16)光刻成形以限定出半导体衬底(12)上的隔离区(22),并留下氮化硅层(16)的保留部分(18)覆盖在半导体衬底(12)上;
氧化隔离区(22)之下的那部分半导体衬底(12),以形成场氧化区;以及
除去氮化硅层(16)的保留部分(18)。
9、如权利要求8的方法,进一步包括下列步骤:
在淀积氮化硅层(16)之前,在第二层二氧化硅上形成一多晶硅层。
10、如权利要求8的方法,其中,除去氮化硅层(16)的保留部分(18)的步骤是用干法腐蚀进行的。
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US984,792 | 1992-12-03 | ||
US07/984,792 US5236862A (en) | 1992-12-03 | 1992-12-03 | Method of forming oxide isolation |
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CN1087751A true CN1087751A (zh) | 1994-06-08 |
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CN93118940A Pending CN1087751A (zh) | 1992-12-03 | 1993-10-15 | 在集成电路中形成隔离的方法和结构 |
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US (1) | US5236862A (zh) |
EP (1) | EP0600176A1 (zh) |
KR (1) | KR100278729B1 (zh) |
CN (1) | CN1087751A (zh) |
Cited By (1)
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CN101924059A (zh) * | 2009-06-13 | 2010-12-22 | 无锡华润上华半导体有限公司 | 一种场氧化隔离制造方法 |
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JPH06216120A (ja) * | 1992-12-03 | 1994-08-05 | Motorola Inc | 集積回路の電気的分離構造の形成方法 |
US5352618A (en) * | 1993-07-30 | 1994-10-04 | Atmel Corporation | Method for forming thin tunneling windows in EEPROMs |
BE1007588A3 (nl) * | 1993-09-23 | 1995-08-16 | Philips Electronics Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam met veldisolatiegebieden gevormd door met isolerend materiaal gevulde groeven. |
KR970003893B1 (ko) * | 1993-10-25 | 1997-03-22 | 삼성전자 주식회사 | 반도체 장치의 소자 분리 방법 |
US5369052A (en) * | 1993-12-06 | 1994-11-29 | Motorola, Inc. | Method of forming dual field oxide isolation |
US5472906A (en) * | 1993-12-08 | 1995-12-05 | Matsushita Electric Industrial Co., Ltd. | Method of forming isolation |
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KR970006269B1 (ko) * | 1994-05-03 | 1997-04-25 | 엘지반도체 주식회사 | 전하결합 소자 제조방법 |
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JP3304621B2 (ja) * | 1994-07-29 | 2002-07-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
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-
1992
- 1992-12-03 US US07/984,792 patent/US5236862A/en not_active Expired - Fee Related
-
1993
- 1993-09-17 KR KR1019930018782A patent/KR100278729B1/ko not_active IP Right Cessation
- 1993-09-24 EP EP93115427A patent/EP0600176A1/en not_active Withdrawn
- 1993-10-15 CN CN93118940A patent/CN1087751A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101924059A (zh) * | 2009-06-13 | 2010-12-22 | 无锡华润上华半导体有限公司 | 一种场氧化隔离制造方法 |
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KR100278729B1 (ko) | 2001-01-15 |
EP0600176A1 (en) | 1994-06-08 |
KR940016682A (ko) | 1994-07-23 |
US5236862A (en) | 1993-08-17 |
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