CN108604555B - 用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方法、相应的衬底布置及其制造方法 - Google Patents

用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方法、相应的衬底布置及其制造方法 Download PDF

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CN108604555B
CN108604555B CN201680059144.1A CN201680059144A CN108604555B CN 108604555 B CN108604555 B CN 108604555B CN 201680059144 A CN201680059144 A CN 201680059144A CN 108604555 B CN108604555 B CN 108604555B
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substrate
contact material
layer
electronic component
coated
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CN108604555A (zh
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A·欣里希
S·杜赫
A·米里奇
M·舍费尔
C·巴赫曼
H·乌尔里希
F·奥斯特瓦尔德
D·本宁
J·鲁茨基
L·保尔森
F·舍富斯
M·贝克尔
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Heraeus Deutschland GmbH and Co KG
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Abstract

本发明涉及一种用于制造用以连接到电子组件(30)的衬底布置(10；10")的方法，包含以下步骤：‑提供具有第一侧面(12)和第二侧面(13)的衬底(11)；‑将接触材料层(15)涂覆到所述衬底(11)的所述第一侧面(12)；以及‑将预固剂(18)涂覆到背离所述衬底(11)的所述接触材料层(15)的侧面(16)的至少一些部分。本发明也涉及一种相应的衬底布置(10；10")以及一个用于将至少一个电子组件(30)连接到所述衬底布置(10；10")的相应的方法，本发明的技术手段在从组装地点到连接地点的运输过程中可提供足够的操作强度。

Description

用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方 法、相应的衬底布置及其制造方法
本发明涉及一种用于制造用以附接到电子组件的衬底布置的方法。本发明进一步涉及用于附接到电子组件的衬底布置。本发明还涉及用于将电子组件附接到衬底布置的方法。
在电力电子中已知提供具有预涂覆接触剂，如预干燥烧结膏、焊料、导电粘着剂的衬底或组件。在顾客地点处的制造过程期间，有可能的是组件可能在从组合件位置传输到烧结位置期间滑动，尤其是用预涂覆接触剂，尤其用预干燥烧结膏粘结到衬底的电子组件。
在此情形下，众所周知在同时施加热量的同时将组件，尤其电子组件放置在干燥烧结膏上。已发现对于许多电子组件而言，这一类型的加热组合件并未确保充足的传输稳定性，因为弯曲组件和/或变脏表面和/或笨拙的表面几何形状，或传输期间的极高加速力导致粘着不足以承受从组合件位置到烧结位置的传输。因此，已知用遮罩或模塑固定电子组件，或在已将其组装之后但焊接和烧结或粘结之前采用复杂的弹簧系统将其夹在适当位置。
已知先前技术的另一缺陷是常常在保持与组件边缘距离的同时和/或用不均匀斜坡状结构的形式涂覆将在衬底上铺展的接触材料。使用已知方法利用接触材料进行全表面涂布是不可能的或仅在极有限的程度上可能，因为例如当喷射烧结膏时烧结膏经受特定需求，并且全表面涂布常常与显著的喷雾损失关联。
考虑到如所描述的目前先进技术，本发明的一个目的为描述用于制造用以附接到电子组件的衬底布置的方法，使得在将电子组件从组合件位置传输到烧结位置时保证充足的传输稳定性。另外，随着方法的进一步进展，应该有可能使用接触材料有效地涂布和产生最大的可能表面区域。应以使得接触材料尽可能延伸到所有侧面上的化合物的边缘的方式使组件与此表面区域分离。
本发明的另一目的为描述用于附接到电子组件的衬底布置，其中以使得已组装但尚未焊接或烧结或粘结的组件在衬底布置上足够稳定传输的方式实施衬底布置。出于确保衬底布置具有较大接触材料表面积的目的还提供另一进展。
本发明的另一目的为描述用于将电子组件附接到衬底布置的方法。
根据本发明，关于用于制造用以附接到电子组件的衬底布置的方法的目的用技术方案1的主题解决，关于衬底布置用技术方案11的主题解决，并且关于用于将电子组件附接到衬底布置的方法用技术方案16的主题解决。
本发明是基于以下构思：描述用于制造用以附接到电子组件的衬底布置的方法，所述方法包含以下步骤：
-提供具有第一侧面和第二侧面的衬底；
-将接触材料层涂覆到衬底的第一侧面；
-将预固剂至少涂覆到背对衬底的接触材料层的侧面的若干部分。
使用根据本发明的方法制造的衬底布置用于后续附接到电子组件。
衬底可以是金属片或一部分金属带，尤其为铜片或一部分铜带。进一步可能的是衬底是引线框或DCB衬底或PCB衬底。术语铜片还理解为涉及由铜合金材料组成的金属片。铜带部分可以是此类由铜合金材料组成的带部分。
金属片或金属带部分，尤其铜片或铜带部分优选地不经预结构化。必要的可能仅是将待使用的衬底切割到一定长度和/或使其侧边缘结构化。
待制备的衬底或衬底坯料可经涂布，尤其在至少一个侧面上用包含金(Au)或镍-金(NiAu)或银(Ag)或镍-银(NiAg)或镍-钯-金(NiPdAu)的材料镀锌。进一步可能的是通过化学电镀将材料涂覆到衬底或衬底坯料的至少一个侧面。
待制备的衬底或衬底坯料可以优选地经涂布，尤其用所描述的材料至少涂布在其随后将接触的侧面上。还可设想的是待制造的衬底或衬底坯料的两个侧面可以涂布有所描述的材料。在本发明的一个实施例中，有可能的是在制备衬底之前，尤其在涂布过程之前使衬底与(所述)衬底坯料分离。衬底坯料可以是金属带或金属片，尤其为铜带或铜片。还可能的是衬底坯料是由铜合金制得的带或片。
有可能的是全表面金属带，尤其铜带经提供并镀锌在一个侧面、不断地在一个侧面、尤其不断地在一个侧面上。或者，有可能的是使衬底与衬底坯料、尤其与金属带、尤其与铜带分离并且例如在镀锌机架中独立地镀锌。
将接触材料层涂覆到衬底的第一侧面，所述第一侧面可以是例如经涂布侧面或相对经涂布侧面的衬底的侧面。应优选地将接触材料层涂覆到衬底的第一侧面的整个表面，或近似整个表面。可以将至少一个衬底定位在用于涂覆接触材料层的工作座中。有可能的是将多个衬底定位在工作座中。进一步有可能的是以喷雾方法将用于形成接触材料层的接触材料涂覆到衬底的第一侧面。刮浆刀方法也是有可能的。
接触材料是烧结膏，尤其是含银烧结膏，或焊料或导电粘着剂或粘着膜，其用于衬底到电子组件的实际附接。预固剂仅用以预固定，也就是用于将衬底临时粘附到电子组件或将电子组件临时粘附到衬底。预固定或临时固定提供足够的稳定性从而能够实现将组件从组合件位置传输到烧结位置。预固剂是临时固定剂。换句话说，预固剂是能够使得将衬底布置或衬底临时粘附到电子组件的固定剂。
将预固剂至少涂覆到背对衬底的接触材料层的侧面的若干部分。可以例如通过喷淋、滴流、喷雾、分配、喷射或借助于转移方法将预固剂涂覆到接触材料层。
因为直接将预固剂涂覆到接触材料层，所以不必另外用预固定构件提供衬底。换句话说，衬底的所有部分均不必保持准备预固剂的涂覆，或保持不含接触材料层。这就衬底材料而言导致材料节省。涂覆到衬底的接触材料层可具有10-150μm、尤其30-100μm、更尤其40-80μm的层厚度。
涂覆到衬底的接触材料层和涂覆到接触材料层的预固剂优选地在将其涂覆之后干燥。
在已涂覆接触材料层之后，衬底优选地不具有侧边缘。在此情况下，衬底的整个表面覆盖有接触材料层。还有可能的是衬底可具有上面未涂覆接触材料层的侧边缘，其中所述边缘的此类宽度尤其占不超过衬底总宽度的20％、尤其不超过衬底总宽度的10％、更尤其不超过衬底总宽度的5％、最尤其不超过衬底总宽度的1％。
因此，甚至在此方法阶段，当衬底涂布有接触材料时或当接触材料层在衬底上制造时，制造具有最小可能的不可用边缘的衬底适配器或衬底布置。换句话说，衬底的第一侧面提供有尽可能多的接触材料，使得可能产生最大的接触材料层。
涂覆到衬底的接触材料层和涂覆到接触材料层的预固剂优选地经干燥。换句话说，具有所涂覆接触材料层的衬底和涂覆在接触材料层顶部上的预固剂进行干燥过程。干燥可以用80-150℃的物体温度进行2-30min。如果进行干燥或预干燥，那么所涂覆预固剂的厚度和所涂覆接触材料层的厚度可能由于干燥和预干燥而减小。
在本发明的另一实施例中，可以衬底的第一侧面被布置成面向载体的方式将具有所涂覆接触材料层和所涂覆预固剂的衬底定位于载体上，其中预固剂和另外可能的接触材料层至少以粘附方式与载体粘结。因此可以包含衬底、预固剂、接触材料层和任选地载体的衬底布置可以传输到其它制造位置或另一器件以进一步处理的方式将衬底放置在载体上。有可能的是仅预固剂以粘附方式粘结到载体。例如在载体与接触材料层之间可能存在小间隙。
载体用以确保可以将衬底布置从第一制造位置传输到另一制造位置或从第一制造设备传输到另一制造设备。载体可以是例如载体膜，尤其是具有低粘合强度的载体膜。进一步可能的是拉伸UV胶带遍及晶圆框架以制造载体。提供有接触材料层和预固剂的衬底可以粘附方式附接到此UV胶带。
根据本发明的优选实施例，优选地呈附著至载体状态的衬底的一个/所述侧边缘的至少一部分可经拆离，和/或优选地呈附著至载体状态的衬底经结构化和/或分离。最终零件几何形状，也就是衬底适配器或衬底布置的最终几何形状因此可以通过在涂覆尤其呈附著至载体状态的接触材料层和预固剂之后产生。如果衬底的一个/所述侧边缘的若干部分，优选地全部与衬底布置的其余部分或衬底适配器的其余部分拆离，那么制造衬底适配器，其中衬底的第一侧面完全由接触材料层覆盖，或第一侧面的整个表面提供有接触材料层。移除衬底布置或衬底适配器的不可用边缘。
进一步可能的是多个衬底布置可以由最初较大的衬底布置通过分离产生。衬底的结构化为可能的，例如用于将衬底和衬底布置调适到待附接的组件的几何形状。
侧边缘的拆离和/或衬底的结构化和/或衬底的分离优选地用激光进行。极小的组件可以用激光切割方法加工。此外，极锋利的边缘可以借助于激光切割方法产生。
尤其当衬底处于与载体附接的状态时，接触材料层和/或预固剂的至少部分在侧边缘的拆离期间和/或衬底的结构化期间和/或衬底的分离期间也可经拆离和/或结构化和/或分离。如果接触材料层经拆离和/或结构化和/或分离，那么可以除去例如通过压制接触材料层形成的斜坡。此外，接触材料层的激光机械加工方法能够实现可能产生或制造的最平坦接触材料层。
衬底布置的后续激光切割或激光机械加工提供无限的成形能力，使得根据本发明的方法能够使得制造各种结构和组件组合。举例来说，可以将基底面积为180mm×180mm或190mm×190mm的接触材料层涂覆到尺寸为200mm×200mm的衬底。因此，在拆离侧边缘之后，可能制造尺寸高达190mm×190mm的衬底适配器，其中此类衬底的整个表面完全由接触材料层覆盖。
接触材料层的接触材料优选地包含辅助烧结剂和金属粒子，尤其银粒子。辅助烧结剂应理解为由有机化合物组成。接触材料可进一步包含粘合剂和/或脂肪酸。粘合剂尤其是如纤维素衍生物的聚合物，例如甲基纤维素、乙基纤维素、乙基甲基纤维素、羧基纤维素和羟丙基纤维素。
脂肪酸尤其可以是丙烯酸(辛酸)、羊蜡酸(癸酸)、月桂酸(十二烷酸)、肉豆蔻酸(十四烷酸)、棕榈酸(十六烷酸)、珍珠酸(十七烷酸)、硬脂酸(十八烷酸)、花生酸(二十烷酸(eicosanoic acid)/二十烷酸(icosanoic acid))、萝酸(二十二烷酸)、木蜡酸(二十四烷酸)。
因此，术语辅助烧结剂包含存在于接触材料中的脂肪酸和/或粘合剂和/或有机化合物。接触材料层中的接触材料优选地是烧结膏，尤其银烧结膏。预固剂优选地包含相同辅助烧结剂。金属粒子，尤其银粒子优选地不包含于预固剂中。
因为接触材料和预固剂优选地包含相同辅助烧结剂，所以在预固定期间或在预固剂涂覆到接触材料层时，接触材料层不以另一预固剂形式被污染。因此避免与接触材料层相关的不期望污染。
本发明进一步基于以下构思：描述用于附接到电子组件的衬底布置，其中衬底布置优选地用根据本发明的前述方法制造。根据本发明的衬底布置包含具有第一侧面和第二侧面的衬底，所述衬底尤其是金属片或金属带部分、优选地铜片或铜带部分、或引线框或DCB衬底或PCB衬底，其中将接触材料层涂覆到衬底的第一侧面的至少若干部分，其中将预固剂至少涂覆到背对衬底的接触材料层的侧面的若干部分。
在本发明的一优选实施例中，将接触材料层涂覆到衬底的第一侧面上的整个表面或近似整个表面。
接触材料层的接触材料包含辅助烧结剂和金属粒子，尤其银粒子。在本发明的一优选实施例中，预固剂包含相同辅助烧结剂。辅助烧结剂理解为由接触材料中的脂肪酸和/或粘合剂和/或有机化合物组成。
粘合剂尤其是如纤维素衍生物的聚合物，例如甲基纤维素、乙基纤维素、乙基甲基纤维素、羧基纤维素和羟丙基纤维素。
脂肪酸可以尤其是丙烯酸(辛酸)、羊蜡酸(癸酸)、月桂酸(十二烷酸)、肉豆蔻酸(十四烷酸)、棕榈酸(十六烷酸)、十七烷酸(margaric acid)(十七烷酸(heptadecanoicacid))、硬脂酸(十八酸)、花生酸(二十烷酸(eicosanoic acid)/二十烷酸(icosanoicacid))、萝酸(二十二烷酸)、木蜡酸(二十四烷酸)。
衬底的至少一个侧面经涂布，尤其用包含金(Au)或镍-金(NiAu)或银(Ag)或镍-银(NiAg)或镍-钯-金(NiPdAu)的材料镀锌。还可能的是通过化学电镀将所描述的材料沉积在衬底的至少一个侧面上。
在另一实施例中，衬底布置包括尤其实施为载体膜的载体，其中载体至少以粘附方式与预固剂粘结。有可能的是，接触材料的至少若干部分还以粘附方式粘结到载体。以使得衬底的第一侧面被布置成面向载体的方式相对于载体配置衬底。载体用以能够使得可以将衬底布置从第一制造位置传输到另一制造位置或从第一制造设备传输到另一制造设备。载体可以是例如具有低粘合强度的载体膜。还可能的是载体是UV胶带。
在本发明的特别优选的实施例中，衬底的第一侧面的整个表面由接触材料层覆盖。在本发明的另一实施例中，有可能的是衬底可具有上面未涂覆接触材料层的侧边缘，其中所述边缘的此类宽度尤其占不超过衬底总宽度的20％、尤其不超过衬底总宽度的10％、更尤其不超过衬底总宽度的5％、最尤其不超过衬底总宽度的1％。
关于衬底布置的结构，尤其关于根据本发明的衬底布置的优势，特别提及的是先前备注和解释与根据本发明的方法结合。
本发明进一步基于以下构思：描述用于将电子组件附接到衬底布置的方法。衬底布置可以尤其是根据本发明的衬底布置和/或使用根据本发明的所描述方法制造的衬底布置。用于将电子组件附接到衬底布置的根据本发明的方法包含以下步骤：
-以使得(所述)衬底的(所述)第一侧面被布置成面向电子组件的方式将衬底布置和至少一个电子组件相对于彼此安置；
-使用涂覆到接触材料层侧面的至少若干部分的(所述)预固剂预固定衬底布置与至少一个电子组件；
-将衬底布置附接到至少一个电子组件。
以使得衬底的第一侧面被布置成面向电子组件的方式将衬底布置和至少一个电子组件相对于彼此安置可以将衬底布置放置在电子组件上的方式进行。在另一实施例中，可设想将电子组件放置在衬底布置上。
如果衬底布置包含载体或配置在载体上，那么尤其在衬底布置和电子组件相对于彼此定位之前，衬底与所涂覆的接触材料层和所涂覆的预固剂一起从(所述)载体拆离。
在衬底布置与电子组件已相对于彼此定位之后，衬底布置优选地与电子组件一起预固定。这一预固定借助于涂覆到衬底第一侧面的至少若干部分的预固剂进行。为此目的，优选地暴露于热。施加优选100-150℃的温度，使得预固剂借助于施加热活化并且衬底布置因此能够与电子组件一起预固定。使用这类预固定，有可能实现以下条件：其中与附接电子组件一起预固定的衬底布置稳定到足以传输，使得电子组件可以不再被传送带的推进摇晃松散。实际上，电子组件保持在其预固定位置。
衬底与所涂覆接触材料层和所涂覆预固剂一起可以借助于喷嘴拆离载体。衬底可以与所涂覆接触材料层和所涂覆预固剂一起附接到电子组件作为取放工艺的零件。这可以在单步骤中进行，也就是说，衬底可以紧接在载体已拆离之后放置在电子组件上。还可能的是在两个独立步骤中使衬底与载体拆离并且将衬底与接触材料层和预固剂一起置放在电子组件上。
电子组件可以是半导体或DCB衬底或PCB衬底。在预固定之后按时序发生衬底布置附接电子组件。可以例如通过烧结和/或压制和/或焊接和/或粘着剂粘结进行将衬底布置附接到电子组件。换句话说，衬底布置经烧结和/或压制和/或焊接和/或粘结到电子组件，衬底布置优选地烧结到电子组件。为此目的，衬底布置提供有接触材料层，尤其呈银烧结膏形式。
关于预固剂与用于将电子组件附接到衬底布置的根据本发明的方法结合，参考在预固剂方面的先前解释。还参考关于预固剂与接触材料层相对于彼此配置的先前解释。
固定到电子组件的衬底布置优选地在用于将衬底布置附接到电子组件的加工炉中传输。加工炉可以是例如压力烧结炉或烧结冲压炉或回流炉或层压炉。
在以下文本中，将基于示例性实施例参考随附示意图更详细地解释本发明和其其它特征。在附图中：
图1-5：展示用于制造衬底布置的方法的单独步骤；
图6a-8：展示根据第一实施例的用于将电子组件附接到衬底布置的根据本发明的方法的单独步骤；并且
图9-11：展示根据另一实施例的用于将电子组件附接到衬底布置的根据本发明的方法的单独步骤。
在以下文本中，相同参考标号将用于相同和功能性等效的零件。
在图1中，表示衬底11。衬底11具有第一侧面12和第二侧面13。衬底11优选地是铜带部分。还有可能使用铜合金带部分。
可以进一步提供的是在其一个或两个侧面12和13上涂布衬底11。第一侧面12和/或第二侧面13优选地用金或镍-金或银或镍-银或镍-钯-金涂布，尤其镀锌。
在所示实例中，衬底11的第一侧面12平行于衬底11的相对第二侧面13设计。
图2展示将接触材料涂覆到衬底10的侧面12以形成接触材料层15。接触材料层15的接触材料优选地是烧结膏，尤其是银烧结膏。烧结膏通常由辅助烧结剂和金属粒子组成。具体来说，金属粒子是银粒子。辅助烧结剂是有机化合物和/或脂肪酸和/或粘合剂。
可以借助于压制工艺将接触材料层15涂覆到衬底11的第一侧面12。将接触材料层15优选地涂覆到衬底11的第一侧面12的最大可能区域。然而，窄边缘19可以保持在衬底11上或衬底11的第一侧面12上，所述窄边缘19例如在压制工艺中由于所选择的涂覆技术并非由接触材料层15覆盖。
边缘19优选地具有此类宽度bR，所述宽度bR尤其占不超过衬底11的总宽度bS的5％。
如图3中所述，将预固剂18涂覆到接触材料层15的第一侧面16。接触材料层15的第一侧面16是背对衬底11或衬底11的第一侧面12的接触材料层15的侧面。
将预固剂18以小液滴状元件或椭圆形元件形式涂覆到接触材料层的这第一侧面16。预固剂18包含相同辅助烧结剂作为接触材料层15的接触材料。此作用在于，当使衬底布置10与电子组件接触时，未将其它种类的污染或材料引入接触材料层15中。
根据图3，衬底布置10包含衬底11、接触材料层15和预固剂18。涂覆到衬底11的接触材料层15具有40-80μm的层厚度。
如图4中所示，以衬底11的第一侧面12被布置成面向载体20的方式将具有所涂覆接触材料层15和所涂覆预固剂18的衬底11定位于载体20上，其中预固剂18至少以粘附方式与载体20粘结。载体20可以是载体膜。在所示实例中，将UV胶带拉伸遍及晶圆框架，使得将衬底11与接触材料层15和预固剂18一起涂覆到此UV胶带。在根据图4的表示中，衬底布置10'因此包含载体20、衬底11以及接触材料层15和预固剂18。
图5展示衬底布置10'已呈现所需最终零件几何形状。例如借助于激光移除边缘19。还拆离呈附接到载体20状态的衬底11。将切口25引入衬底10'中，使得将衬底布置10'分成三种单独的几何形状或三个较小的衬底布置10"。当侧边缘19拆离时并且当衬底11分离时，接触材料层15和预固剂18的至少部分也经拆离或经结构化和分离。
如图6a中所表示，分离的衬底布置10"借助于喷嘴40从载体20拆离。分离的衬底布置10"可以是例如图5的左侧衬底布置10"。通过向衬底布置10"施加拉力移除固定剂18与载体20之间的粘着剂粘结，使得衬底布置10"可以再次借助于喷嘴40附接到电子组件30上。以使得衬底11的第一侧面12布置成面向电子组件30的方式使衬底布置10"与电子组件30相对于彼此定位。
根据图7，衬底布置10"通过涂覆到接触材料层15的第一侧面16的至少部分的预固剂18预固定到至少一个电子组件30。衬底布置10"因此借助于预固剂18预固定在电子组件30的第一侧面31上。预固定可以通过施加轻压力和/或施加热进行。另一方面，在示出的实施例中，电子组件30的第二侧面32不含其它层和/或组件。
在图8中，电子组件30呈附接到衬底布置上的状态表示。当衬底布置10"附接到电子组件30上时，尤其当烧结和/或压制和/或粘结时，预固剂18溶解。所保留的均是接触材料层15。因为预固剂18包含与接触材料层15中的接触材料相同的辅助烧结剂，所以接触材料层并未污染。换句话说，在处理之后，预固剂或预涂覆粘着剂不具有活性并且不再存在。
图9-11中表示涉及用于将至少一个电子组件附接到衬底布置10的方法的第二实施例。所示方法步骤前面通常是图1-3中所表示的方法步骤，其中衬底13还可以是引线框、DCB或PCB。因此，有可能将两个电子组件30和30'定位在衬底布置10上，所述衬底布置10在所示实例中不包含载体。在安装工艺中定位电子组件30和30'。在此情形下，「取放」工艺为可能的。
在图9中所表示的实例中，还可以施加热量。分别定位电子组件30和30'，使得电子组件30和30'的第一侧面31面向衬底11的第一侧面12，使得电子组件30和30'可以通过接触材料层15的第一侧面16上的预固剂18预固定在衬底布置10上。如图10中所表示，固定电子组件30和30'以通过预固剂18或预涂覆粘着剂进一步处理。
预固定后面是将衬底布置10实际附接到电子组件30和30'。术语附接应理解成意味着衬底布置10连接到电子组件30和30'。可以通过焊接或压制或烧结或粘着剂粘结进行附接。在此情形下，可能的是在加工炉，例如压力烧结炉或烧结冲压炉或回流炉或层压炉中将衬底布置10与电子组件30和30'烧结在一起。在附接，优选地烧结期间，预固剂18近乎完全移除，尤其燃烧掉和/或熔化掉。在处理之后，预涂覆粘着剂不具活性并且不再存在。
此时应注意，可以单独或以任何组合将与根据图1-11的实施例，尤其图示中所表示的细节有关的先前文本中所描述的方法步骤和元件要求为本发明的本质。
参考符号清单
10、10'、10” 衬底布置
11 衬底
12 第一侧面
13 第二侧面
15 接触材料层
16 接触材料层的第一侧面
18 预固剂
19 边缘
20 载体
25 切口
30、30' 电子组件
31 电子组件的第一侧面
32 电子组件的第二侧面
40 喷嘴
bS 衬底的总宽度
bR 边缘宽度

Claims (39)

1.一种用于制造用以附接到电子组件的衬底组合件的方法，所述方法包含：
提供具有第一侧面和第二侧面的衬底；
将接触材料层涂覆到所述衬底的所述第一侧面，使得在涂覆接触材料层之后，所述衬底不具有侧边缘或者具有上面未涂覆接触材料层的侧边缘，其中所述边缘具有的宽度不超过所述衬底的总宽度的20％；
将预固剂至少涂覆到背离所述衬底的所述接触材料层的侧面的部分；
将具有经涂覆接触材料层和经涂覆预固剂的所述衬底定位在载体膜上，使得所述衬底的所述第一侧面布置成面向所述载体膜，并且其中所述预固剂至少以粘附方式与所述载体粘结；
将具有经涂覆接触材料层和经涂覆预固剂的所述衬底在被定位到所述载体膜时分离成多个衬底组合件，包括将所述衬底与上面未涂覆接触材料层的所述侧边缘分离；
其中所述接触材料和所述预固剂包含相同的辅助烧结剂。
2.根据权利要求1所述的方法，
其特征在于
所述衬底是金属片或金属带部分或引线框或DCB衬底或PCB衬底。
3.根据权利要求1所述的方法，
其特征在于
所述衬底是铜片或铜带部分。
4.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
待提供的所述衬底的所述第一侧面和所述第二侧面中的至少一者或衬底坯料的第一侧面和第二侧面中的至少一者被涂布。
5.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
使用包含金(Au)或镍-金(NiAu)或银(Ag)或镍-银(NiAg)或镍-钯-金(NiPdAu)的材料涂布待提供的所述衬底的所述第一侧面和所述第二侧面中的至少一者或衬底坯料的第一侧面和第二侧面中的至少一者。
6.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
待提供的所述衬底的所述第一侧面和所述第二侧面中的至少一者或衬底坯料的第一侧面和第二侧面中的至少一者通过化学电镀被涂布。
7.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
待提供的所述衬底的所述第一侧面和所述第二侧面中的至少一者或衬底坯料的第一侧面和第二侧面中的至少一者通过镀锌被涂布。
8.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
涂覆到所述衬底的所述接触材料层的层厚度为10μm到150μm。
9.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
涂覆到所述衬底的所述接触材料层的层厚度为30μm到100μm。
10.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
涂覆到所述衬底的所述接触材料层的层厚度为40μm到80μm。
11.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的20％。
12.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的10％。
13.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的5％。
14.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述边缘的宽度(bR)不超过所述衬底的总宽度(bS)的1％。
15.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述衬底的所述侧边缘的至少部分经拆离和/或所述衬底经结构化和/或分离。
16.根据权利要求15所述的方法，
其特征在于
所述衬底呈附接到所述载体状态。
17.根据权利要求15所述的方法，
其特征在于
借助于激光进行所述侧边缘的所述拆离和/或所述衬底的所述结构化和/或所述衬底的所述分离。
18.根据权利要求15所述的方法，
其特征在于
当所述侧边缘经拆离时和/或当所述衬底经结构化时和/或当所述衬底经分离时，所述接触材料层和/或所述预固剂的至少部分经拆离和/或结构化和/或分离。
19.根据权利要求1-3中任一权利要求所述的方法，
其特征在于
所述接触材料层的接触材料包含辅助烧结剂和金属粒子，其中所述预固剂包含相同辅助烧结剂。
20.根据权利要求19所述的方法，
其特征在于
所述金属粒子为银粒子。
21.一种通过根据权利要求1到20中任一权利要求所述的方法产生的用以附接到电子组件的衬底组合件，包含衬底，所述衬底具有第一侧面和第二侧面，其中将接触材料层涂覆到所述衬底的所述第一侧面的至少部分，其中将预固剂涂覆到背对所述衬底的所述接触材料层的侧面的至少部分。
22.根据权利要求21所述的衬底组合件，
其特征在于
所述衬底为是金属片或金属带部分或引线框或DCB衬底或PCB衬底。
23.根据权利要求21所述的衬底组合件，
其特征在于
所述衬底是铜片或铜带部分。
24.根据权利要求21所述的衬底组合件，
其特征在于
所述接触材料层的接触材料包含辅助烧结剂和金属粒子，其中所述预固剂包含相同辅助烧结剂。
25.根据权利要求24所述的衬底组合件，
其特征在于
所述金属粒子为银粒子。
26.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述衬底的所述第一侧面和所述第二侧面中的至少一者被涂布。
27.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
使用包含金(Au)或镍-金(NiAu)或银(Ag)或镍-银(NiAg)或镍-钯-金(NiPdAu)的材料涂布待提供的所述衬底的所述第一侧面和所述第二侧面中的至少一者。
28.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述衬底的所述第一侧面和所述第二侧面中的至少一者通过化学电镀被涂布。
29.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述衬底的所述第一侧面和所述第二侧面中的至少一者通过化学镀锌被涂布。
30.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
载体，其中所述载体至少以粘附方式与所述预固剂粘结。
31.根据权利要求30所述的衬底组合件，
其特征在于
所述载体实施为载体膜。
32.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的20％。
33.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的10％。
34.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的5％。
35.根据权利要求21-25中任一权利要求所述的衬底组合件，
其特征在于
所述侧边缘的宽度(bR)不超过所述衬底的总宽度(bS)的1％。
36.一种用于将至少一个电子组件附接到根据权利要求21-35中任一权利要求所述的衬底组合件或已用根据权利要求1到20中任一权利要求所述的方法产生的衬底组合件的方法，包含以下步骤：
-以使得所述衬底的所述第一侧面布置成面向所述电子组件的方式将所述衬底组合件与所述至少一个电子组件相对于彼此定位，
-使用涂覆到接触材料层的侧面的至少部分的所述预固剂预固定所述衬底组合件与所述至少一个电子组件，
-将所述衬底组合件附接到所述至少一个电子组件。
37.根据权利要求36所述的方法，
其特征在于
从所述载体拆离与所述经涂覆接触材料层和所述经涂覆预固剂一起的所述衬底。
38.根据权利要求36所述的方法，
其特征在于
在将所述衬底组合件与所述电子组件相对于彼此定位之前，从所述载体拆离与所述经涂覆接触材料层和所述经涂覆预固剂一起的所述衬底。
39.根据权利要求36-38中任一权利要求所述的方法，
其特征在于
在附接到至少一个电子组件期间，所述衬底组合件与其一起烧结和/或压制和/或焊接和/或以粘附方式粘结。
CN201680059144.1A 2015-10-08 2016-09-28 用预固剂涂覆接触材料层以将衬底布置连接到电子组件的方法、相应的衬底布置及其制造方法 Active CN108604555B (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3553812A1 (de) * 2018-04-11 2019-10-16 Heraeus Deutschland GmbH & Co KG Substratanordnung zur verbindung mit einem elektronikbauteil
US11594513B2 (en) 2018-04-27 2023-02-28 Nitto Denko Corporation Manufacturing method for semiconductor device
EP3611761A1 (de) * 2018-08-13 2020-02-19 Heraeus Deutschland GmbH & Co KG Verfahren und metallsubstrat zum kontaktieren eines leistungshalbleiters durch ein kontaktierungsmittel mit zumindest einem kontaktierungsfreien bereich als belastungsreduzierende struktur
EP3627544A1 (de) * 2018-09-20 2020-03-25 Heraeus Deutschland GmbH & Co. KG Substratanordnung zum verbinden mit zumindest einem elektronikbauteil und verfahren zum herstellen einer substratanordnung
DE102018221148A1 (de) * 2018-12-06 2020-06-10 Heraeus Deutschland GmbH & Co. KG Verfahren zum Herstellen eines Substratadapters und Substratadapter zum Verbinden mit einem Elektronikbauteil
US11497112B2 (en) 2020-12-11 2022-11-08 Toyota Motor Engineering & Manufacturing North America, Inc. Driver board assemblies and methods of forming a driver board assembly
DE102021207267A1 (de) 2021-07-09 2023-01-12 Heraeus Deutschland GmbH & Co. KG Als temporäres Fixiermittel verwendbare Zusammensetzung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824270A2 (en) * 1996-08-06 1998-02-18 Hitachi Chemical Co., Ltd. A method of mounting a plurality of electronic parts on a circuit board
WO2008006340A1 (de) * 2006-07-14 2008-01-17 Danfoss Silicon Power Gmbh Verfahren zur hitze- und stossfesten verbindung eines halbleiters durch drucksinterung
CN102315138A (zh) * 2010-05-27 2012-01-11 赛米控电子股份有限公司 两个连接配对件低温压力烧结连接的方法及其制造的系统
CN104094387A (zh) * 2012-02-09 2014-10-08 罗伯特·博世有限公司 电气元件和/或电子元件的连接装置
CN104641462A (zh) * 2012-07-30 2015-05-20 埃里希·塔尔纳 基板复合物、用于结合基板的方法和装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050127134A1 (en) * 2003-09-15 2005-06-16 Guo-Quan Lu Nano-metal composite made by deposition from colloidal suspensions
JP2006202938A (ja) * 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
DE102008034946B4 (de) * 2008-07-26 2016-05-19 Semikron Elektronik Gmbh & Co. Kg Herstellungsverfahren eines Edelmetallverbindungsmittels
JP5158904B2 (ja) * 2010-03-19 2013-03-06 古河電気工業株式会社 導電接続部材、及び導電接続部材の作製方法
DE102010021765B4 (de) 2010-05-27 2014-06-12 Semikron Elektronik Gmbh & Co. Kg Herstellungsverfahren zur Anordnung zweier Verbindungspartner mittels einer Niedertemperatur Drucksinterverbindung
DE102010030317B4 (de) * 2010-06-21 2016-09-01 Infineon Technologies Ag Schaltungsanordnung mit Shuntwiderstand
DE102010044329A1 (de) 2010-09-03 2012-03-08 Heraeus Materials Technology Gmbh & Co. Kg Kontaktierungsmittel und Verfahren zur Kontaktierung elektrischer Bauteile
HUE028880T2 (en) 2011-09-20 2017-01-30 Heraeus Deutschland Gmbh & Co Kg Paste and process for connecting electronic components with a carrier
JP5971909B2 (ja) * 2011-09-21 2016-08-17 古河電気工業株式会社 導電性ペースト、及び該導電性ペーストを焼成して得られる接合体
DE102012202727B4 (de) * 2012-02-22 2015-07-02 Vectron International Gmbh Verfahren zur Verbindung eines ersten elektronischen Bauelements mit einem zweiten Bauelement
DE102012109156A1 (de) * 2012-09-27 2014-03-27 Osram Opto Semiconductors Gmbh Bauteilanordnung und Verfahren zum Herstellen von elektrischen Bauteilen
JP6200808B2 (ja) 2012-10-15 2017-09-20 積水化学工業株式会社 有機無機ハイブリッド粒子、導電性粒子、導電材料及び接続構造体
JP5664679B2 (ja) * 2013-03-07 2015-02-04 三菱マテリアル株式会社 パワーモジュール用基板の製造方法
DE102014104272A1 (de) * 2014-03-26 2015-10-01 Heraeus Deutschland GmbH & Co. KG Träger und Clip jeweils für ein Halbleiterelement, Verfahren zur Herstellung, Verwendung und Sinterpaste
DE102014109766B3 (de) 2014-07-11 2015-04-02 Heraeus Deutschland GmbH & Co. KG Verfahren zum Herstellen eines Substratadapters, Substratadapter und Verfahren zum Kontaktieren eines Halbleiterelements
DE202015001441U1 (de) * 2015-02-24 2015-03-18 Vincotech Gmbh Leistungshalbleitermodul mit kombinierten Dickfilm- und Metallsinterschichten

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0824270A2 (en) * 1996-08-06 1998-02-18 Hitachi Chemical Co., Ltd. A method of mounting a plurality of electronic parts on a circuit board
WO2008006340A1 (de) * 2006-07-14 2008-01-17 Danfoss Silicon Power Gmbh Verfahren zur hitze- und stossfesten verbindung eines halbleiters durch drucksinterung
CN102315138A (zh) * 2010-05-27 2012-01-11 赛米控电子股份有限公司 两个连接配对件低温压力烧结连接的方法及其制造的系统
CN104094387A (zh) * 2012-02-09 2014-10-08 罗伯特·博世有限公司 电气元件和/或电子元件的连接装置
CN104641462A (zh) * 2012-07-30 2015-05-20 埃里希·塔尔纳 基板复合物、用于结合基板的方法和装置

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