CN108574009A - 鳍式场效应管及其形成方法 - Google Patents

鳍式场效应管及其形成方法 Download PDF

Info

Publication number
CN108574009A
CN108574009A CN201710130767.XA CN201710130767A CN108574009A CN 108574009 A CN108574009 A CN 108574009A CN 201710130767 A CN201710130767 A CN 201710130767A CN 108574009 A CN108574009 A CN 108574009A
Authority
CN
China
Prior art keywords
dielectric layer
layer
field effect
fin
effect pipe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710130767.XA
Other languages
English (en)
Other versions
CN108574009B (zh
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710130767.XA priority Critical patent/CN108574009B/zh
Priority to US15/912,218 priority patent/US10460996B2/en
Publication of CN108574009A publication Critical patent/CN108574009A/zh
Application granted granted Critical
Publication of CN108574009B publication Critical patent/CN108574009B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供一种鳍式场效应管及其形成方法，所述鳍式场效应管的形成方法包括：提供半导体衬底，所述半导体衬底上具有多个分立的鳍部；形成横跨所述鳍部的伪栅极，所述伪栅极覆盖鳍部的部分顶部和侧壁；形成覆盖所述伪栅极和所述鳍部的层间介质层；去除所述伪栅极，在层间介质层中形成开口；在所述开口中形成栅介质层；在所述栅介质层和所述层间介质层上形成阻挡层；去除位于层间介质层上的栅介质层和阻挡层；去除位于层间介质层上的栅介质层和阻挡层的步骤之后，进行退火处理；去除所述开口中的阻挡层；在所述开口中形成金属栅极。本发明形成的鳍式场效应管的电学性能得到提高。

Description

鳍式场效应管及其形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种鳍式场效应管及其形成方法。
背景技术
随着半导体技术的飞速发展，半导体器件的特征尺寸不断缩小。半导体器件特征尺寸的减小对半导体器件的性能提出了更高的要求。
目前，金属-氧化物半导体场效应晶体管(MOSFET)的尺寸正在不断变小。为了适应工艺节点的减小，MOSFET场效应管的沟道长度也在逐渐缩短。沟道长度的缩短具有增加芯片的管芯密度、增加MOSFET场效应管的开关速度等好处。
然而，沟道长度的缩短容易造成栅极对沟道控制能力变差的问题，从而使栅极电压夹断(pinch off)沟道的难度也越来越大，进而造成亚阀值漏电现象，即出现短沟道效应(short-channel effects，SCE)。
因此，为了更好地适应器件尺寸按比例缩小的要求，半导体工艺逐渐从平面MOSFET晶体管向具有更高功效的三维立体式晶体管(如鳍式场效应管)过渡。鳍式场效应晶体管具有很好的沟道控制能力，可以减小短沟道效应。
然而，鳍式场效应管器件工作时容易发生漏电现象，从而影响鳍式场效应管器件的电学性能。如何提高鳍式场效应管的电学性能，成为亟需解决的问题。
发明内容
本发明解决的问题是提供一种鳍式场效应管及其形成方法，改善鳍式场效应管的漏电问题，提高鳍式场效应管的电学性能。
为解决上述问题，本发明提供一种鳍式场效应管的形成方法，其特征在于，包括：提供半导体衬底，所述半导体衬底上具有多个分立的鳍部；形成横跨所述鳍部的伪栅极，所述伪栅极覆盖鳍部的部分顶部和侧壁；形成覆盖所述伪栅极和所述鳍部的层间介质层；去除所述伪栅极，在层间介质层中形成开口；在所述开口中形成栅介质层；在所述栅介质层和所述层间介质层上形成阻挡层；去除位于层间介质层上的栅介质层和阻挡层；去除位于层间介质层上的栅介质层和阻挡层的步骤之后，进行退火处理；去除所述开口中的阻挡层；在所述开口中形成金属栅极。
可选的，去除位于层间介质层上阻挡层的步骤包括：
在所述开口中填充有机涂层；
去除所述有机涂层露出的阻挡层；
去除所述有机涂层。
可选的，在所述开口中填充有机涂层的步骤包括：
形成覆盖所述阻挡层的有机涂膜；
回刻蚀所述位于层间介质层上的有机涂膜，形成位于开口中的有机涂层。
可选的，去除所述有机涂层露出的阻挡层的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为SiH4，SiH4的气体流量为30sccm至3000sccm，温度为360摄氏度至520摄氏度，压强为0.03torr至10torr。
可选的，去除所述有机涂层的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为N2和H2的混合气体，N2的气体流量为1000sccm至8000sccm，H2的气体流量为500sccm至2000sccm，温度为150摄氏度至350摄氏度，压强为500mtorr至2000mtorr。
可选的，形成所述栅介质层的工艺为原子层沉积工艺，所述原子层沉积工艺的参数包括：通入前驱体Si，温度为80摄氏度至300摄氏度，压强为5torr至20torr，沉积次数为5次至50次。
可选的，在形成栅介质层之前，在开口底部形成界面介质层。
可选的，形成所述界面介质层的工艺为氧化工艺，所述氧化工艺的参数包括：通入H2O2液体，在10摄氏度至100摄氏度下反应5秒钟至500秒钟；
或者通入气体H2和O2，H2气体流量范围为：0.2slm至10slm，O2气体流量范围为10slm至100slm，反应温度范围为800摄氏度至1100摄氏度，压强为4torr至100torr，时间为5秒钟至30秒钟。
可选的，所述界面介质层的材料为氧化硅或者氮氧化硅。
可选的，所述阻挡层的厚度范围为：20埃至50埃。
可选的，进行退火处理的步骤中，所述退火处理的工艺为尖峰退火工艺或者快速退火工艺，所述尖峰退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度；所述快速退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度，时间为5秒钟至20秒钟。
可选的，在形成栅介质层之后，阻挡层之前，还在栅介质层表面形成第一功函数层；
去除所述层间介质层上阻挡层的步骤中，还去除层间介质层上的第一功函数层。
可选的，所述第一功函数层的材料为氮化钛或者氮化钽。
可选的，所述栅介质层的材料为氧化铪或者氧化镧铪。
可选的，所述阻挡层的材料为硅。
可选的，在去除阻挡层之后，形成金属栅极之前，在所述开口中形成第二功函数层；形成金属栅极的步骤包括：在所述第二功函数层上形成金属栅极。
可选的，形成伪栅极之后，形成层间介质层的步骤之前，所述形成方法还包括：
在所述伪栅极的侧壁形成侧墙；
在所述伪栅极和侧墙两侧的半导体衬底中形成源漏掺杂区。
相应地，本发明还提供一种鳍式场效应管，包括：半导体衬底，所述半导体衬底上具有多个分立的鳍部；位于半导体衬底和鳍部上的层间介质层；位于所述鳍部上的栅介质层和阻挡层，且所述阻挡层位于栅介质层上；位于层间介质层中的开口，所述阻挡层围成所述开口；位于所述鳍部中的源漏掺杂区。
可选的，所述鳍式场效应管还包括：
位于鳍部上的界面介质层；
位于界面介质层表面的栅介质层；
位于栅介质层表面的第一功函数层；
位于第一功函数层表面的阻挡层。
可选的，所述阻挡层的厚度范围为：20埃至50埃。
与现有技术相比，本发明的技术方案具有以下优点：
本发明提供的鳍式场效应管形成方法的技术方案中，在进行退火处理之前，去除了位于层间介质层上的栅介质层和阻挡层，减小了退火引起的阻挡层产生的应力影响，使得后续工艺中形成的金属栅极的漏电问题得到改善，从而提高了鳍式场效应管的电学性能。
可选方案中，所述阻挡层的作用是控制位于鳍部上的界面介质层的再生长问题。为了修复与鳍部相接触的界面介质层的缺陷，使得界面介质层致密化，在去除位于层间介质层上的栅介质层和阻挡层的步骤之后，还要进行退火处理。所述退火处理的温度较高，外界空气中的氧容易使得界面介质层发生再生长。所述阻挡层能够防止外界氧的扩散，从而改善了界面介质层的再生长问题，进而提高了鳍式场效应管的电学性能。
附图说明
图1是鳍式场效应管形成方法一步骤的结构示意图；
图2至图15是本发明鳍式场效应管一实施例形成过程的剖面结构示意图；
图16是本发明鳍式场效应管一实施例的剖面结构示意图。
具体实施方式
根据背景技术形成的鳍式场效应管的电学性能有待提高。现结合一种鳍式场效应管对鳍式场效应管的电学性能有待提高的原因进行分析。
参考图1，图1为鳍式场效应管形成方法一步骤的结构示意图，所述鳍式场效应管的形成方法，包括：提供衬底100，所述衬底100上的具有多个分立的鳍部110；形成位于所述鳍部110露出的衬底100上的隔离结构120，所述隔离结构120覆盖所述鳍部110的部分侧壁表面，且所述隔离结构120顶部低于鳍部110顶部；形成横跨所述鳍部110的伪栅极(图未示)，所述伪栅极覆盖鳍部110的部分顶部和侧壁；在所述伪栅极的侧壁上形成侧墙150；在位于所述伪栅极两侧的鳍部110中形成源漏掺杂区140；形成覆盖所述源漏掺杂区140和伪栅极的刻蚀停止层130；形成覆盖所述伪栅极和所述鳍部110的层间介质层131；去除所述伪栅极，在层间介质层131中形成开口115；在所述开口115中形成界面介质层111；在所述界面介质层111和所述层间介质层131上形成栅介质层160；在所述栅介质层160上形成功函数层170；在所述功函数层170上形成阻挡层180；在所述开口115中填充金属，形成金属栅极(图未示)；形成所述阻挡层180之后，进行退火处理。
由于退火处理的步骤中会产生较高的温度，使得形成的阻挡层180产生应力，继而使得鳍部110上的界面介质层111也产生应力形变，从而发生漏电现象，因此，降低了鳍式场效应管的电学性能。
此外，退火处理中所述阻挡层180受热容易发生膨胀，由于阻挡层180和栅介质层160的膨胀系数不同，受热过程中阻挡层180和栅介质层160相互作用产生应力，从而也会使得与栅介质层160接触的界面介质层111产生应力形变，因而导致发生漏电现象。
为了解决所述技术问题，本发明提供一种鳍式场效应管的形成方法，包括：提供半导体衬底，所述半导体衬底上具有多个分立的鳍部；形成横跨所述鳍部的伪栅极，所述伪栅极覆盖鳍部的部分顶部和侧壁；形成覆盖所述伪栅极和所述鳍部的层间介质层；去除所述伪栅极，在层间介质层中形成开口；在所述开口中形成栅介质层；在所述栅介质层和所述层间介质层上形成阻挡层；去除位于层间介质层上的栅介质层和阻挡层；去除位于层间介质层上的栅介质层和阻挡层的步骤之后，进行退火处理；去除所述开口中的阻挡层；在所述开口中形成金属栅极。
本发明在进行退火处理之前，将位于层间介质层上的栅介质层和阻挡层去除，这样做的目的是为了减小退火时阻挡层所产生的应力，从而减小位于衬底上的界面介质层退火时产生的应力，进而改善了界面介质层应力形变而导致的漏电问题，因此，提高了鳍式场效应管的电学性能。
此外，将位于层间介质层上的栅介质层和阻挡层去除，有利于使得退火时所述栅介质层和阻挡层产生的应力得到释放，从而减小了退火时阻挡层产生的应力，缓解了界面介质层产生的应力形变，进而改善了漏电问题。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图15是本发明一实施例鳍式场效应管形成过程的结构示意图。
参考图2，提供半导体衬底200，所述半导体衬底200上具有多个分立的鳍部210。
本实施例中，所述半导体衬底200上还包括隔离结构220，所述隔离结构220覆盖所述鳍部210的部分侧壁表面，且所述隔离结构220顶部低于所述鳍部210顶部。
所述隔离结构220可以起到电学隔离相邻鳍部210的作用。
本实施例中，所述半导体衬底200为硅衬底；在其他实施例中，所述半导体衬底200的材料还可以为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述半导体衬底200还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底。
本实施例中，所述鳍部210的材料为硅；在其他实施例中，所述鳍部210的材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。
本实施例中，所述隔离结构220的材料为氧化硅；在其他实施例中，所述隔离结构220的材料为氧化硅、氮化硅或氮氧化硅。
本实施例中，形成所述半导体衬底200、鳍部210的工艺步骤包括：提供初始衬底；在所述初始衬底表面形成图形化的硬掩膜层；以所述硬掩膜层为掩膜刻蚀所述初始衬底，刻蚀后的初始衬底作为半导体衬底200，位于半导体衬底200表面的凸起作为鳍部210；保留所述位于鳍部210顶部的硬掩膜层。
具体地，形成所述硬掩膜层的工艺步骤包括：首先形成初始硬掩膜层；在所述初始硬掩膜层表面形成图形化的光刻胶层；以所述图形化的光刻胶层为掩膜刻蚀所述初始硬掩膜层，在初始衬底表面形成硬掩膜层；去除所述图形化的光刻胶层。在其他实施例中，所述硬掩膜层的形成工艺还能够包括：自对准双重图形化(SADP，Self-aligned DoublePatterned)工艺、自对准三重图形化(Self-aligned Triple Patterned)工艺、或自对准四重图形化(Self-aligned Double Double Patterned)工艺。所述双重图形化工艺包括LELE(Litho-Etch-Litho-Etch)工艺或LLE(Litho-Litho-Etch)工艺。
形成所述隔离结构220的工艺步骤包括：在所述半导体衬底200上形成覆盖所述鳍部210的隔离膜，所述隔离膜顶部高于所述鳍部210顶部；对所述隔离膜顶部进行平坦化处理；在所述平坦化处理之后，回刻蚀去除部分厚度的隔离膜，形成位于所述半导体衬底200上的所述隔离结构220，在回刻蚀去除部分厚度的隔离膜的过程中去除所述位于鳍部210顶部的硬掩膜层。
参考图3，形成横跨所述鳍部210的伪栅极211，所述伪栅极211覆盖鳍部210的部分顶部和侧壁。
形成所述伪栅极211的步骤包括：形成覆盖所述半导体衬底200和鳍部210的栅极层；在所述栅极层上形成硬掩膜层，所述硬掩膜层定义出待形成的伪栅极的图形；以所述硬掩膜层为掩膜刻蚀所述栅极层，形成横跨所述鳍部的伪栅极211；在形成所述伪栅极211之后，去除位于伪栅极211顶部的硬掩膜层。
本实施例中，所述伪栅极211的材料为多晶硅。
本实施例中，在形成所述伪栅极211之前，还可以在所述半导体衬底200上形成伪栅介质层212。所述伪栅介质层212的材料为高K栅介质材料。
本实施例中，在形成伪栅极211之后，形成后续工艺中层间介质层的步骤之前，所述形成方法还包括：在所述伪栅极211的侧壁形成侧墙250；在所述伪栅极211和侧墙250两侧的鳍部210中形成源漏掺杂区240，所述源漏掺杂区240内掺杂有P型离子或者N型离子。
形成所述源漏掺杂区240的工艺步骤包括：刻蚀位于所述伪栅极211两侧的鳍部210，在所述伪栅极211两侧的鳍部210中形成凹槽；形成填充满所述凹槽的源漏掺杂区240，在所述源漏掺杂区240内掺杂有P型离子或者N型离子。
本实施例中，采用选择性外延工艺形成所述源漏掺杂区240。当形成的鳍式场效应管为NMOS器件时，所述源漏掺杂区240的材料为Si或者SiC，所述源漏掺杂区240的材料为SiC时，所述源漏掺杂区240还可以向沟道区提供拉应力作用，提高NMOS器件的载流子迁移率；所述源漏掺杂区240内掺杂有N型离子，例如：所述N型离子为P、As或Sb。
当形成的所述鳍式场效应管为PMOS器件时，所述源漏掺杂区240的材料为Si或者SiGe，且所述源漏掺杂区240内掺杂有P型离子，所述P型离子为B、Ga或In。所述源漏掺杂区240的材料为SiGe时，所述源漏掺杂区240还可以向沟道区提供压应力作用，提高PMOS器件的载流子迁移率。
参考图4，形成覆盖所述伪栅极211和鳍部210的刻蚀停止层230。
本实施例中，所述刻蚀停止层230的作用是在后续形成鳍式场效应管接触孔的工艺中，作为刻蚀形成接触孔的停止层。所述刻蚀停止层230的材料是氮化硅；所述刻蚀停止层230的厚度范围是5纳米至30纳米。
形成所述刻蚀停止层230的工艺为干法刻蚀，所述工艺参数包括：刻蚀气体为CH2F2、O2和CF4的混合气体，CH2F2的气体流量为8sccm至50sccm，O2的气体流量为2sccm至30sccm，CF4的气体流量为30sccm至200sccm，压强为10mtorr至2000mtorr，电压为30V至500V，RF功率为100W至1000W。
结合参考图5和图6，形成覆盖所述伪栅极211和所述鳍部210的层间介质层231，所述层间介质层231露出所述伪栅极211顶部。
参考图5，在所述刻蚀停止层230上覆盖层间介质膜232，所述层间介质膜232顶部高于所述伪栅极211顶部。
本实施例中，所述层间介质膜232的材料为二氧化硅。
参考图6，平坦化所述层间介质膜232(见图5)，形成露出所述伪栅极211且覆盖所述鳍部210的层间介质层231。本实施例中，所述平坦化步骤使所述层间介质层231顶部与伪栅极211顶部齐平。
本实施例中，伪栅极211上还形成有刻蚀停止层230，平坦化步骤去除位于伪栅极211顶部的刻蚀停止层230。
本实施例中，采用化学机械平坦化工艺能使得所述层间介质膜232的整个表面实现平坦化，减少了形成所述层间介质层231步骤中产生的表面缺陷。同时，平坦化所述层间介质膜232的过程还会去除位于伪栅极211顶部的刻蚀停止层230，也起到了简化工艺流程的作用。
参考图7，去除所述伪栅极211，在层间介质层231中形成开口213。
本实施例中，在去除所述伪栅极211的同时，也去除位于所述鳍部210上的伪栅介质层212(见图6)。所述伪栅极211的材料包括多晶硅；去除所述伪栅极211的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为HBr和He的混合气体，HBr的气体流量为150sccm至500sccm，He的气体流量为100sccm至400sccm，压强为3mtorr至10mtorr，RF功率为10W至500W。
参考图8，在所述开口213中形成栅介质层260。
本实施例中，所述栅介质层260的材料为氧化铪或者氧化镧铪。所述栅介质层260的厚度范围为：10埃至30埃。
形成所述栅介质层260的工艺为原子层沉积工艺，所述工艺的参数包括：向原子层沉积室内通入前驱体Si，温度为80摄氏度至300摄氏度，压强为5torr至20torr，沉积次数为5次至50次。
本实施例中，在形成栅介质层260之前，在开口底部还形成有界面介质层216，所述栅介质层260位于界面介质层216上。所述界面介质层216的厚度范围为：5埃至15埃。
形成所述界面介质层216的工艺为氧化工艺，所述氧化工艺的参数包括：通入H2O2气体，在10摄氏度至100摄氏度下反应5秒钟至500秒钟；或者通入气体H2和O2，H2气体流量范围为：0.2slm至10slm，O2气体流量范围为10slm至100slm，反应温度范围为800摄氏度至1100摄氏度，压强为4torr至100torr，时间为5秒钟至30秒钟。
参考图9和图10，在所述栅介质层260和所述层间介质层231上形成阻挡层280。
参考图9，在形成栅介质层260之后，形成阻挡层280(见图10)之前，还在栅介质层260表面形成第一功函数层270。
所述第一功函数层270的作用是用来调节鳍式场效应管的阈值电压。
本实施例中，所述第一功函数层270的材料为氮化钛或者氮化钽。所述第一功函数层270的厚度范围为：8埃至50埃。
形成第一功函数层270的工艺为原子层沉积，所述工艺的参数包括：向原子层沉积室内通入前驱体Ti，温度为80摄氏度至300摄氏度，压强为5torr至20torr，沉积次数为5次至50次。
参考图10，在所述第一功函数层270上形成阻挡层280。
本实施例中，所述阻挡层280的作用是在后续工艺中控制位于鳍部210上界面介质层216的再生长。
需要说明的是，为了修复与鳍部210相接触的界面介质层216的缺陷，使得界面介质层216致密化，后续工艺中在去除位于层间介质层231上的栅介质层260和阻挡层280的步骤之后，还要进行退火处理。所述退火处理的温度较高，外界空气中的氧容易使得界面介质层216发生再生长，从而影响鳍式场效应管的电学性能。
本实施例中，在所述栅介质层260上，还形成阻挡层280，所述阻挡层280可以阻挡外界中氧的进入，从而缓解了后续退火工艺中界面介质层216的再生长问题。
本实施例中，所述阻挡层280的材料为硅。
需要说明的是，所述阻挡层280的厚度既不能过大也不能过小，当阻挡层280的厚度过大时，容易使得所述开口213过小，从而导致后续工艺形成的金属栅极的尺寸过小；当阻挡层280的厚度过小时，会使得外界的氧能够穿透阻挡层280，从而导致所述阻挡层280防止界面介质层216再生长的问题得难以解决。本实施例中，所述阻挡层280的厚度范围为20埃至50埃。
形成所述阻挡层280的工艺为原子层沉积工艺或者炉管沉积工艺，所述工艺的参数包括：通入SiH4气体，在温度为360摄氏度至520摄氏度下，压强为0.03torr至10torr。
参考图11至图14，去除位于层间介质层231上的栅介质层260和阻挡层280。
参考图11和图12，去除位于层间介质层231上的栅介质层260和阻挡层280的步骤包括：在所述开口213(见图10)中填充有机涂层214。
参考图11，形成覆盖所述阻挡层280的有机涂膜215。
所述形成覆盖所述阻挡层280的有机涂膜215的工艺为旋涂工艺，所述旋涂工艺参数包括：转速为1000r/min至50000r/min。
参考图12，回刻蚀所述位于层间介质层231上的有机涂膜215(见图11)形成位于开口213(见图10)中的有机涂层214。
本实施例中，所述有机涂层214的材料是有机材料，所述有机涂层214的作用是充当后续工艺中去除位于层间介质层231上的栅介质层260和阻挡层280的掩膜。
参考图13，以所述有机涂层214为掩模，去除位于层间介质层231上的栅介质层260和阻挡层280。
本实施例中，在去除所述位于层间介质层231上的栅介质层260和阻挡层280的同时，还去除位于层间介质层231上的第一功函数层270。
本实施例中，去除位于层间介质层231上的栅介质层260和阻挡层280的步骤包括：以所述有机涂层214为掩膜刻蚀所述栅介质层260和阻挡层280，去除位于层间介质层231上的栅介质层260和阻挡层280；在去除所述位于层间介质层231上的栅介质层260和阻挡层280的同时，还去除位于层间介质层231上的第一功函数层270。
本实施例中，去除位于层间介质层231上的栅介质层260的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为HBr和He的混合气体，HBr的气体流量为150sccm至500sccm，He的气体流量为100sccm至400sccm，温度为50摄氏度至100摄氏度，压强为3mtorr至10mtorr，功率为10W至500W。
去除所述阻挡层280的工艺为湿法刻蚀工艺，所述湿法刻蚀工艺的参数包括：刻蚀温度为40摄氏度至90摄氏度，刻蚀溶液的比例为NH4OH:H2O2:H2O＝1:2:50；或者刻蚀溶液的比例为HCL:H2O2:H2O＝1:1:50。
参考图14，去除所述有机涂层214(见图13)。
本实施例中，去除所述有机涂层214的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为CH4、H2和N2的混合气体，CH4的气体流量为10sccm至100sccm，H2的气体流量为100sccm至800sccm，N2的气体流量为30sccm至500sccm，温度为30摄氏度至60摄氏度，压强为5mtorr至150mtorr，电压为80V至200V，功率为800W至2200W，时间为50秒至500秒。
本实施例在去除位于层间介质层231上的栅介质层260和阻挡层280的步骤之后，进行退火处理。
所述退火工艺的作用是为了修复与鳍部210接触的界面介质层216的表面缺陷，使得界面介质层216表面致密化。本实施例中，去除位于层间介质层231上的栅介质层260和阻挡层280的步骤之后，进行退火处理。由于退火处理之前，去除了位于层间介质层231上的栅介质层260和阻挡层280，减小了退火引起的阻挡层280产生的应力影响，进而减小了位于鳍部210上的界面介质层216受影响产生的应力形变，从而防止了界面介质层216应力形变而导致的漏电问题，因此，使得后续工艺中形成的金属栅极的漏电问题得到改善，从而提高了鳍式场效应管的电学性能。
具体地，所述退火的工艺为尖峰退火工艺或者快速退火工艺，所述尖峰退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度；所述快速退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度，时间为5秒钟至20秒钟。
参考图15，去除所述开口213中的阻挡层280(见图14)；在所述开口213中形成金属栅极(图未示)。
本实施例中，在去除阻挡层280之后，形成金属栅极(图未示)之前，在所述开口213中还形成有第二功函数层(图未示)；形成金属栅极的步骤包括：在所述第二功函数层上形成金属栅极。
本实施例中，所述第二功函数层的材料是TiAL，在其他实施例中，所述第二功函数层的材料还可以是TiCAL或TiC。所述第二功函数层的作用是用来调节鳍式场效应管的阈值电压。所述金属栅极的材料包括：Ti、Ta、TiN、TaN、TiAl、TiAlN、Cu、Al、W、Ag或Au中的一种或多种。
相应地，本发明还提供一种鳍式场效应管，参考图16，所述鳍式场效应管包括：半导体衬底300，所述半导体衬底300上具有多个分立的鳍部310；位于半导体衬底300和鳍部310上的层间介质层331；位于所述鳍部310上的栅介质层360和阻挡层380，且所述阻挡层380位于栅介质层360上；位于层间介质层331中的开口313，所述阻挡层380围成所述开口313；位于鳍部310中的源漏掺杂区340。
以下将结合附图16对本实施例提供的鳍式场效应管进行详细说明。
本实施例中，所述半导体衬底300上还包括隔离结构320，所述隔离结构320覆盖所述鳍部310的部分侧壁表面，且所述隔离结构320顶部低于所述鳍部310顶部。
所述隔离结构320可以起到电学隔离相邻鳍部310的作用。
所述半导体衬底300的材料为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述半导体衬底300还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底；所述鳍部310的材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟；所述隔离结构320的材料为氧化硅、氮化硅或氮氧化硅。本实施例中，所述半导体衬底300为硅衬底，所述鳍部310的材料为硅，所述隔离结构320的材料为氧化硅。
所述鳍式场效应管为NMOS器件时，所述源漏掺杂区340的材料为Si或者SiC，且所述源漏掺杂区340内掺杂有N型离子，所述N型离子为P、As或Sb；当形成的所述鳍式场效应管为PMOS器件时，所述源漏掺杂区340的材料为Si或者SiGe，且所述源漏掺杂区340内掺杂有P型离子，所述P型离子为B、Ga或In。
其中，所述源漏掺杂区340的材料为SiC时，所述源漏掺杂区340还用于向沟道区提供拉应力作用，提高NMOS器件的载流子迁移率；所述源漏掺杂区340的材料为SiGe时，所述源漏掺杂区340还用于向沟道区提供压应力作用，提高PMOS器件的载流子迁移率。
本实施例中，在所述隔离结构320和鳍部310上还具有刻蚀停止层330。
所述刻蚀停止层330用于在形成鳍式场效应管接触孔的工艺中定义接触孔的刻蚀停止位置。所述刻蚀停止层330的材料是氮化硅；所述刻蚀停止层330的厚度范围是8纳米至30纳米。
所述鳍式场效应管还包括：位于鳍部310上的界面介质层311；位于界面介质层311表面的栅介质层360；位于栅介质层360表面的第一功函数层370；位于第一功函数层370表面的阻挡层380。
本实施例中，所述界面介质层311的材料为氧化硅，所述界面介质层311的厚度范围为：5埃至10埃；所述栅介质层260的材料为氧化铪或者氧化镧铪。所述栅介质层260的厚度范围为：10埃至30埃。所述第一功函数层370的材料为氮化钛或者氮化钽，所述第一功函数层370的厚度范围为：8埃至50埃；所述阻挡层380的材料为硅，所述阻挡层380的厚度范围为：20埃至50埃。所述第一功函数层370的作用是用来调节鳍式场效应管的阈值电压。
本实施例中，所述鳍式场效应管的后续形成工艺中还包括退火处理，由于所述阻挡层380位于所述开口313中，退火处理工艺中的高温不会使得所述阻挡层380产生很大的应力作用，进而使得位于鳍部310上的界面介质层311不会因阻挡层380的应力作用而产生形变，发生漏电现象，从而提高了鳍式场效应管的电学性能。
需要说明的是，由于所述阻挡层380位于所述开口313中，有利于使得退火时所述栅介质层360和阻挡层380产生的应力得到释放，从而减小了退火时阻挡层380产生的应力，进而缓解了界面介质层311产生的应力形变，从而改善了漏电问题。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种鳍式场效应管的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底上具有多个分立的鳍部；
形成横跨所述鳍部的伪栅极，所述伪栅极覆盖鳍部的部分顶部和侧壁；
形成覆盖所述伪栅极和所述鳍部的层间介质层；
去除所述伪栅极，在层间介质层中形成开口；
在所述开口中形成栅介质层；
在所述栅介质层和所述层间介质层上形成阻挡层；
去除位于层间介质层上的栅介质层和阻挡层；
去除位于层间介质层上的栅介质层和阻挡层的步骤之后，进行退火处理；
去除所述开口中的阻挡层；
在所述开口中形成金属栅极。
2.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，去除位于层间介质层上阻挡层的步骤包括：
在所述开口中填充有机涂层；
去除所述有机涂层露出的阻挡层；
去除所述有机涂层。
3.如权利要求2所述的鳍式场效应管的形成方法，其特征在于，在所述开口中填充有机涂层的步骤包括：
形成覆盖所述阻挡层的有机涂膜；
回刻蚀所述位于层间介质层上的有机涂膜，形成位于开口中的有机涂层。
4.如权利要求2所述的鳍式场效应管的形成方法，其特征在于，去除所述有机涂层露出的阻挡层的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为SiH4，SiH4的气体流量为30sccm至3000sccm，温度为360摄氏度至520摄氏度，压强为0.03torr至10torr。
5.如权利要求2所述的鳍式场效应管的形成方法，其特征在于，去除所述有机涂层的工艺为干法刻蚀工艺，所述干法刻蚀工艺的参数包括：刻蚀气体为N2和H2的混合气体，N2的气体流量为1000sccm至8000sccm，H2的气体流量为500sccm至2000sccm，温度为150摄氏度至350摄氏度，压强为500mtorr至2000mtorr。
6.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，形成所述栅介质层的工艺为原子层沉积工艺，所述原子层沉积工艺的参数包括：通入前驱体Si，温度为80摄氏度至300摄氏度，压强为5torr至20torr，沉积次数为5次至50次。
7.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，在形成栅介质层之前，在开口底部形成界面介质层。
8.如权利要求7所述的鳍式场效应管的形成方法，其特征在于，形成所述界面介质层的工艺为氧化工艺，所述氧化工艺的参数包括：通入H2O2液体，在10摄氏度至100摄氏度下反应5秒钟至500秒钟；
或者通入气体H2和O2，H2气体流量范围为：0.2slm至10slm，O2气体流量范围为10slm至100slm，反应温度范围为800摄氏度至1100摄氏度，压强为4torr至100torr，时间为5秒钟至30秒钟。
9.如权利要求7所述的鳍式场效应管的形成方法，其特征在于，所述界面介质层的材料为氧化硅或者氮氧化硅。
10.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，所述阻挡层的厚度范围为：20埃至50埃。
11.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，进行退火处理的步骤中，所述退火处理的工艺为尖峰退火工艺或者快速退火工艺，所述尖峰退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度；所述快速退火工艺的参数包括：温度范围为900摄氏度至1050摄氏度，时间为5秒钟至20秒钟。
12.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，在形成栅介质层之后，阻挡层之前，还在栅介质层表面形成第一功函数层；
去除所述层间介质层上阻挡层的步骤中，还去除层间介质层上的第一功函数层。
13.如权利要求12所述的鳍式场效应管的形成方法，其特征在于，所述第一功函数层的材料为氮化钛或者氮化钽。
14.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，所述栅介质层的材料为氧化铪或者氧化镧铪。
15.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，所述阻挡层的材料为硅。
16.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，在去除阻挡层之后，形成金属栅极之前，在所述开口中形成第二功函数层；形成金属栅极的步骤包括：在所述第二功函数层上形成金属栅极。
17.如权利要求1所述的鳍式场效应管的形成方法，其特征在于，形成伪栅极之后，形成层间介质层的步骤之前，所述形成方法还包括：
在所述伪栅极的侧壁形成侧墙；
在所述伪栅极和侧墙两侧的半导体衬底中形成源漏掺杂区。
18.一种鳍式场效应管，其特征在于，包括：
半导体衬底，所述半导体衬底上具有多个分立的鳍部；
位于半导体衬底和鳍部上的层间介质层；
位于所述鳍部上的栅介质层和阻挡层，且所述阻挡层位于栅介质层上；
位于层间介质层中的开口，所述阻挡层围成所述开口；
位于所述鳍部中的源漏掺杂区。
19.如权利要求18所述的鳍式场效应管，其特征在于，所述鳍式场效应管还包括：
位于鳍部上的界面介质层；
位于界面介质层表面的栅介质层；
位于栅介质层表面的第一功函数层；
位于第一功函数层表面的阻挡层。
20.如权利要求18所述的鳍式场效应管，其特征在于，所述阻挡层的厚度范围为：20埃至50埃。
CN201710130767.XA 2017-03-07 2017-03-07 鳍式场效应管及其形成方法 Active CN108574009B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201710130767.XA CN108574009B (zh) 2017-03-07 2017-03-07 鳍式场效应管及其形成方法
US15/912,218 US10460996B2 (en) 2017-03-07 2018-03-05 Fin field effect transistor and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710130767.XA CN108574009B (zh) 2017-03-07 2017-03-07 鳍式场效应管及其形成方法

Publications (2)

Publication Number Publication Date
CN108574009A true CN108574009A (zh) 2018-09-25
CN108574009B CN108574009B (zh) 2021-04-02

Family

ID=63445054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710130767.XA Active CN108574009B (zh) 2017-03-07 2017-03-07 鳍式场效应管及其形成方法

Country Status (2)

Country Link
US (1) US10460996B2 (zh)
CN (1) CN108574009B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023035640A1 (zh) * 2021-09-10 2023-03-16 长鑫存储技术有限公司 半导体结构制作方法及半导体结构处理设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111341847B (zh) * 2018-12-19 2023-03-28 联华电子股份有限公司 半导体结构及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130302976A1 (en) * 2012-05-14 2013-11-14 United Microelectronics Corp. Method of forming semiconductor device
CN104112666A (zh) * 2013-04-22 2014-10-22 中国科学院微电子研究所 半导体器件及其制造方法
US20160104786A1 (en) * 2014-10-13 2016-04-14 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN106298665A (zh) * 2015-05-25 2017-01-04 中国科学院微电子研究所 半导体器件的制造方法
CN106409677A (zh) * 2015-07-30 2017-02-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497171B1 (en) * 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130302976A1 (en) * 2012-05-14 2013-11-14 United Microelectronics Corp. Method of forming semiconductor device
CN104112666A (zh) * 2013-04-22 2014-10-22 中国科学院微电子研究所 半导体器件及其制造方法
US20160104786A1 (en) * 2014-10-13 2016-04-14 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN106298665A (zh) * 2015-05-25 2017-01-04 中国科学院微电子研究所 半导体器件的制造方法
CN106409677A (zh) * 2015-07-30 2017-02-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023035640A1 (zh) * 2021-09-10 2023-03-16 长鑫存储技术有限公司 半导体结构制作方法及半导体结构处理设备

Also Published As

Publication number Publication date
CN108574009B (zh) 2021-04-02
US20180261508A1 (en) 2018-09-13
US10460996B2 (en) 2019-10-29

Similar Documents

Publication Publication Date Title
CN106684144B (zh) 半导体结构的制造方法
CN110875250B (zh) 半导体工艺的方法及半导体结构
CN105470132B (zh) 鳍式场效应管的形成方法
CN105225951B (zh) 鳍式场效应晶体管的形成方法
CN104821277B (zh) 晶体管的形成方法
CN108231588A (zh) 晶体管及其形成方法
KR102277762B1 (ko) 반도체 디바이스 및 제조 방법
CN108010884A (zh) 半导体结构及其形成方法
CN109585446A (zh) 半导体装置
CN109427664A (zh) 半导体结构及其形成方法
CN109994547A (zh) 半导体器件及其形成方法
CN106486374B (zh) 半导体结构的形成方法
CN109390235A (zh) 半导体结构及其形成方法
CN105226023A (zh) 半导体器件的形成方法
CN105513964A (zh) 晶体管的形成方法
CN105448730B (zh) 半导体结构及其形成方法
JP2004288891A (ja) 半導体装置およびその製造方法
CN104517842B (zh) 一种制作半导体器件的方法
CN108538724A (zh) 半导体结构及其形成方法
CN108574009A (zh) 鳍式场效应管及其形成方法
CN110164767A (zh) 半导体器件及其形成方法
CN107045981B (zh) 半导体结构的形成方法
CN106876273B (zh) 半导体结构的制造方法
CN107481932A (zh) 半导体结构的制造方法
CN106653693B (zh) 改善核心器件和输入输出器件性能的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant