CN109585446A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109585446A
CN109585446A CN201711216324.9A CN201711216324A CN109585446A CN 109585446 A CN109585446 A CN 109585446A CN 201711216324 A CN201711216324 A CN 201711216324A CN 109585446 A CN109585446 A CN 109585446A
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Prior art keywords
metal
substrate
self
gate
gate dielectric
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CN201711216324.9A
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CN109585446B (zh
Inventor
黄如立
庄英良
叶明熙
黄国彬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

根据一些实施例，本公开提供一种半导体装置，其具有可调谐功函数值的金属栅极结构。在一范例中，第一栅极结构及第二栅极结构形成于基底上，其中第一栅极结构包括具有第一材料的第一功函数金属，且第二栅极结构包括具有第二材料的第二功函数金属，第一材料不同于第二材料，其中第一栅极结构还包括：栅极介电层；具有金属磷酸盐的自保护层；及位于自保护层上的第一功函数金属。

Description

半导体装置
技术领域
本公开实施例涉及一种半导体装置及其形成方法。
背景技术
可靠地生产次半微米(sub-half micron)及更小的特征是半导体装置的下一代超大型集成电路(very large scale integration,VLSI)和极大型集成电路(ultra large-scale integration,ULSI)的关键技术挑战之一。然而，随着电路技术的限制的推进，超大型集成电路(VLSI)和极大型集成电路(ULSI)技术的缩小尺寸对处理能力具有更高的要求。在基底上可靠地形成栅极结构对于超大型集成电路(VLSI)和极大型集成电路(ULSI)的成功以及对于持续努力提高个别基底和晶粒的电路密度和品质非常重要。
随着半导体产业已经进入纳米技术工艺节点以追求更高的装置密度、更高的性能和更低的成本，来自制造和设计的挑战已造成三维设计的发展，例如鳍式场效晶体管(finfield effect transistors,FinFET)。一般的鳍式场效晶体管(FinFET)通过例如蚀刻至基底的硅层之中，从而被制造成具有从基底延伸的鳍结构。鳍式场效晶体管(FinFET)的沟道形成在垂直的鳍之中。提供栅极结构于鳍结构上方(例如：上覆并遮盖)。在沟道上具有栅极结构是有益的，从而允许栅极结构周围的沟道的栅极控制。鳍式场效晶体管(FinFET)装置提供许多优点，包括减少短沟道效应及增加电流。
随着装置尺寸持续微缩化(scaling down)，可以通过使用金属栅极电极而非典型的多晶硅栅极电极来改善鳍式场效晶体管(FinFET)装置性能。形成金属栅极堆叠的其中一工艺形成替代栅极工艺(也称为“后栅极(gate-last)”工艺)，其中最终栅极堆叠是“最后”制造的。然而，在具有复杂表面拓扑(topology)的高级工艺节点(advanced processnodes)中执行此类集成电路(IC)制造工艺存在挑战性。在栅极制造期间对于沉积和图案化工艺的不精确及不适当的控制可能使装置结构的电气性能产生不利地品质下降。
因此，需要制造具有期望的电气性能及良好界面控制的装置结构。
发明内容
根据一实施例，本公开提供一种半导体装置，包括：形成于基底上的第一栅极结构及第二栅极结构；其中第一栅极结构包括具有第一材料的第一功函数金属，且第二栅极结构包括具有第二材料的第二功函数金属，第一材料不同于第二材料，其中第一栅极结构还包括：栅极介电层；具有金属磷酸盐的自保护层；及位于自保护层上的第一功函数金属。
根据另一实施例，本公开提供一种半导体装置，包括：形成于基底上的栅极结构，其中栅极结构包括：栅极介电层；位于栅极介电层上的包含金属磷酸盐的自保护层，其中金属磷酸盐与栅极介电层具有共同的金属元素；及形成于自保护层上的功函数金属。
根据又一实施例，本公开提供一种半导体装置的形成方法，包括：使用蚀刻溶液将设置于基底上的栅极介电层上的第一功函数金属图案化，其中蚀刻溶液包括磷酸及酸溶液中的过氧化氢；以及一旦从基底移除第一功函数金属，则通过使栅极介电层暴露于蚀刻溶液以形成自保护层于栅极介电层上。
附图说明
以下将配合所附附图详述本公开的实施例，应注意的是，依照工业上的标准实施，以下图示并未按照比例绘制，事实上，可能任意的放大或缩小元件的尺寸以便清楚表现出本公开的特征。而在说明书及附图中，除了特别说明外，同样或类似的元件将以类似的符号表示。
图1A-图1B是根据一些实施例，用于制造装置结构于基底上的示例性工艺的流程图。
图2A-图2C1是根据一些实施例，半导体装置结构在图1的不同制造阶段的透视图。
图2C2-图2O是根据一些实施例，半导体装置结构在图1的不同制造阶段的剖面图。
图3A-图3C示出在图1所示的金属图案化工艺期间的表面结构反应的不同范例。
附图标记说明：
工艺100
步骤102
步骤104
步骤106
步骤108
步骤110
步骤112
步骤114
步骤116
步骤118
步骤120
步骤122
步骤124
步骤126
步骤128
步骤130
基底200
半导体装置结构201
鳍结构202
栅极介电层206
虚设栅极层208
硬掩模层210
虚设栅极结构212
凹槽214
隔离结构216
层间介电质(ILD)218
间隔物特征220
顶表面222
顶表面224
开口230
表面232
表面233
界面层240
栅极介电层242
第一功函数金属244
第一掩模结构248
p型装置区250a
n型装置区250b
底部抗反射涂层(BARC)252
光致抗蚀剂254
表面256
自保护层257
金属阻挡层261
第二功函数金属265
栅极电极金属276
金属栅极结构280
第二掩模结构291
光致抗蚀剂292
底部抗反射涂层(BARC)293
线A-A'
具体实施方式
以下提供许多不同的实施方法或是例子来实行各种实施例的不同特征。以下描述具体的元件及其排列的例子以阐述本公开。当然这些仅是例子且不该以此限定本公开的范围。例如，元件的尺寸并不限定于所公开的范围或数值，而是取决于工艺条件和/或装置所期望的性质。此外，在描述中提及第一个元件形成于第二个元件上时，其可以包括第一个元件与第二个元件直接接触的实施例，也可以包括有其他元件形成于第一个与第二个元件之间的实施例，其中第一个元件与第二个元件并未直接接触。为简化及清楚起见，各种特征可任意绘制成不同尺寸。
此外，其中可能用到与空间相关的用词，像是“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，这些关系词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系。这些空间关系词包括使用中或操作中的装置的不同方位，以及图示中所描述的方位。装置可能被转向不同方位(旋转90度或其他方位)，则其中使用的空间相关形容词也可相同地照着解释。
本公开实施例大体而言涉及半导体装置，更具体涉及形成在半导体装置中的替代栅极。本公开实施例提供一种保护层的结构及其形成方法，该保护层在替代栅极制造工艺中保护形成在栅极结构中的栅极介电层。在此所述的一些范例显示于鳍式场效晶体管(FinFET)的上下文中。在其他实施方式中，根据一些实施例，可在垂直栅极全环(vertical,gate all around,VGAA)装置、水平栅极全环(horizontal,gate all around,HGAA)装置或其他装置中执行替代栅极及工艺。此外，可在任何高级技术节点(advanced technologynodes)中执行实施例。
在用于形成晶体管的金属栅极的替代栅极工艺中，形成虚设栅极堆叠于基底上方，以作为随后形成于实际栅极堆叠上的占位符(placeholder)。形成间隔物结构在虚设栅极堆叠的周围。在形成相邻于间隔物结构的源极/漏极特征和层间介电质(interlayerdielectric,ILD)之后，移除虚设栅极堆叠，并留下被间隔物结构和层间介电质(ILD)所包围的开口。接着，形成金属栅极于由间隔物结构和层间介电质(ILD)所定义的开口中。
金属栅极结构包括诸如高介电常数(high-k)介电层的栅极介电层、可选的阻挡层、功函数金属层和栅极金属电极。可使用多重沉积和图案化工艺以形成功函数金属层，例如：微调晶体管的阈值电压(threshold voltage,Vt)。在一些实施例中，功函数金属层可对不同类型的晶体管使用不同的材料，例如：p型鳍式场效晶体管(FinFET)或n型鳍式场效晶体管(FinFET)，以根据需要提高装置的电气性能。可在图案化工艺期间可选地使用阻挡层以保护栅极介电层。然而，在一些清洁和/或蚀刻工艺中可能会不慎地蚀刻栅极介电层和可选的阻挡层。因此，栅极介电层和可选的阻挡层可能会在金属栅极结构中失去其效用和功能。本公开实施例可以解决上述问题。
图1示出用于形成半导体装置结构的工艺100的示例性流程图，例如图2A-图2O所示的装置结构201。图2A-图2C1及图2C2-图2O分别是根据一些实施例，对应于工艺100的各个阶段的部分基底的透视图及示意性剖面图。应注意的是，工艺100可用于形成任何合适的结构，包括图2A-图2O所示的半导体装置结构201或在此未呈现的其它半导体结构。
工艺100开始于步骤102，如图2A所示，提供具有多个鳍结构202形成在其上的基底200。
基底200可以是或包括块状半导体基底、绝缘体上半导体(semiconductor-on-insulator,SOI)基底或其它基底。基底200的半导体材料可包括或选自硅(例如：像是Si<100>或Si<111>的硅晶体)、硅锗、锗、砷化镓或其它半导体材料中的至少一种材料。半导体材料可为掺杂或未掺杂的，例如：具有p型或n型掺杂剂。在将绝缘体上半导体(SOI)结构用于基底200的一些实施例中，基底200可包括设置在绝缘层上的半导体材料，其可为设置在半导体基底中的埋藏绝缘体，或其可为玻璃或蓝宝石基底。在本文所述的实施例中，基底200为含硅材料，例如晶体硅基底。此外，基底200不限于任何特定的尺寸、形状或材料。基底200可为具有200mm直径、300mm直径或其它直径(例如：450mm等)的球形/圆形基底。基底200也可为任何多边形、正方形、矩形、弧形或其它非圆形的工件，例如：根据需要的多边形基底。
每个鳍结构202提供形成有一或多个装置的主动区。使用包括掩模、光刻和/或蚀刻工艺的合适的工艺来制造鳍结构202。在一个范例中，形成掩模层使其上覆于基底200。光刻工艺包括形成上覆于掩模层的光致抗蚀剂层(光致抗蚀剂)、将光致抗蚀剂层暴露于图案、实行后曝光烘烤工艺以及将光致抗蚀剂层显影以使光致抗蚀剂层图案化。使用合适的蚀刻工艺将光致抗蚀剂层的图案转移到掩模层以形成掩模元件。接着，可使用掩模元件来保护基底200的区域，同时蚀刻工艺形成凹槽214于基底中，留下延伸的鳍，例如鳍结构202。可使用反应性离子蚀刻(reactive ion etch，RIE)和/或其它合适的方法来蚀刻凹槽214。可利用在基底上形成鳍结构的方法的许多其它实施例。
在一实施例中，鳍结构202的宽度大约为10纳米(nm)，高度大约为10nm至60nm，例如约为50nm高。然而，应当理解，其他尺寸可用于鳍结构202。在一个范例中，鳍结构202包括硅材料或其它元素半导体(例如锗)，包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体。鳍结构202也可为包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其组合的合金半导体。此外，鳍结构202可根据需要使用n型和/或p型掺杂剂进行掺杂。
如上所述，在一个范例中，可通过蚀刻基底200的一部分而形成多个鳍结构202，以形成凹槽214于基底200中。接着凹槽214可填充有隔离材料，使隔离材料凹陷或回蚀隔离材料以形成隔离结构216。用于隔离结构216和/或鳍结构202的其它制造技术是可能的。隔离结构216可隔离基底200的一些区域，例如：鳍结构202中的主动区。在一个范例中，隔离结构216可由浅沟槽隔离(shallow trench isolation,STI)结构和/或其它合适的隔离结构。浅沟槽隔离(STI)结构可由氧化硅、氮化硅、氮氧化硅、掺杂氟化物的硅酸盐玻璃(fluoride-doped silicate glass,FSG)、低介电常数(low-k)介电材料和/或其它合适的绝缘材料所形成。浅沟槽隔离(STI)结构可包括多层结构，例如具有一或多个衬层。
虚设栅极结构212形成在鳍结构202上方。在图2A所示的范例中，虚设栅极结构212包括栅极介电层206、虚设栅极层208和硬掩模层210。应注意的是，虚设栅极结构212可还包括盖层和/或其它合适的层。可通过合适的沉积技术形成虚设栅极结构212中的各个层，并通过合适的光刻和蚀刻技术进行图案化。虚设栅极结构212于鳍结构202的二或三个面上接合(engages)鳍结构202。在此所述的术语“虚设”是指将于稍后阶段中被移除的牺牲结构，且将在替代栅极工艺中被替换成实际栅极结构，例如：高介电常数(high-k)金属栅极结构。替代栅极工艺是指在整个栅极制造工艺的后期制造栅极结构。栅极介电层206可为介电氧化层。举例而言，可通过化学氧化、热氧化、原子层沉积(atomic layer deposition,ALD)、化学气相沉积(chemical vapor deposition,CVD)和/或其它合适的方法以形成介电氧化层。虚设栅极层208可为多晶硅层或其它合适的层。举例而言，可通过合适的沉积工艺(例如：低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)和等离子体增强化学气相沉积(plasma-enhanced CVD,PECVD))以形成虚设栅极层208。硬掩模层210可为适合于将虚设栅极结构212图案化成所需的特征/尺寸于基板上的任何材料。
在一实施例中，先沉积虚设栅极结构212的各个层以作为毯覆层。接着，通过包括光刻和蚀刻的工艺将毯覆层图案化，移除部分的毯覆层并使剩余的部分维持在隔离结构216和鳍结构202上以形成虚设栅极结构212。
在一个范例中，半导体装置结构201包括p型装置区250a和n型装置区250b。可在p型装置区250a中形成一或多个p型装置，例如p型鳍式场效晶体管(FinFET)，且可在n型装置区250b中形成一或多个n型装置，例如n型鳍式场效晶体管(FinFET)。半导体装置201可包括在集成电路(IC)中，例如微处理器、记忆装置和/或其他集成电路(IC)。
在步骤104中，如图2B所示，形成间隔物特征220于虚设栅极结构212的侧壁上，接着，形成层间介电质(interlayer dielectric,ILD)218于间隔物特征220上。间隔物特征220包括不同于用于虚设栅极结构212的材料。在一实施例中，间隔物特征220包括介电材料，例如：氮化硅或氮氧化硅。在一个范例中，间隔物特征220可为单层或多层。在一实施例中，在形成虚设栅极结构212之后，通过在装置结构201上方共形地沉积间隔物材料以形成一或多个间隔物层。随后，如图2B所示，实行异向性蚀刻工艺以移除部分的间隔物层，从而形成间隔物特征220。
在形成间隔物特征220之后，实行一或多个外延生长工艺以生长硅特征，从而形成源极/漏极区(未示出)。外延生长工艺可利用用于形成p型装置区250a的p型掺杂剂或用于形成n型装置区250b的n型掺杂剂来原位(in-situ)掺杂生长的硅。
随后，形成层间介电质(ILD)218于基底200和间隔物特征220上。在一些实施例中，装置201可还包括位于层间介电质(ILD)218下方以及基底200和间隔物特征220上方的接触蚀刻停止层(未示出)。层间介电质(ILD)218可包括诸如以下的材料：四乙基正硅酸盐(tetraethylorthosilicate,TEOS)氧化物、未掺杂的硅酸盐玻璃、掺杂的氧化硅(例如：硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、熔融二氧化硅玻璃(fused silicaglass,FSG)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼掺杂硅玻璃(boron dopedsilicon glass,BSG))和/或其它合适的介电材料。可通过等离子体增强化学气相沉积(PECVD)工艺、高密度等离子体化学气相沉积(High Density Plasma Chemical VaporDeposition,HDP-CVD)工艺或其他合适的沉积技术来沉积层间介电质(ILD)218。在一实施例中，通过化学气相沉积(CVD)工艺形成层间介电质(ILD)218以填充凹槽214。如图2B所示，在各种沉积工艺之后，进行化学机械平坦化(chemical mechanical planarization,CMP)工艺以将层间介电质(ILD)218平坦化，并定义与虚设栅极结构212的顶表面222大抵上共平面的顶表面224，虚设栅极结构212暴露在用于随后的制造步骤的基底200上。
在步骤106中，如图2C1所示，从基底200移除虚设栅极结构212以定义层间介电质(ILD)218中的开口230。在图2C1所示的实施例中，开口230暴露隔离结构216的表面232。图2C2示出沿着包含层间介电质(ILD)218所定义的开口230的线A-A'所切割的剖面图，以便于描述装置制造工艺。
开口230允许在其中形成栅极结构。尽管图2C2所示的范例暴露鳍结构202的表面233，但应注意的是，所暴露的表面也可包括与基底不同的结构(例如：隔离结构216)或与基底200不同的其它位置。
可使用蚀刻工艺移除虚设栅极结构212。蚀刻工艺可包括合适的湿蚀刻、干(等离子体)蚀刻和/或其它工艺。举例而言，干蚀刻工艺可使用含氯气体、含氟气体、其它蚀刻气体或上述的组合。湿蚀刻溶液可包括NH4OH、氢氟酸(hydrofluoric acid,HF)或稀释的氢氟酸(HF)、去离子水、四甲基氢氧化铵(tetramethylammonium hydroxide,TMAH)、其它合适的湿蚀刻溶液或上述的组合。
在步骤108中，如图2D所示，在由间隔物特征220所定义的开口230中依序地形成界面层240、栅极介电层242和第一功函数金属244。在一个范例中，界面层240可包括诸如氧化硅(SiO2)或氮氧化硅(SiON)等的介电材料。可通过化学氧化、热氧化、原子层沉积(atomiclayer deposition,ALD)、化学气相沉积(CVD)和/或其它合适的介电质以形成界面层240。
栅极介电层242可包括高介电常数材料，例如：氧化铪(HfO2)、Al2O3、氧化镧(LaO2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、上述的组合或其它合适的材料。可通过原子层沉积(ALD)和/或其他合适的方法形成栅极介电层242。应注意的是，当不存在界面层240时，栅极介电层242可直接形成在基底200上(例如，在鳍结构202上)。
在形成栅极介电层242之后，形成第一功函数金属244于栅极介电层242上。第一功函数金属244是形成用以调谐(tuning)装置的功函数。第一功函金属244可为p型装置区250a中用于p型鳍式场效晶体管(FinFET)装置的p型功函数材料或者n型装置区中250b用于n型鳍式场效晶体管(FinFET)装置的n型功函数材料。p型功函数材料的合适范例(其可具有4.8eV至5.2eV的功函数)包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的p型功函数材料或上述的组合；且n型功函数材料的合适范例(其可具有3.9eV至4.3eV的功函数)包括Ti、Ag、TaAl、TaAlC、HfAl、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的n型功函数材料或上述的组合。
功函数值与第一功函数金属244的材料组成相关。选择第一功函数金属244的材料以调谐其功函数值，从而在将形成于相应区域的装置中达到期望的阈值电压(thresholdvoltage,Vt)。第一功函数金属244提供均匀的阈值电压(Vt)。可通过化学气相沉积(CVD)、原子层沉积(ALD)和/或其它合适的方法沉积第一功函数金属244。在此所示的范例中，使用原子层沉积(ALD)工艺形成第一功函数金属244。
可通过在原子层沉积(ALD)工艺期间改变工艺参数(例如：沉积时间、前驱物脉冲的数量、脉冲频率、基底温度、压力等)以改变及调整第一功函数金属层244的厚度。在一个范例中，通过改变用于沉积第一功函数金属层244的原子层沉积(ALD)工艺的沉积时间以调整第一功函数金属层244的厚度。
在步骤110中，如图2E所示，第一掩模结构248设置在n型装置区250b上并填充基底200的装置结构201的n型装置区250b中的开口230。第一掩模结构248覆盖装置结构201的n型装置区250b，并暴露装置结构201的p型装置区250a以用于进一步的蚀刻。第一掩模结构248在蚀刻/图案化工艺期间作为掩模，以保护由第一掩模结构248所覆盖的结构免于在蚀刻/图案化工艺期间受到损坏。
第一掩模结构248可包括设置在底部抗反射涂层(bottom anti-reflectivecoating,BARC)252上的光致抗蚀剂254。可以通过光刻工艺将光致抗蚀剂254图案化使其具有可作为掩模的期望的尺寸以转移特征至基底200上。底部抗反射涂层(BARC)252可为涂布到基底200上的有机材料，并填充图2E所示的n型装置区250b的开口230。尽管图2E所示的范例显示第一掩模结构248形成并填充于n型装置区250b所定义的开口230中，但应注意的是，第一掩模结构248可形成在基底的其他部分，例如：p型装置区250a。
在步骤112中，如图2F所示，进行蚀刻工艺以从基底200的p型装置区250a的开口230移除第一功函数金属244。蚀刻工艺可为通过蚀刻溶液浸渍或浸泡基板200所进行的湿蚀刻工艺。在另一个范例中，利用诸如气相或等离子体工艺的干蚀刻工艺以移除p型装置区250a中的第一功函数金属244。在又一个范例中，利用湿蚀刻工艺及干蚀刻工艺的组合以移除p型装置区域250a中的第一功函数金属244。在具体的范例中，在步骤112中，从p型装置区250a的开口230移除第一功函数金属244是通过将基底浸入(dipping)、浸渍(immersing)或浸泡(soaking)在湿蚀刻槽内的蚀刻溶液中所进行的湿蚀刻工艺。蚀刻溶液可为pH值在预定范围内的碱性、中性或酸性溶液。蚀刻溶液的选择是基于欲从基底200所移除的第一功函数金属244的材料类型。
在一实施例中，蚀刻溶液包括磷酸(或正磷酸)，例如：在水溶液(例如：H2O)中85重量百分比(85wt％)的H3PO4。进一步地，在此实施例中，蚀刻溶液可包括磷酸与其它成分(例如：过氧化氢(H2O2))的混合物。也可使用其它蚀刻剂，例如：氢氟酸(HF)、盐酸(HCl)和/或硫酸(H2SO4)。在一个范例中，蚀刻溶液的去离子水中磷酸的比例为约1:5至约1:50。
在一个范例中，蚀刻溶液是与来自第一功函数金属244的材料反应的酸溶液。酸溶液蚀刻第一功函数金属244，例如：含金属材料。可添加其他蚀刻剂，例如：氢氟酸(HF)、盐酸(HCl)和/或硫酸(H2SO4)，以对给定浓度提供不同的pH值。这些蚀刻剂可用于维持期望的pH值和/或帮助溶解在蚀刻溶液中的化合物的解离。可以将蚀刻溶液的pH值控制在小于或约等于6，例如小于4，或更特别地，例如小于2。在具体的实例中，蚀刻溶液的pH值小于1。在一个范例中，可将蚀刻工艺维持在约20至约80度的摄氏温度。
在步骤114中，如图2G所示，一旦移除p型装置区250a中的第一功函数金属244，当蚀刻溶液遇到栅极介电层242的表面256时，同时形成自保护层(self-protective layer)257于栅极介电层242上。由于磷酸螯合，自保护层257形成在栅极介电层242的表面256上(包括底部和侧壁部分的表面)。由选择用于栅极介电层242的来自高介电常数材料的金属元素(例如：Hf、Zr或Ta等)与来自磷酸的磷元素反应以形成自保护层257。保护层包括金属磷酸盐(例如：含金属磷酸螯合物或含金属错合剂)，以保护栅极介电层242的表面256免于受到进一步蚀刻。当栅极介质层242的表面256暴露时，嵌入在栅极介电层242中的金属元素也同时暴露出来，并触发嵌入在栅极介电层242中的金属元素与来自磷酸的磷元素发生化学反应，以形成作为自保护层257的金属磷酸盐。金属磷酸盐的一些金属元素嵌入在栅极介电层242中，而金属磷酸盐的一些金属元素形成为自保护层257。自保护层257进一步防止磷酸穿透并蚀刻栅极介电层242。
在一个范例中，栅极介电层242包括铪(Hf)元素，例如HfO2或HfSiO4或其他含铪(Hf)的介电质。如图3A所示，通过形成磷酸盐金属键结(P-Hf键结)，铪(Hf)元素与蚀刻溶液反应以形成含铪(Hf)磷酸螯合物或含铪(Hf)磷酸盐(或称为含铪(Hf)络合剂)。磷酸盐头部基可从栅极介电层242配位到含有铪(Hf)元素的表面上，形成单齿和双齿络合物以保护栅极介电层242。形成在来自栅极介电层242的高介电常数材料中的磷酸盐金属键结在界面处提供良好的键结，将自保护层257结合到栅极介电层242上。
相似地，在另一个范例中，栅极介电层242包括锆(Zr)或钽(Ta)元素，例如：ZrO2、Ta2O5或其他含锆(Zr)或钽(Ta)的介电质。分别如图3B及图3C所示，通过形成磷酸盐金属键结(P-Zr键结或P-Ta键结)，金属元素与蚀刻溶液反应以形成含锆(Zr)或含钽(Ta)磷酸螯合物或者含锆(Zr)或含钽(Ta)磷酸盐(或是称为含锆(Zr)或含钽(Ta)络合剂)。磷酸盐头部基可从栅极介电层242配位到含有锆(Zr)或钽(Ta)元素的表面上，形成单齿和双齿络合物以保护栅极介电层242。
如图2G所示，由于栅极介质层242与来自蚀刻溶液的成分键结，当栅极介电层242的表面256(包括底部和侧壁部分的表面)暴露时，自保护层257形成在栅极介质层242上。接着，自保护层257的形成导致开口230中第一功函数金属244的蚀刻在栅极介电层242处自动停止。因为来自自保护层257的金属元素是源自于来自栅极介电层242的金属元素，故栅极介电层242与自保护层257具有共同的形成于其中的金属元素。该共同的金属元素可为Ta、Ti、Hf、Zr或其组合，或是被选择用以制造栅极介电层242的金属介电材料的任何合适的材料。
在形成自保护层257之后，可将基底200从蚀刻溶液中移除。可进行冲洗工艺以从开口230移除蚀刻残余物(例如：磷酸盐单层)。举例而言，冲洗工艺可使用含有去离子水、碳化去离子水(carbonized DI water)的溶液，例如：具有二氧化碳的去离子水或具有NH4OH的去离子水。可在约20至约80度的摄氏温度下进行冲洗工艺。此外，也可进行干燥工艺以使基底200的表面干燥。举例而言，干燥工艺可包括在存在氮气流的情况下旋转干燥基底200。举例而言，干燥工艺可包括异丙醇(isoprophyl alcohol,IPA)干燥工艺。
在步骤116中，如图2H所示，在p型装置区250a中形成自保护层257之后，接着将第一掩模结构248从装置结构201的n型装置区250b移除。在移除第一掩模结构248之后，第一功函数金属244暴露于n型装置区250b中以及自保护层257形成于p型装置区250a中。
在步骤118中，如图2I所示，可共形地形成可选的金属阻挡层261于自保护层257上。如上所述，当来自栅极介电层242的金属元素遇到来自磷酸的磷元素时，会发生化学反应以形成包含磷酸螯合物的自保护层257。相似地，将可选的金属阻挡层261的材料选择为包括金属元素，该金属元素能够与自保护层257中来自磷酸螯合物的磷元素反应，以形成具有良好接合性的键结并达成良好的界面控制。形成的金属阻挡层261可提供更宽的工艺容许范围(process windows)，其可帮助调谐金属栅极结构的功函数值，该金属栅极结构将被形成及完成于层间介电质(ILD)218所定义的开口230之中。功函数值的调谐有助于在将形成于相应区域的装置中达到期望的阈值电压(Vt)。因此，通过可选地形成金属阻挡层261于开口230中，其在后续将形成为金属栅极结构的一部分，可得到用以形成金属栅极结构的膜架构(film scheme)的更多选择，使得金属栅极结构的功函数值可更有弹性地调整或维持。
在一个范例中，形成在自保护层257上的金属阻挡层261为含钽(Ta)层。如前面图3C所述，磷元素与钽(Ta)元素具有相对较强的键结能量。因此，含有钽(Ta)元素的金属阻挡层261在金属阻挡层261与自保护层257和/或栅极介电层242之间提供具有强键结的界面，该界面包括遵循图3C所示的相似的反应机制的含钽(Ta)磷酸螯合物。具有钽(Ta)元素的金属阻挡层261也有助于更加稳固地在栅极介电层242与金属阻挡层261之间密封自保护层257，以提供良好的界面控制和接合处理。应注意的是，也可以使用含有金属元素(其可与磷元素反应并与磷元素形成键结)的其它金属介电质来形成金属阻挡层261。金属阻挡层261的合适范例包括含钽(Ta)层、含钛(Ti)层等。在一个范例中，金属阻挡层261选自Ta2O5、TaSiON、TaSiO、TiN、TiON、TiO、TiSiO等。可通过化学气相沉积(CVD)、原子层沉积(ALD)和/或其他合适的工艺来沉积金属阻挡层261。在此所述的一个范例中，使用原子层沉积(ALD)工艺形成金属阻挡层261。
在步骤120中，如图2J所示，在可选金属阻挡层261形成在开口230中之后，共形地形成第二功函数金属265在可选的金属阻挡层261上。被选择用来制造第二功函数金属265的材料(其在多重图案化工艺之后将保留在p型装置区250a中)可不同于存在基底200的n型装置区250b上的第一功函数金属244。
如上所述，功函数值与第一功函数金属244及第二功函数金属265的材料组成相关。通过利用不同的材料在基底200的不同装置区(例如：p型和n型装置区250a和250b)中制造第一功函数金属244和第二功函数金属265，可根据需要更有弹性地调整及调谐金属栅极结构的功函数值。p型功函数材料的合适范例(其可具有4.8eV至5.2eV的功函数)包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的p型功函数材料或上述的组合；且n型功函数材料的合适范例(其可具有3.9eV至4.3eV的功函数)包括Ti、Ag、TaAl、TaAlC、HfAl、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的n型功函数材料或上述的组合。
可通过化学气相沉积(CVD)、原子层沉积(ALD)和/或其它合适的方法沉积第二功函数金属265。
在此所示的一个范例中，使用原子层沉积(ALD)工艺来形成第二功函数金属265。可通过在原子层沉积(ALD)工艺期间改变工艺参数(例如：沉积时间、前驱物脉冲的数量、脉冲频率、基底温度、压力等)以改变及调整第二功函数金属265的厚度。在一个范例中，通过改变用于沉积第二功函数金属265的原子层沉积(ALD)工艺的沉积时间以调整第二功函数金属265的厚度。
在步骤122中，如图2K所示，在形成第二功函数金属265之后，将第二掩模结构291设置在p型装置区250a上并填充基底200的装置结构201的p型装置区250a中的开口230。第二掩模结构291覆盖装置结构201的p型装置区250a，并暴露装置结构201的n型装置区250b以用于进一步的蚀刻。第二掩模结构291在蚀刻/图案化工艺期间作为掩模，以保护由第二掩模结构291所覆盖的结构免于在蚀刻/图案化工艺期间受到损坏。
相似于上述的第一掩模结构248，第二掩模结构291可包括设置在底部抗反射涂层(BARC)293上的光致抗蚀剂292。可以通过光刻工艺将光致抗蚀剂292图案化使其具有可作为掩模的期望的尺寸以转移特征至基底200上。底部抗反射涂层(BARC)293可为涂布到基底200上的有机材料，并填充图2K所示的p型装置区250a的开口230。应注意的是，第一掩模结构248及第二掩模结构291是在工艺的不同阶段形成，以蚀刻基底的不同区域的层，进而在基底的不同区域形成不同的膜架构以满足不同的装置性能需求及调整。
在步骤124中，如图2L所示，进行蚀刻工艺以从基底200的n型装置区250b移除第二功函数金属265及可选的金属阻挡层261。蚀刻工艺可为通过蚀刻溶液浸渍或浸泡基板200所进行的湿蚀刻工艺。在另一个范例中，利用诸如气相或等离子体工艺的干蚀刻工艺以移除n型装置区250b中的第二功函数金属265及可选的金属阻挡层261。在又一个范例中，利用湿蚀刻工艺及干蚀刻工艺的组合以移除n型装置区域250b中的第二功函数金属265及可选的金属阻挡层261。在具体的范例中，在步骤124中，移除n型装置区250b中的第二功函数金属265及可选的金属阻挡层261是通过将基底浸入(dipping)、浸渍(immersing)或浸泡(soaking)在湿蚀刻槽内的蚀刻溶液中所进行的湿蚀刻工艺。蚀刻溶液可为pH值在预定范围内的碱性、中性或酸性溶液。蚀刻溶液的选择是基于欲从基底200所移除的第二功函数金属265及可选的金属阻挡层261的材料类型。
在步骤126中，如图2M所示，在从n型装置区250b移除第二功函数金属265和可选的金属阻挡层261之后，接着从装置结构201的p型装置区250a移除第二掩模结构291。在移除第二掩模结构291之后，第二功函数金属265暴露于p型装置区250a中以及第一功函数金属244形成于n型装置区250b中。
因此，形成在p型装置区250a中的膜架构(例如：栅极介电层242、自保护层257、可选的金属阻挡层261和第二功函数金属层265)被配置为不同于形成在基底200的n型装置区250b中的膜架构(例如：栅极介电层242和第一功函数金属层244)。通过对装置结构201的不同区域中(例如：p型装置区250a或n型装置区250b)的不同结构使用不同膜架构及不同材料，可更有弹性且有效地调整并增进形成在装置结构201中的金属栅极结构的功函数值或其他相关的电气性能。
此外，通过在栅极介电层242与第二功函数金属层265(或可选的金属阻挡层261)之间的界面处形成自保护层257，可以获得并达成良好的界面控制以及电气性能增强及调整。
在步骤128中，如图2N所示，在将第二掩模结构291从基底200移除之后，将栅极电极金属276填充至层间介电层(ILD)218所定义的开口230之中，以完成金属栅极结构280。栅极电极金属276也可称为金属填充层，其是通过化学气相沉积(CVD)、物理气相沉积(PVD)、电镀和/或其他合适的工艺所形成。栅极电极金属276可包括Al、W或Cu和/或其他合适的材料。在一个范例中，在形成栅极电极金属276之前，可形成衬层(未示出)(例如：TiN、TaN、TiON、TaON等)于基底上。
在步骤130中，如图2O所示，可进行化学机械平坦化(CMP)工艺以从金属栅极结构280移除多余的材料，以将装置201的顶表面平坦化。
虽然并非意在限制，但本公开的一或多个实施例对半导体装置及其形成提供许多益处。举例而言，本公开的实施例提供用于在替换栅极工艺中将功函数金属层图案化的方法。根据本公开实施例，可利用包含磷酸(或正磷酸)及在酸基溶液中的过氧化氢的蚀刻溶液以将功函数金属图案化。一旦从基底移除功函数金属且暴露下方的栅极介电层之后，可以在栅极介电层上方形成自保护层以终止图案化工艺。因此，自保护层可保持其阻挡及桥接能力，以在装置的不同位置形成具有不同变化的膜架构，进而以增进电气性能。此外，在形成功函金属之前，可在自保护层上形成可选的金属阻挡层，以在界面处提供弹性的调谐特征，从而对装置提供不同的功函数值。可在任何现有的湿蚀刻工具中进行使用包含磷酸的蚀刻剂的图案化工艺。
根据一实施例，本公开提供一种半导体装置，包括：形成于基底上的第一栅极结构及第二栅极结构；其中第一栅极结构包括具有第一材料的第一功函数金属，且第二栅极结构包括具有第二材料的第二功函数金属，第一材料不同于第二材料，其中第一栅极结构还包括：栅极介电层；具有金属磷酸盐的自保护层；及位于自保护层上的第一功函数金属。
如前述的半导体装置，其中第一栅极结构还包括：位于自保护层与第一功函数金属之间的金属阻挡层。
如前述的半导体装置，还包括：位于第一功函数金属上的栅极电极金属。
如前述的半导体装置，其中来自金属磷酸盐的金属元素内嵌于栅极介电层中。
如前述的半导体装置，其中栅极介电层与自保护层共享共同的金属元素。
如前述的半导体装置，其中共同的金属元素为Ta、Ti、Hf、Zr或其组合的至少其中之一。
如前述的半导体装置，其中金属阻挡层为含钽(Ta)层。
如前述的半导体装置，其中金属阻挡层与自保护层在其之间的介面处形成含钽(Ta)磷酸盐键结。
如前述的半导体装置，其中栅极介电层系选自氧化铪(HfO2)、Al2O3、氧化镧(LaO2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2或其组合的至少其中之一的高介电常数材料。
如前述的半导体装置，其中第一栅极结构还包括栅极介电层下方的界面层。
如前述的半导体装置，其中第一功函数金属是用于n型鳍式场效晶体管(FinFET)，且第二功函数金属是用于p型鳍式场效晶体管(FinFET)。
根据另一实施例，本公开提供一种半导体装置，包括：形成于基底上的栅极结构，其中栅极结构包括：栅极介电层；位于栅极介电层上的包含金属磷酸盐的自保护层，其中金属磷酸盐与栅极介电层具有共同的金属元素；及形成于自保护层上的功函数金属。
如前述的半导体装置，其中共同的金属元素为Ta、Ti、Hf、Zr或其组合的至少其中之一。
如前述的半导体装置，还包括：位于自保护层上的金属阻挡层，其中金属阻挡层与来自自保护层的金属磷酸盐接合。
如前述的半导体装置，其中金属阻挡层为含钽(Ta)材料。
根据又一实施例，本公开提供一种半导体装置的形成方法，包括：使用蚀刻溶液将设置于基底上的栅极介电层上的第一功函数金属图案化，其中蚀刻溶液包括磷酸及酸溶液中的过氧化氢；以及一旦从基底移除第一功函数金属，则通过使栅极介电层暴露于蚀刻溶液以形成自保护层于栅极介电层上。
如前述的半导体装置的形成方法，还包括：形成第二功函数金属于自保护层上。
如前述的半导体装置的形成方法，其中自保护层包括与栅极介电层具有共同金属元素的金属磷酸盐。
如前述的半导体装置的形成方法，其中共同金属元素为Ta、Ti、Hf、Zr或其组合的至少其中之一。
如前述的半导体装置的形成方法，还包括：形成金属阻挡层于自保护层上，其中金属阻挡层与来自自保护层的金属磷酸盐接合。
前述内容概述了许多实施例的特征，使本领域普通技术人员可以更佳的了解本公开的各个方面。本领域普通技术人员应该可理解，他们可以很容易的以本公开为基础来设计或修饰其它工艺及结构，并以此达到相同的目的和/或达到与本公开介绍的实施例相同的优点。本领域普通技术人员也应该了解这些相等的结构并不会背离本公开的构思与范围。本公开可以作各种改变、置换、修改而不会背离本公开的发明构思与范围。

Claims (1)

1.一种半导体装置，包括：
一第一栅极结构及一第二栅极结构，形成于一基底上；其中该第一栅极结构包括具有一第一材料的一第一功函数金属，且该第二栅极结构包括具有一第二材料的一第二功函数金属，该第一材料不同于该第二材料，其中该第一栅极结构还包括：
一栅极介电层；
一自保护层，其具有金属磷酸盐；及
该第一功函数金属，位于该自保护层上。
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