CN109216356B - 半导体器件结构、半导体器件及其形成方法 - Google Patents

半导体器件结构、半导体器件及其形成方法 Download PDF

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CN109216356B
CN109216356B CN201810455390.XA CN201810455390A CN109216356B CN 109216356 B CN109216356 B CN 109216356B CN 201810455390 A CN201810455390 A CN 201810455390A CN 109216356 B CN109216356 B CN 109216356B
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layer
gate dielectric
dielectric layer
self
gate
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CN109216356A (zh
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黄如立
庄英良
叶明熙
黄国彬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

提供了具有可调功函值的金属栅极结构的半导体器件结构。在一个实例中，半导体器件包括位于衬底上的第一栅极结构和第二栅极结构；其中，第一栅极结构包括具有第一材料的第一栅极介电层，并且第二栅极结构包括具有第二材料的第二栅极介电层，第一材料与第二材料不同，其中，第一栅极结构和第二栅极结构还包括分别设置在第一栅极介电层和第二栅极介电层上的第一自保护层和第二自保护层，其中，第一自保护层包括金属磷酸盐，并且第二自保护层包括含硼络合剂，以及位于第一栅极结构中的第一自保护层上的第一功函调整层。本发明的实施例还涉及在不同材料的高K介电层上形成的自保护层。本申请的实施例提供了一种半导体器件结构、半导体器件及其形成方法。

Description

半导体器件结构、半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体器件结构、半导体器件及其形成方法，具体地，涉及在不同材料的高K介电层上形成的自保护层。
背景技术
随着半导体工业在追求更高的器件密度、更高的性能和更低的成本的过程中进入纳米技术工艺节点，来自制造和设计的挑战已经引起了诸如鳍式场效应晶体管(FinFET)的三维设计的发展。典型的FinFET制造为具有从衬底延伸的鳍结构，例如通过蚀刻至衬底的硅层内。在垂直鳍中形成FinFET的沟道。在鳍结构上方(例如，覆盖以包裹)提供栅极结构。在通道上具有栅极结构是有益的，允许栅极结构周围的沟道的栅极控制。FinFET器件提供了许多优势，包括减少短沟道效应和增加电流。
随着器件尺寸持续按比例缩小，可以通过使用金属栅电极而不是典型的多晶硅栅电极来改进FinFET器件的性能。形成金属栅极堆叠件的一个工艺是其中“后”制造栅极堆叠件的替换栅极工艺(也称为“后栅极”工艺)。然而，在具有复杂表面拓扑结构和不同表面材料的先进工艺节点中实施这种IC制造工艺存在挑战。在栅极制造期间对沉积和图案化工艺的不精确和不适当的控制可能不利地恶化器件结构的电性能。
发明内容
本发明的实施例提供了一种半导体器件，包括：第一栅极结构和第二栅极结构，位于衬底上；其中，所述第一栅极结构包括具有第一材料的第一栅极介电层，并且所述第二栅极结构包括具有第二材料的第二栅极介电层，所述第一材料与所述第二材料不同，其中，所述第一栅极结构和所述第二栅极结构还包括：第一自保护层和第二自保护层，分别设置在所述第一栅极介电层和所述第二栅极介电层上，其中，所述第一自保护层包括金属磷酸盐，并且所述第二自保护层包括含硼络合剂；以及第一功函调整层，位于所述第一栅极结构中的所述第一自保护层上。
本发明的另一实施例提供了一种半导体器件结构，包括：栅极结构，形成在衬底上，其中，所述栅极结构包括：栅极介电层；自保护层，位于所述栅极介电层上，所述自保护层包括金属磷酸盐或含硼络合剂，其中，所述金属磷酸盐与所述栅极介电层具有共同的金属元素，或所述含硼络合剂与所述栅极介电层具有共同的硅元素；以及功函调整层，形成在所述自保护层上。
本发明的又一实施例提供了一种用于形成半导体器件的方法，包括：使用蚀刻溶液图案化设置在衬底上的第一栅极介电层和第二栅极介电层上的功函调整层，其中，所述蚀刻溶液包括酸性溶液中的磷酸、硼酸和过氧化氢，其中，所述第一栅极介电层和所述第二栅极介电层每个均包括不同类型的材料；以及当从所述第一栅极介电层和所述第二栅极介电层去除所述功函调整层之后，通过将所述第一栅极介电层和所述第二栅极介电层暴露于所述蚀刻溶液，分别在所述第一栅极介电层和所述第二栅极介电层上形成第一自保护层和第二自保护层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于在衬底上制造器件结构的示例性工艺的流程图；
图2A、图2B和图2C1示出了根据一些实施例的处于图1的不同制造阶段的半导体器件结构的立体图；
图2C2至图2C4示出了根据一些实施例的处于图1的不同制造阶段的半导体器件结构的截面图；
图2D1至图2D3、图2E1至图2E3、图2F1至图2F3、图2G1至图2G3、图2H1至图2H3、图2I1至图2I3、图2J1至图2J3、图2K1至图2K3、图2L1至图2L3、图2M1至图2M3和图2N1至图2N3示出了根据一些实施例的处于图1的不同制造阶段的半导体器件结构的截面图；以及
图3A至图3B示出了根据一些实施例的图1中示出的金属图案化工艺期间的表面结构反应的不同实例。
图4A至图4B示出了图1的制造工艺之后的半导体器件的实例。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明通常涉及半导体器件，并且更具体地，涉及形成在半导体器件中的替换栅极。本发明提供了用于保护在替换栅极制造工艺中形成在栅极结构中的栅极介电层的保护层的方法和结构。在FinFET的上下文中描述了本文的一些实例。在其它实施方式中，根据一些实施例的替换栅极和工艺可以在垂直全环栅(VGAA)器件、水平全环栅(HGAA)器件或其它器件中实现。此外，实施例可以在任何先进技术节点中实现。
在用于形成晶体管的金属栅极的替换栅极工艺中，在衬底上方形成伪栅极堆叠件，作为用于之后形成在衬底上的实栅极堆叠件的预留位置。围绕伪栅极堆叠件形成间隔件结构。在形成邻近于间隔件结构的源极/漏极部件和层间电介质(ILD)之后，去除伪栅极堆叠件，留下由间隔件结构和ILD围绕的开口。然后，在由间隔件结构和ILD限定的开口中形成金属栅极。
金属栅极结构包括诸如高k介电层的栅极介电层、可选阻挡层、层和栅极金属电极。可以使用多个沉积和图案化工艺形成该层，例如以微调晶体管的阈值电压(Vt)。在一些实施例中，该层可以针对不同类型的晶体管(诸如p型FinFET或n型FinFET)利用不同的材料，以根据需要增强器件电性能。在图案化工艺期间，可选地使用阻挡层保护栅极介电层。然而，栅极介电层和可选的阻挡层可能由于一些清洗和/或蚀刻工艺而被不经意地蚀刻。因此，栅极介电层和可选的阻挡层可能失去其在金属栅极结构中效用和功能。本发明的实施例可以解决这种问题。
图1示出了实施为形成半导体器件结构的工艺100的示例性流程图，半导体器件结构诸如图2A至图2N3中示出的器件结构201。图2A至图2C1是立体图，并且图2C2至图2N3是根据一些实施例的对应于工艺100的各个阶段的衬底的部分的示意性截面图。应该注意，工艺100可以用于形成任何合适的结构，包括图2A至图2N3中示出的半导体器件结构201或未在本文呈现的其它半导体结构。
工艺100开始于操作102，操作102提供具有形成在多个鳍结构202(形成在衬底200上)上方的伪栅极的衬底200，如图2A所示。
衬底200可以是或包括块状半导体衬底、绝缘体上半导体(SOI)衬底或其它衬底。衬底200的半导体材料可以包括或可以是选自硅(例如，如Si<100>或Si<111>的晶体硅)、硅锗、锗、砷化镓或其它半导体材料的至少一种的材料。半导体材料可以是掺杂的或未掺杂的，诸如掺杂有p型或n型掺杂剂。在SOI结构用于衬底200的一些实施例中，衬底200可以包括设置在绝缘层上的半导体材料，绝缘层可以是设置在半导体衬底中的掩埋绝缘体，或可以是玻璃或蓝宝石衬底。在本文示出的实施例中，衬底200是含硅材料，例如晶体硅衬底。此外，衬底200不限于任何特定的尺寸、形状或材料。衬底200可以是具有200mm直径、300mm直径或其它直径(诸如450mm)等的圆化/圆形衬底。衬底200也可以是任何多边形、正方形、矩形、弯曲或其它非圆形工件，诸如根据需要的多边形衬底。
每个鳍结构202提供形成一个或多个器件的有源区域。使用包括掩模、光刻和/或蚀刻工艺的合适工艺制造鳍结构202。在实例中，掩模层形成为覆盖衬底200。光刻工艺包括形成覆盖掩模层的光刻胶层(抗蚀剂)，将光刻胶层曝光成图案，实施曝光后烘烤工艺以及显影光刻胶层以图案化光刻胶层。使用合适的蚀刻工艺将光刻胶层的图案转移至掩模层以形成掩模元件。然后掩模元件可以用于保护衬底200的区域，同时蚀刻工艺在衬底中形成凹槽214，留下延伸的鳍，诸如鳍结构202。可以使用反应离子蚀刻(RIE)和/或其它合适的工艺蚀刻凹槽214。可以利用在衬底上形成鳍结构的许多其它方法的实施例。
在实施例中，鳍结构202的宽度约10纳米(nm)并且高度在从约10nm至60nm的范围内，诸如约50nm高。然而，应该理解，其它尺寸可以用于鳍结构202。在一个实例中，鳍结构202包括硅材料或诸如锗的另一元素半导体或包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体。鳍结构202也可以是包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或它们的组合的合金半导体。此外，鳍结构202可以根据需要使用n型和/或p型掺杂剂掺杂。
如描述的，在实例中，可以蚀刻掉部分衬底200，在衬底200中形成凹槽214来形成多个鳍结构202。然后，可以用凹进的或回蚀刻的隔离材料填充凹槽214以形成隔离结构216。用于隔离结构216和/或鳍结构202的其它制造技术是可能的。隔离结构216可以隔离衬底200的一些区域，例如，鳍结构202中的有源区。在实例中，隔离结构216可以是浅沟槽隔离(STI)结构和/或其它合适的隔离结构。STI结构可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料形成。STI结构可以包括例如具有一个或多个衬垫层的多层结构。
在鳍结构202上方形成伪栅极结构212。在图2A所示的实例中，伪栅极结构212包括栅极介电层206、伪栅极层208和硬掩模层210。应该注意，伪栅极结构212还可以包括覆盖层和/或其它合适的层。可以通过合适的沉积技术形成伪栅极结构212中的各个层，并且通过合适的光刻和蚀刻技术图案化伪栅极结构212中的各个层。伪栅极结构212在鳍结构202的两侧或三侧接合鳍结构202。如此处描述的，术语“伪”是指将在之后的阶段去除并且将在替换栅极工艺中用另一结构(诸如高k电介质和金属栅极结构)替换的牺牲结构。替换栅极工艺是指在整个栅极制造工艺的之后的阶段制造栅极结构。栅极介电层206可以是介电氧化物层。例如，可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其它合适的方法来形成介电氧化物层。伪栅极层208可以是多晶硅层或其它合适的层。例如，可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)的合适的沉积工艺形成伪栅极层208。硬掩模层210可以是适用于图案化衬底上的伪栅极结构212以具有期望的部件/尺寸的任何材料。
在实施例中，伪栅极结构212的各个层首先沉积为毯式层。然后，通过包括光刻和蚀刻工艺的工艺图案化毯式层，去除毯式层的部分并且保留隔离结构216和鳍结构202上方的剩余部分以形成伪栅极结构212。
在实例中，半导体器件结构201包括p型器件区域250a和n型器件区域250b。可以在p型器件区域250a中形成诸如p型FinFET的一个或多个p型器件，并且可以在n型器件区域250b中形成诸如n型FinFET的一个或多个n型器件。半导体器件结构201可以包括在诸如微处理器、存储器器件的IC和/或其它IC中。
在操作104中，如图2B所示，在伪栅极结构212的侧壁上形成间隔部件220，并且然后在间隔部件220上形成层间电介质218。间隔部件220包括与用于伪栅极结构212的材料不同的材料。在实施例中，间隔部件220包括介电材料，诸如氮化硅或氮氧化硅。在实例中，间隔部件220可以是单层或多层。在实施例中，在形成伪栅极结构212之后，可以通过在器件结构201上方共形地沉积间隔件材料来形成一个或多个间隔件层。随后，如图2B所示，实施各向异性蚀刻工艺以去除间隔件层的部分以形成间隔部件220。
在形成间隔部件220之后，可以实施一个或多个外延生长工艺以生长外延源极/漏极区域(未示出)。外延生长工艺可以用用于形成p型器件区域250a的p型掺杂剂或用于形成n型器件区域250b的n型掺杂剂原位掺杂外延源极/漏极区域。
随后，在衬底200上方和间隔部件220上形成ILD 218。在一些实施例中，器件区域201还可以包括位于ILD 218下面并且位于衬底200和间隔部件220之上的接触蚀刻停止层(未示出)。ILD 218可以包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃、掺杂的氧化硅(诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其它合适的介电材料的材料。可以通过PECVD工艺、HDP-CVD工艺或其它合适的沉积技术来沉积ILD 218。在实施例中，通过CVD工艺形成ILD 218以填充凹槽214并且填充相邻的伪栅极结构212之间。如图2B所示，在各个沉积工艺之后，实施化学机械平坦化(CMP)工艺以平坦化ILD 218，限定与衬底200上暴露的伪栅极结构212的顶面222基本共面的顶面224以用于随后的制造步骤。
在操作106中，如图2C1所示，从衬底200去除伪栅极结构212，以限定ILD 218中的开口230。在图2C1所示的实施例中，开口230暴露隔离结构216的表面232。图2C2示出了沿着线A-A’切割的截面图，包括限定在ILD 218中的开口230，以便于描述器件制造工艺。图2C3示出了沿着线B-B’切割的截面图，包括暴露n型器件区域250b中的鳍结构202和隔离结构216的开口230。图2C4示出了沿着线C-C’切割的截面图，包括暴露p型器件区域250a中的鳍结构202和隔离结构216的开口230。开口230允许在其中形成诸如金属栅极结构的栅极结构。
可以使用蚀刻工艺去除伪栅极结构212。蚀刻工艺可以包括合适的湿蚀刻、干(等离子体)蚀刻和/或其它工艺。例如，干蚀刻工艺可以使用含氯气体、含氟气体、其它蚀刻气体或它们的组合。湿蚀刻溶液可以包括NH4OH、HF(氢氟酸)或稀释的HF、去离子水、TMAH(四甲基氢氧化铵)、其它合适的湿蚀刻溶液或它们的组合。
在操作108中，如图2D1至图2D3所示，分别在由p型器件区域250a和n型器件区域250b中的间隔部件220限定的开口230中依次形成界面层240、栅极介电层242、243和第一功函调整层244。类似地，图2D1示出了沿着线A-A’器切割的截面图，包括限定在ILD 218中的开口230，以便于描述器件制造工艺。图2D2示出了沿着线B-B’切割的截面图，包括暴露n型器件区域250b中的鳍结构202和隔离结构216的开口230。图2D3示出了沿着线C-C’切割的截面图，包括暴露p型器件区域250a中的鳍结构202和隔离结构216的开口230。
在实例中，界面层240可以包括诸如氧化硅层(SiO2)或氮氧化硅(SiON)等的介电材料。可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD和/或其它合适的电介质形成界面层240。虽然图2D1至图2D3所示的界面层240形成在鳍结构202与栅极介电层242、243之间，但是应该注意，界面层240可以形成为沿着开口230的侧壁并且与间隔部件220和栅极介电层242、243接触并且位于间隔部件220和栅极介电层242、243之间。
在图2D1至图2D3所示的该具体实例中，p型器件区域250a中的栅极介电层242可以由与n型器件区域250b中的栅极介电层243不同的材料制造。栅极介电层242、243可以包括高k介电常数材料，诸如氧化铪(HfO2)、Al2O3、氧化镧(LaO2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或其它合适的材料。可以通过ALD和/或其它合适的方法形成栅极介电层242、243。例如，可以在器件区域250a和250b中共形地沉积栅极介电层242，并且使用光刻、掩模和蚀刻，可以从n型器件区域250b去除栅极介电层242。然后，可以在器件区域250a和250b中共形地沉积栅极介电层243，并且使用光刻、掩模和蚀刻，可以从p型器件区域250a去除栅极介电层243。应该注意，当界面层240不存在时，栅极介电层242可以直接形成在衬底200上(例如，鳍结构202上)。
在一个实例中，位于p型器件区域250a中的如图2D3所示的栅极介电层242可以是含Ta材料，诸如TaN、TaON、TaO、HfN、ZrN等。位于n型器件区域250b中的如图2D2所示的栅极介电层243可以是含Si材料，诸如TaSiN、TiSiN、WSiN、HfSiN、ZrSiN等。应该注意，在不同位置(诸如，p型器件区域250a或n型器件区域250b)形成不同栅极介电层材料可以提供不同的材料特性，以根据需要实现不同的器件电性能。在一个具体实例中，栅极介电层242、243分别是TaN层和TiSiN层，反之亦然。
在形成栅极介电层242、243之后，在栅极介电层242、243上形成第一功函调整层244。第一功函调整层244形成为用于调整器件的功函数。第一功函调整层244可以是用于p型器件区域250a中的p型FinFET器件的p型功函材料或是用于n型器件区域250b中的n型FinFET器件的n型功函材料，可以具有范围介于4.8eV和5.2eV之间的功函数的p型功函材料的合适的实例包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的p型层材料或它们的组合，并且可以具有范围介于3.9eV和4.3eV之间的功函数的n型功函材料的合适的实例包括Ti、Ag、TaAl、TaAlC、HfAl、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的n型层材料或它们的组合。
功函值与第一功函调整层244的材料组分相关。选择第一功函调整层244的材料以调整其功函值，使得在将在相应的区域中形成的器件中实现期望的阈值电压(Vt)。第一功函调整层244可以提供均匀的阈值电压(Vt)。可以通过CVD、ALD和/或其它合适的工艺沉积第一功函调整层244。在此处示出的实例中，使用ALD工艺形成第一功函调整层244。
可以通过在ALD沉积工艺期间改变工艺参数(诸如循环次数、前体脉冲数量、脉冲频率、衬底温度、压力等)来改变和调整第一功函调整层244的厚度。在一个实例中，通过改变用于沉积第一功函调整层244的ALD工艺的沉积循环次数来调整第一功函调整层244的厚度。
在操作110中，如图2E1至图2E3所示，第一图案化掩模结构248设置在衬底200的器件结构201的n型器件区域250b上。第一图案化掩模结构248覆盖器件结构201的n型器件区域250b的第一部分265，如图2E2所示，并且暴露器件结构201的p型器件区域250a和n型器件区域250b的第二部分267以用于进一步蚀刻，如图2E2至图2E3所示。该实例可以应用于期望在包括不同材料的栅极介电层的不同位置形成不同类型的层时的情况。因此，当从衬底去除层的部分时，可能暴露包括不同材料的不同栅极介电层，这可能在层去除工艺期间对蚀刻停止点引起挑战。因此，当在衬底的某些位置从衬底去除层时，实施适当地选择的蚀刻/图案化工艺以提供良好的界面控制。
第一图案化掩模结构248在蚀刻/图案化工艺期间用作掩模，以在蚀刻/图案化工艺期间保护由第一图案化掩模结构248覆盖的结构免受损坏。第一图案化掩模结构248可以包括设置在底部抗反射涂层(BARC)251上的光刻胶254。可以通过光刻工艺图案化光刻胶254以具有可以用作掩模的期望的尺寸以将部件转移至衬底200。BARC 251可以是涂覆至衬底200上的填充器件区域250a和250b中的开口230的有机材料，并且可以诸如在图案化光刻胶254之后通过蚀刻工艺去除BARC 251的部分，从而使得BARC 251保留在如图2E1和图2E2所示的n型器件区域250b中。虽然图2E1和图2E2所示的实例示出了在限定在n型器件区域250b上的开口230中形成的第一图案化掩模结构248，但是应该注意，根据需要可以在诸如p型器件区域250a的衬底的其它部分处形成第一图案化掩模结构248。
在操作112中，如图2F1至图2F3所示，实施蚀刻工艺以从由第一图案化掩模结构248限定的衬底200的开口230去除p型器件区域250a和n型器件区域250b的第二部分267中的第一功函调整层244。蚀刻工艺可以是通过用蚀刻溶液浸渍或浸泡衬底200实施的湿蚀刻工艺。在另一实例中，利用诸如蒸气或等离子体工艺的干工艺去除p型器件区域250a中和n型器件区域250b的一些位置的第一功函调整层244。在又另一实例中，利用湿和干工艺的组合从期望的位置去除第一功函调整层244。在具体实例中，在操作112中，从开口230去除第一功函调整层244是通过将衬底浸入、浸渍或浸泡在湿槽中的蚀刻溶液中实施的湿工艺。蚀刻溶液可以是pH值在预定范围内的碱性、中性或酸性溶液。根据要从衬底200去除的第一功函调整层244的材料类型选择蚀刻溶液。
在实施例中，蚀刻溶液包括水溶液(例如，H2O)中的磷酸(H3PO4或正磷酸)和硼酸(H3BO3)。为了进一步说明该实施例，蚀刻溶液可以包括磷酸和硼酸与诸如过氧化氢(H2O2)的其它组分的混合物。在实例中，蚀刻溶液的DI水中的磷酸的体积比率在从约1％至约10％的范围内。蚀刻溶液的DI水中的硼酸的体积比率小于10％，诸如在从约1％至约5％的范围内。蚀刻溶液的DI水中的过氧化氢(H2O2)的体积比率小于20％，诸如在从约1％至约5％的范围内。可选地，可以将蚀刻溶液中的磷酸和硼酸之间的比率控制在约1:5至约5:1(体积)的范围内，诸如约2:1(体积)。在一个具体实例中，蚀刻溶液包括磷酸、硼酸和过氧化氢(H2O2)。
在实例中，蚀刻溶液是与第一功函调整层244的材料反应的酸性溶液。酸性溶液蚀刻第一功函调整层244，例如含金属材料。可以添加诸如氢氟酸(HF)、盐酸(HCl)和/或硫酸(H2SO4)的其它酸性蚀刻剂，以提供给定浓度的不同pH值。
在另一实例中，蚀刻溶液是与第一功函调整层244的材料反应的碱性溶液。碱性溶液蚀刻第一功函调整层244，例如含金属材料。可以添加诸如NH4OH的其它碱性蚀刻剂，以提供给定浓度的不同pH值。这些蚀刻剂可以用于保持期望水平的pH值和/或帮助溶解在蚀刻溶液中的化学化合物的解离。蚀刻溶液的pH值可以根据需要控制在约2至约12的范围内。在实例中，蚀刻工艺可以维持在约20至约80摄氏度的范围内的温度。
在操作114中，如图2G1至图2G3所示，在去除p型器件区域250a中的第一功函调整层244和n型器件区域250b的第二部分267之后，当蚀刻溶液遇到栅极介电层242、243的表面时，在栅极介电层242、243上形成自保护层257a、257b。由于磷酸和硼酸螯合，在栅极介电层242、243的表面255、256(包括底部和侧壁部分的表面)上形成自保护层257a、257b。特定地选择蚀刻溶液以与栅极介电层242、243的某些元素反应，以在对应的表面255、256上形成期望的自保护层257a、257b。来自磷酸的磷(P)元素倾向于与来自选择用于栅极介电层242的高介电常数材料的诸如Ta、Hf、Zr等的金属元素反应，在自保护层257a的第一区域236(例如，蚀刻溶液遇到栅极介电层242的表面255的区域)上形成金属磷酸盐，诸如含金属磷酸螯合物或含金属络合剂，以保护栅极介电层242的表面255免受进一步蚀刻。
同时，来自硼酸的硼(B)元素倾向于与来自选择用于栅极介电层243的高介电常数材料的诸如TaSiN、TiSiN、WSiN、HfSiN、ZrSiN等的硅元素反应，在自保护层257b的第二区域238(例如，蚀刻溶液遇到栅极介电层243的表面256的区域)上形成包含硅和/或硼的络合剂，诸如硅硼酸盐络合剂，以保护栅极介电层243的表面256免受进一步蚀刻。
自保护层257b、257a包括硅硼酸盐络合剂和金属磷酸盐，诸如含金属磷酸螯合物或含金属络合剂，以保护栅极介电层243、242的表面256、255免受进一步蚀刻，这取决于自保护层257b、257a从哪里形成。当栅极介电层242、243的表面255、256暴露时，嵌入在栅极介电层242、243内的金属和硅元素也同时暴露，从而触发嵌入在栅极介电层242、243内的金属和硅元素与蚀刻溶液之间的化学反应。来自蚀刻溶液的磷酸的磷元素和硼酸的硼元素分别与栅极介电层242、243反应，以主要在自保护层257a的第一区域236上形成金属磷酸盐并且主要在自保护层257b的第二区域238上形成硅硼酸盐络合剂。来自金属磷酸盐的一些金属元素和来自硅硼酸盐络合剂的硅元素分别源自栅极介电层242、243的表面255、256，而一些金属和硅元素形成为自保护层257a、257b。因此，金属磷酸盐和硅硼酸盐络合剂桥接在栅极介电层242、243和自保护层257a、257b之间。虽然金属磷酸盐可能由于源自栅极介电层242的表面255的金属元素而主要形成在自保护层257a的第一区域236中，但是应该注意，可以在整个自保护层257a发现和检测到金属磷酸盐，如果存在的话。相比之下，虽然硅硼酸盐络合剂由于源自栅极介电层243的表面256的硅元素而主要形成在自保护层257b的第二区域238中，但是应该注意，可以在整个自保护层257b发现和检测到硅硼酸盐络合剂，如果存在的话。
在一个实例中，栅极介电层243包括硅元素，诸如TaSiN、TiSiN、WSiN、HfSiN、ZrSiN和含硅电介质。如图3A所示，Si元素与来自蚀刻溶液的硼酸反应以形成Si-B硅硼酸盐络合剂。
类似地，栅极介电层242包括Ta元素，诸如TaN、TaON、TaO等。如图3B所示，磷酸盐头部基团可以配位至栅极介电层242的含Ta元素的表面，形成单配位基和双配位基复合物以保护栅极介电层242。在栅极介电层242的高介电常数材料中形成的磷酸盐金属连接在界面处提供了良好的接合，将自保护层257a连接至栅极介电层242。应当认为，磷酸盐金属连接也可以由Zr或Hf形成，使得包括这些金属元素(诸如HfN、ZrN和HfO2)的高k材料也可以用于在界面处形成自保护层257a。
如图2G1至图2G3所示，由于栅极介电层242、243与来自蚀刻溶液的组分结合，当栅极介电层242、243的表面255、256(包括底部和侧壁部分的表面)暴露时，在栅极介电层242、243上形成自保护层257a、257b。进而，自保护层257a、257b的形成导致开口230中的第一功函调整层244的蚀刻自动停止在栅极介电层242、243处。因为来自自保护层257a、257b的金属和硅元素分别源自栅极介电层242、243的硅和金属元素，因此栅极介电层242、243和自保护层257a、257b具有在其中形成的共同金属和/或硅元素。共同的硅元素来自选择用于制造栅极介电层243的任何合适的含硅材料。共同的金属元素可以是Ta、Ti、Hf、Zr或它们的组合，或选择用于制造栅极介电层242的金属介电材料的任何合适的材料。
在形成自保护层257a、257b之后，可以从蚀刻溶液中去除衬底200。可以实施清洗工艺以从开口230去除蚀刻残留物。例如，清洗工艺可以使用含DI水、碳化DI水的溶液，诸如具有二氧化碳的DI水或具有NH4OH的DI水。可以在从约20至约80摄氏度的范围内的温度下实施清洗工艺。此外，也可以实施干燥工艺以干燥衬底200的表面。例如，干燥工艺可以包括在存在氮气流的情况下旋转干燥衬底200。例如，干燥工艺可以包括异丙醇(IPA)干燥工艺。
在一个实例中，自保护层257a、257b具有在从
Figure GDA0002583679800000131
至
Figure GDA0002583679800000132
的范围内的厚度。
在操作116中，如图2H1至图2H3所示，在p型器件区域250a和n型器件区域250b的第二部分267中形成自保护层257a、257b之后，去除第一图案化掩模结构248。在去除第一图案化掩模结构248之后，暴露n型器件区域250b的第一部分265中的第一功函调整层244以及形成在p型器件区域250a和n型器件区域250b的第二部分267中的自保护层257a、257b。
在操作118中，如图2I1至图2I3所示，在去除第一图案化掩模结构248之后，在自保护层257a、257b和第一功函调整层244上共形地形成第二功函调整层266。选择的用于制造第二功函调整层266的材料(将在多重图案化工艺之后保留在p型器件区域250a和n型器件区域250b的第二部分267中)可以与存在于衬底200的n型器件区域250b的第一部分265上的第一功函调整层244不同。
虽然此处描述的实例提供了在n型器件区域250b中形成不同类型的层，但是应该注意，可以在p型器件区域250a内，或在n型器件区域250b和p型器件区域250a之间或半导体器件结构201中的任何合适的位置形成不同类型的层。
如以上讨论的，功函值与第一功函调整层244和第二功函调整层266的材料组分相关。通过利用不同的材料在衬底200的不同的器件区域中(例如，在p型器件区域250a和n型器件区域250b内或之间)制造第一功函调整层244和第二功函调整层266，可以根据需要更灵活地调整和调节金属栅极结构的功函值。可以具有范围介于4.8eV和5.2eV之间的功函数的p型层材料的合适的实例包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其它合适的p型材料或它们的组合，并且可以具有范围介于3.9eV和4.3eV之间的功函数的n型材料的合适的实例包括Ti、Ag、TaAl、TaAlC、HfAl、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其它合适的n型材料或它们的组合。
可以通过CVD、ALD和/或其它合适的工艺沉积第二功函调整层266。
在此处示出的实施例中，使用ALD工艺形成第二功函调整层266。可以通过在ALD沉积工艺期间改变工艺参数(诸如循环次数、前体脉冲数量、脉冲频率、衬底温度、压力等)来改变和调整第二功函调整层266的厚度。在一个实例中，通过改变用于沉积第二功函调整层266的ALD工艺的沉积循环次数来调整第二功函调整层266的厚度。
在操作120中，如图2J1至图2J3所示，在形成第二功函调整层266之后，第二图案化掩模结构291设置在p型器件区域250a和n型器件区域250b的第二部分267上，并且填充衬底200的器件结构201的p型器件区域250a和n型器件区域250b的第二部分267中的开口230。第二图案化掩模结构291覆盖p型器件区域250a和n型器件区域250b的第二部分267，并且暴露器件结构201的n型器件区域250b的第一部分265以用于进一步蚀刻。第二图案化掩模结构291在蚀刻/图案化工艺期间用作掩模，以在蚀刻/图案化工艺期间保护由第二图案化掩模结构291覆盖的结构免受损坏。
类似于上述第一图案化掩模结构248，第二图案化掩模结构291可以包括设置在底部抗反射涂层(BARC)293上的光刻胶292。可以通过光刻工艺图案化光刻胶292以具有可以用作掩模的期望的尺寸以将部件转移至衬底200。BARC 293可以是涂覆至衬底200上的填充器件区域250a和250b中的开口230的有机材料，并且可以诸如在图案化光刻胶292之后通过蚀刻工艺去除BARC 293的部分，从而使得BARC 293保留在如图2J1至图2J3所示的p型器件区域250a中。应该注意，第一图案化掩模结构248与第二图案化掩模结构291在该工艺的不同阶段形成，以蚀刻衬底的不同区域的层，以针对不同器件需求和调整在衬底的不同区域处形成不同的膜结构。
在操作122中，如图2K1至图2K3所示，实施蚀刻工艺以从衬底200的n型器件区域250b的第一部分265去除第二功函调整层266。蚀刻工艺可以是通过用蚀刻溶液浸渍或浸泡衬底200实施的湿蚀刻工艺。在另一实例中，利用诸如蒸气或等离子体工艺的干工艺去除n型器件区域250b的第一部分265中的第二功函调整层266。在又另一实例中，利用湿和干工艺的组合以根据需要去除n型器件区域250b中的第二功函调整层266。在具体实例中，在操作112中，去除第二功函调整层266是通过将衬底浸入、浸渍或浸泡在湿槽中的蚀刻溶液中实施的湿工艺。蚀刻溶液可以是pH值在预定范围内的碱性、中性或酸性溶液。根据要从衬底200去除的第二功函调整层266的材料类型选择蚀刻溶液。
在操作124中，如图2L1至图2L3所示，在去除第二功函调整层266之后，然后从器件结构201的p型器件区域250a和n型器件区域250b的第二部分267去除第二图案化掩模结构291。在去除第二图案化掩模结构291之后，暴露p型器件区域250a以及n型器件区域250b的第二部分267中的第二功函调整层266，同时保持形成在n型器件区域250b的第一部分265中的第一功函调整层244。
因此，形成在p型器件区域250a中的膜结构(例如，栅极介电层242、自保护层257a和第二功函调整层266)被配置为与形成在衬底200的n型器件区域250b的不同位置中的膜结构(例如，栅极介电层243、自保护层257b和第二功函调整层266或第一功函调整层244)不同。在一些情况下，根据需要可以利用第三层。通过利用不同的膜结构，针对器件结构201的不同区域(例如，p型器件区域250a或n型器件区域250b的不同位置，反之亦然)中的不同结构的不同材料，可以灵活和有效地调整和增强形成在器件结构201中的金属栅极结构的功函值或其它相关的电性能。
此外，通过在栅极介电层242、243与第一功函调整层244和第二功函调整层266(或甚至根据需要的第三层)之间的界面处形成自保护层257a、257b，可以获得和实现良好的界面控制以及电性能的增强和调整。
在操作126中，如图2M1和图2M3所示，在从衬底200去除第二图案化掩模结构291之后，将栅电极金属276填充在限定在ILD 218中的开口230中以完成金属栅极结构280。栅电极金属276也可以称为由CVD、PVD、镀和/或其它合适的工艺形成的金属填充层。栅电极金属276可以包括Al、W或Cu和/或其它合适的材料。在一个实例中，在形成栅电极金属276之前，可以在衬底上形成衬垫层(未示出)，诸如TiN、TaN、TiON、TaON等。
在操作128中，如图2N1至图2N3所示，可以实施CMP工艺以从金属栅极结构280去除过量的材料，以平坦化器件结构201的顶面。
图4A至图4B示出了可以形成在p型器件区域250a和n型器件区域250b中的膜结构的又另一实施例。除了界面层240、栅极介电层242、243、自保护层257a、257b、功函调整层266以及栅电极金属276之外，可以在膜结构中使用或替换额外或不同的层。例如，在图4A所示的用于p型器件区域250a中的膜结构的实例中，在自保护层257a上形成覆盖层302，并且随后在覆盖层上形成阻挡层304。在形成阻挡层304之后，如以上讨论的，可以在阻挡层304上形成第二功函调整层266。在形成栅电极金属276之前，可以在第二功函调整层266上形成粘合层306。阻挡层304和/或覆盖层302可以包括钽和/或钛的氮化物、硅氮化物、碳氮化物和/或铝氮化物；钨的氮化物、碳氮化物和/或碳化物等；或它们的组合。此处利用的第二功函调整层266是含Ti、Al、W的合金。粘合层306可以是可选的并且可以由类似于覆盖层302的材料制造。
在一个具体实例中，覆盖层302是TiN层并且阻挡层是TaN层。此处利用的第二功函调整层266是AlTiN或TiN。可选的粘合层306可以是TiN层。
在图4B所示的用于n型器件区域250b中的膜结构的另一实例中，类似地，在自保护层257b上形成覆盖层302和阻挡层304。在图4B所示的结构中，可以在阻挡层304上形成与第一功函调整层244和第二功函调整层266不同的第三功函调整层282。随后，可以在第三功函调整层282上形成粘合层306，随后是栅电极金属276。
在一个具体实例中，覆盖层302是TiN层并且阻挡层是TaN层。此处利用的第二功函调整层266是AlTiN或TiN。
虽然不旨在限制，但是本发明的一个或多个实施例可以对半导体器件及其形成提供许多益处。例如，本发明的实施例提供了用于在替换栅极工艺中图案化层的方法。根据本发明，可以利用包括磷酸(或正磷酸)和硼酸的蚀刻溶液以及蚀刻溶液中的过氧化氢来图案化层，其中，栅极介电材料的不同类型的材料设置在该层下面。当从衬底去除该层并且一旦暴露下面的栅极介电层时，可以利用不同材料在栅极介电层上方同时形成自保护层以终止图案化工艺。因此，自保护层可以保持其阻挡和桥接能力，以在器件的不同位置处形成具有不同变化的膜结构，以增强电性能。利用包括磷酸和硼酸的蚀刻剂来蚀刻不同位置处包括不同材料的栅极介电层的图案化工艺可以在任何现有湿蚀刻工具中实施。
在实施例中，半导体器件包括位于衬底上的第一栅极结构和第二栅极结构；其中，第一栅极结构包括具有第一材料的第一栅极介电层，并且第二栅极结构包括具有第二材料的第二栅极介电层，第一材料与第二材料不同，其中，第一栅极结构和第二栅极结构还包括分别设置在第一栅极介电层和第二栅极介电层上的第一自保护层和第二自保护层，其中，第一自保护层包括金属磷酸盐，并且第二自保护层包括含硼络合剂，以及位于第一栅极结构中的第一自保护层上的第一功函调整层。在实施例中，第二栅极结构还包括位于第二栅极结构中的第二自保护层上的第二功函调整层。在实施例中，在第一功函调整层或第二功函调整层上形成栅电极金属。在实施例中，来自金属磷酸盐的金属元素嵌入在第一栅极介电层内。在实施例中，第一栅极介电层和第一自保护层共享共同的金属元素。在实施例中，共同的金属元素是Ta、Ti、Hf、Zr的至少一种或它们的组合。在实施例中，第二栅极介电层和第二自保护层共享共同的硅元素。在实施例中，来自第二栅极介电层与第二自保护层的硅元素在第二自保护层中形成含硼络合剂。在实施例中，含硼络合剂是硅硼酸盐络合剂。在实施例中，第一栅极介电层的第一材料是含Ta材料。在实施例中，第二栅极介电层的第二材料是含硅材料。在实施例中，第一栅介电层的第一材料是TaN、TaON、TaO、HfN、ZrN的至少一种或它们的组合，并且第二栅极介电层的第二材料是TaSiN、TiSiN、WSiN、HfSiN、ZrSiN的至少一种或它们的组合。在实施例中，第一自保护层和第二自保护层的厚度在从
Figure GDA0002583679800000181
至
Figure GDA0002583679800000182
的范围内。
在另一实施例中，半导体器件结构包括形成在衬底上的栅极结构，其中，栅极结构包括栅极介电层、位于栅极介电层上的自保护层，自保护层包括金属磷酸盐或含硼络合剂，其中，金属磷酸盐与栅极介电层具有共同的金属元素或含硼络合剂与栅极介电层具有共同的硅元素，以及形成在自保护层上的功函调整层。在实施例中，含硼络合剂包括硅硼酸盐络合剂。在实施例中，自保护层的厚度在从
Figure GDA0002583679800000183
至
Figure GDA0002583679800000184
的范围内。在实施例中，栅极介电层还包括包含金属元素的第一部分和包含硅元素的第二部分。
在又另一实施例中，用于形成半导体器件的方法包括使用蚀刻溶液图案化设置在衬底上的第一栅极介电层和第二栅极介电层上的功函调整层，其中，蚀刻溶液包括酸性溶液中的磷酸、硼酸和过氧化氢，其中，第一栅极介电层和第二栅极介电层每个均包括不同类型的材料，并且当从第一栅极介电层和第二栅极介电层去除功函调整层时，通过将第一栅极介电层和第二栅极介电层暴露于蚀刻溶液分别在第一栅极介电层和第二栅极介电层上形成第一自保护层和第二自保护层。在实施例中，第一自保护层包括金属磷酸盐，并且第二自保护层包括含硼络合剂，金属磷酸盐和含硼络合剂分别具有源自第一栅极介电层和第二栅极介电层的金属和硅元素。在实施例中，其中，蚀刻溶液中磷酸与硼酸的浓度比率(体积比)在从1:5至5:1的范围内。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
第一栅极结构和第二栅极结构，位于衬底上；其中，所述第一栅极结构包括具有第一材料的第一栅极介电层，并且所述第二栅极结构包括具有第二材料的第二栅极介电层，所述第一材料与所述第二材料不同，其中，所述第一栅极结构和所述第二栅极结构还包括：
第一自保护层和第二自保护层，分别设置在所述第一栅极介电层和所述第二栅极介电层上，其中，所述第一自保护层包括金属磷酸盐，并且所述第二自保护层包括含硼络合剂；以及
第一功函调整层，位于所述第一栅极结构中的所述第一自保护层上。
2.根据权利要求1所述的半导体器件，其中，所述第二栅极结构还包括：
第二功函调整层，位于所述第二栅极结构中的所述第二自保护层上。
3.根据权利要求2所述的半导体器件，还包括：
栅电极金属，位于所述第一功函调整层或所述第二功函调整层上。
4.根据权利要求1所述的半导体器件，其中，来自所述金属磷酸盐的金属元素嵌入在所述第一栅极介电层内。
5.根据权利要求1所述的半导体器件，其中，所述第一栅极介电层和所述第一自保护层共享共同的金属元素。
6.根据权利要求5所述的半导体器件，其中，所述共同的金属元素是Ta、Ti、Hf、Zr的至少一种。
7.根据权利要求1所述的半导体器件，其中，所述第二栅极介电层和所述第二自保护层共享共同的硅元素。
8.根据权利要求7所述的半导体器件，其中，来自所述第二栅极介电层的硅元素用于在所述第二自保护层中形成含硼络合剂。
9.根据权利要求8所述的半导体器件，其中，所述含硼络合剂是硅硼酸盐络合剂。
10.根据权利要求1所述的半导体器件，其中，所述第一栅极介电层的所述第一材料是含Ta材料。
11.根据权利要求1所述的半导体器件，其中，所述第二栅极介电层的所述第二材料是含硅材料。
12.根据权利要求1所述的半导体器件，其中，所述第一栅极介电层的所述第一材料是TaN、TaON、TaO、HfN、ZrN的至少一种或它们的组合，并且所述第二栅极介电层的所述第二材料是TaSiN、TiSiN、WSiN、HfSiN、ZrSiN的至少一种。
13.根据权利要求1所述的半导体器件，其中，所述第一自保护层和所述第二自保护层的厚度在从
Figure FDA0002909912860000021
至
Figure FDA0002909912860000022
的范围内。
14.一种半导体器件结构，包括：
栅极结构，形成在衬底上，其中，所述栅极结构包括：
栅极介电层，包括包含不同材料的第一栅极介电层和第二栅极介电层；
第一自保护层和第二自保护层，分别位于所述第一栅极介电层和所述第二栅极介电层上，所述第一自保护层包括金属磷酸盐，所述第二自保护层包括含硼络合剂，其中，所述金属磷酸盐与所述第一栅极介电层具有共同的金属元素，或所述含硼络合剂与所述第二栅极介电层具有共同的硅元素；以及
功函调整层，形成在所述第一自保护层和第二自保护层上。
15.根据权利要求14所述的半导体器件结构，其中，所述含硼络合剂包括硅硼酸盐络合剂。
16.根据权利要求15所述的半导体器件结构，其中，所述第一自保护层和第二自保护层的厚度在从
Figure FDA0002909912860000023
至
Figure FDA0002909912860000024
的范围内。
17.根据权利要求15所述的半导体器件结构，其中，所述第一栅极介电层包含所述金属元素，所述第二栅极介电层包含所述硅元素。
18.一种用于形成半导体器件的方法，包括：
使用蚀刻溶液图案化设置在衬底上的第一栅极介电层和第二栅极介电层上的功函调整层，其中，所述蚀刻溶液包括酸性溶液中的磷酸、硼酸和过氧化氢，其中，所述第一栅极介电层和所述第二栅极介电层每个均包括不同类型的材料；以及
当从所述第一栅极介电层和所述第二栅极介电层去除所述功函调整层之后，通过将所述第一栅极介电层和所述第二栅极介电层暴露于所述蚀刻溶液，分别在所述第一栅极介电层和所述第二栅极介电层上形成第一自保护层和第二自保护层，所述第一自保护层包括金属磷酸盐，并且所述第二自保护层包括含硼络合剂。
19.根据权利要求18所述的方法，其中，所述金属磷酸盐和所述含硼络合剂分别具有源自所述第一栅极介电层和所述第二栅极介电层的金属和硅元素。
20.根据权利要求18所述的方法，其中，所述蚀刻溶液中磷酸与硼酸的按体积计的浓度比率在从1:5至5:1的范围内。
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