CN106206436A - 用于金属栅极的方法和结构 - Google Patents

用于金属栅极的方法和结构 Download PDF

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CN106206436A
CN106206436A CN201510262736.0A CN201510262736A CN106206436A CN 106206436 A CN106206436 A CN 106206436A CN 201510262736 A CN201510262736 A CN 201510262736A CN 106206436 A CN106206436 A CN 106206436A
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coating
barrier layer
oxide skin
oxide
layer
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CN106206436B (zh
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黄如立
江志隆
戴铭家
叶明熙
陈昭成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了具有金属栅极的半导体器件及其形成方法。该方法包括：接收衬底、形成在衬底上方的伪栅极堆叠件和围绕伪栅极堆叠件的结构。该方法还包括去除伪栅极堆叠件，从而在结构中生成沟槽。该方法还包括在沟槽中形成栅极介电层；在栅极介电层上方形成阻挡层；在阻挡层上方形成氧化物层；以及在氧化物层上方形成功函金属层。在实施例中，该方法还包括通过含有磷酸的蚀刻剂去除功函金属层，其中，氧化物层防止蚀刻剂蚀刻阻挡层。本发明涉及用于金属栅极的方法和结构。

Description

用于金属栅极的方法和结构
技术领域
本发明涉及用于金属栅极的方法和结构。
背景技术
半导体集成电路(IC)产业经历了指数级发展。IC材料和设计中的技术进步已经产生了数代的IC，其中每代IC都具有比上一代IC更小和更复杂的电路。在IC发展过程中，功能密度(即，每一芯片面积上互连器件的数量)通常已经增加而几何尺寸(即，使用制造工艺可以制造的最小部件(或线))却已减小。通常这种按比例缩小工艺通过提高生产效率和降低相关成本而带来益处。这种按比例缩小也增大了加工和制造IC的复杂度。
例如，当制造诸如鳍式FET(FinFET)的场效应晶体管(FET)时，通过使用金属栅电极代替典型的多晶硅栅电极可以改进器件性能。一种形成金属栅极堆叠件的工艺被称为替代栅极或“后栅极”工艺，其中，“最后”制造最终的栅极堆叠件，这允许降低后续工艺的数量，包括在形成栅极之后实施的高温处理。然而，存在实施这种IC制造工艺的挑战，特别是在先进的工艺节点中具有缩放的IC部件和复杂的表面拓扑结构，诸如N16、N10等。一种挑战是金属图案化工艺可能会损坏在金属栅电极和栅极介电层之间提供的金属阻挡层。因此，金属材料可能侵入到栅极介电层内，从而导致器件缺陷。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种形成半导体器件的方法，包括：接收衬底、形成在所述衬底上方的伪栅极堆叠件和围绕所述伪栅极堆叠件的结构；去除所述伪栅极堆叠件，从而在所述结构中生成沟槽；在所述沟槽中形成栅极介电层；在所述栅极介电层上方形成阻挡层；在所述阻挡层上方形成氧化物层；以及在所述氧化物层上方形成第一功函金属层。
在上述方法中，形成所述氧化物层包括用氧处理所述阻挡层。
在上述方法中，形成所述氧化物层包括在所述阻挡层上方沉积所述氧化物层。
在上述方法中，所述阻挡层包括氮化钽并且所述氧化物层包括氧化钽。
在上述方法中，所述阻挡层包括氮化钛并且所述氧化物层包括氧化钛。
在上述方法中，所述阻挡层包括氮化铌并且所述氧化物层包括氧化铌。
在上述方法中，所述氧化物层包括氧化钽、氧化钛和氧化铌中的一种。
在上述方法中，还包括：通过含有磷酸的蚀刻剂去除所述第一功函金属层。
在上述方法中，去除所述第一功函金属层包括冲洗工艺和干燥工艺。
在上述方法中，还包括：在所述氧化物层上方形成第二功函金属层，其中，所述第二功函金属层与所述第一功函金属层不同。
根据本发发明的另一方面，还提供了一种形成半导体器件的方法，包括：接收衬底和位于所述衬底上方的第一栅极结构和第二栅极结构，其中，所述第一栅极结构和所述第二栅极结构包括第一沟槽和第二沟槽；在所述第一沟槽和所述第二沟槽中形成栅极介电层；在所述栅极介电层上方形成阻挡层；在所述阻挡层上方形成氧化物层，其中，所述氧化物层包括：氧化钽、氧化钛和氧化铌中的一种；以及在所述氧化物层上方形成第一功函金属层。
在上述方法中，形成所述氧化物层包括用氧处理所述阻挡层。
在上述方法中，还包括：在所述第二栅极结构上方形成掩蔽元件；以及使用含有磷酸的蚀刻剂蚀刻位于所述第一沟槽中的所述第一功函金属层。
在上述方法中，还包括：用含有去离子水(DIW)的溶液冲洗所述第一沟槽。
在上述方法中，还包括：在所述第一沟槽中的所述氧化物层上方形成第二功函金属层，其中，所述第二功函金属层与所述第一功函金属层不同。
根据本发明的又一方面，还提供了一种半导体器件，包括：衬底；以及第一栅极结构和第二栅极结构，位于所述衬底上方，其中：每个所述第一栅极结构和所述第二栅极结构均包括：栅极介电层，位于所述衬底上方，阻挡层，位于所述栅极介电层上方；和氧化物层，位于所述阻挡层上方。
在上述半导体器件中：所述第一栅极结构还包括位于所述第一栅极结构的所述氧化物层上方的n型功函金属层；以及所述第二栅极结构还包括位于所述第二栅极结构的所述氧化物层上方的p型功函金属层。
在上述半导体器件中，所述阻挡层包括氮化钽并且所述氧化物层包括氧化钽。
在上述半导体器件中，所述阻挡层包括氮化钛并且所述氧化物层包括氧化钛。
在上述半导体器件中，所述阻挡层包括氮化铌并且所述氧化物层包括氧化铌。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据本发明的各个方面的制造半导体器件的方法的流程图。
图2至图14是根据一些实施例的根据图1的方法形成半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
本发明通常涉及半导体器件，和更具体地，涉及具有FinFET的半导体器件。本发明的目的在于提供在FinFET“后栅极”工艺中有效地保护下面的栅极介电层的保护层的结构和用于该结构的方法。
在用于形成晶体管的金属栅极的后栅极工艺中，在衬底上方形成伪栅极堆叠件作为实际栅极堆叠件的预留位置(placeholder)。然后形成围绕伪栅极堆叠件的间隔部件。在邻近间隔部件形成源极/漏极部件之后，去除伪栅极堆叠件，从而留下由间隔件围绕的开口。最后，在开口中形成金属栅极。金属栅极包括诸如高k介电层的栅极介电层、阻挡层和功函金属层。例如，多重图案化工艺可以用于形成功函金属层，以微调晶体管的阈值电压(Vt)。阻挡层的目的是在图案化工艺期间保护栅极介电层。然而，诸如SC-1(标准清洁1)和SC-2(标准清洁2)的一些传统的蚀刻剂具有较差的蚀刻选择性。因此，阻挡层可能无意中被蚀刻，失去其作为保护层的有效性。本发明的实施例解决这样的问题。
现在参考图1，根据本发明的各方面示出了形成半导体器件的方法10的流程图。方法10仅仅是实例并且不旨在限制本发明超出权利要求中明确列举的。可以在方法10之前、期间和之后提供额外的操作，并对于方法的额外的实施例，可以替代、消除或重排描述的一些操作。在下文中结合图2至图14来描述方法10，图2至图14示出了处于各个制造阶段的半导体器件100的部分。器件100可以是在IC或其部分的加工期间制造的中间器件，其可以包括SRAM和/或其他逻辑电路；诸如电阻器、电容器、和电感器的无源部件；和诸如p型FET(PFET)、n型FET(NFET)、FinFET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高电压晶体管、高频晶体管、其他存储单元和它们的组合的有源部件。
在操作12中，方法10(图1)接收衬底102，衬底102中和/或上形成有各种结构。参考图2，器件100包括衬底102和在衬底102上方的隔离结构106。隔离结构106将器件100分成多个器件区。在所示出的实例中，存在n-FET器件区100a和p-FET器件区100b。在本实施例中，器件100包括FinFET，并且衬底102包括两个有源鳍104a和104b，两个有源鳍104a和104b穿过隔离结构106向上突出。两个鳍104a和104b分别位于器件区100a和100b中。在更进一步的实施例中，图2至图13是沿着相应的鳍104a/104b的鳍长度方向的器件100的示意性截面图，而图14是沿着相应的鳍104a/104b的鳍宽度方向的器件100的示意性截面图。在各个实施例中，器件区100a和100b可以是连续的或不连续的。本发明不局限于任何特定数量的器件或器件区，或任何特定的器件配置。
器件100还包括分别位于器件区100a和100b中的栅极结构101a和101b。栅极结构101a和101b的每一个均包括伪栅极堆叠件110和位于伪栅极堆叠件110的侧壁上的间隔部件112。栅极结构101a和101b的每一个均分别与有源鳍104a和104b的部分接合。该器件100还包括位于相应的有源鳍104a和104b中的源极/漏极区108a和108b，源极/漏极区108a和108b设置在相应的栅极结构101a和101b的相对两侧上。器件100还包括围绕栅极结构101a和101b的层间介电(ILD)层114。将在下文中进一步描述器件100的各种前述结构。
在本实施例中，衬底102是硅衬底。可选地，衬底102可以包括其他元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在又一些可选方式中，衬底102是诸如掩埋介电层的绝缘体上半导体(SOI)。
在本实施例中，鳍104a适合于形成n型FinFET，和鳍104b适合于形成p型FinFET。此配置仅用于说明目的，并不限制本发明。可以使用包括光刻和蚀刻工艺的合适的工艺制造鳍104a/104b。光刻工艺可以包括在衬底102上面形成光刻胶层(抗蚀剂)、将光刻胶曝光成一图案、实施曝光后烘烤工艺、和显影光刻胶以形成包括光刻胶的掩蔽元件。掩蔽元件然后用于在衬底102内蚀刻凹槽，从而留下位于衬底102上的鳍104a/104b(见图14)。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他合适的工艺。可选地，可以使用芯轴-间隔件双重图案化光刻形成鳍104a/104b。用于形成鳍104a/104b的方法的多个其他实施例可以是合适的。
隔离结构106可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料、和/或其他合适的绝缘材料形成。隔离结构106可以是浅沟槽隔离(STI)部件。在实施例中，通过在衬底102中蚀刻沟槽，例如，作为鳍104a/104b的形成工艺的一部分来形成隔离结构106。然后用隔离材料填充沟槽，之后进行化学机械抛光(CMP)工艺。诸如场氧化物、硅的局部氧化(LOCOS)、和/或其他适合的结构的其他隔离结构是可能的。隔离结构106可以包括多层结构，例如，具有一个或多个热氧化物衬垫层。
在本实施例中，伪栅极堆叠件110在鳍的两侧或三侧上与鳍104a/104b接合。其被称为“伪”是因为它将在后续步骤中被去除并且将在“后栅极”工艺中由诸如高-k金属栅极的“真”栅极堆叠件取代。伪栅极堆叠件110可以包括一个或多个材料层，诸如氧化物层、多晶硅层、硬掩模层、覆盖层、和其他合适的层。伪栅堆叠件110中的各层可以通过合适的沉积技术形成。例如，可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)、和/或其他合适的方法形成氧化物层。例如，可以通过诸如低压化学汽相沉积(LPCVD)和等离子增强CVD(PECVD)的合适的沉积工艺形成多晶硅层。在实施例中，首先沉积作为毯状层的伪栅极堆叠件110。然后，通过包括光刻工艺和蚀刻工艺的工艺图案化毯状层，从而去除部分的毯状层，和将剩余部分保持在隔离结构106和鳍104a/104b上方作为伪栅极堆叠件110。
在伪栅极堆叠件110的侧壁上形成间隔部件112。间隔部件112包括与伪栅极堆叠件110不同的材料。在实施例中，间隔部件112包括介电材料，诸如氮化硅或氮氧化硅。在实例中，间隔部件112包括多个层，诸如邻近伪栅极堆叠件110的密封层和邻近密封层的主要间隔件层。在实施例中，在已经形成伪栅极堆叠件110之后，通过在器件100上方毯式沉积间隔件材料形成一个或多个间隔件层。然后，实施各向异性蚀刻工艺以去除间隔件层的部分以形成如图2所示的间隔部件112。
源极/漏极区108a和108b可以包括源极/漏极部件，并且可以通过诸如蚀刻工艺以及之后的一个或多个外延工艺的各种技术形成。在一个实例中，实施一个或多个蚀刻工艺以去除鳍104a/104b的部分以在其中形成凹槽。可以实施清洗工艺，清洗工艺利用氢氟酸(HF)溶液或其他合适的溶液清洗凹槽。随后，实施一个或多个外延生长工艺以在凹槽中生长硅部件。外延生长工艺可以用p型掺杂剂或n型掺杂剂原位掺杂生长的硅以形成p型FinFET或n型FinFET。
在衬底102上方形成ILD层114。在实施例中，器件100还包括位于ILD层114下方的接触蚀刻停止层。ILD层114可以包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其他合适的介电材料。可以通过PECVD工艺或其他合适的沉积技术沉积ILD层114。在实施例中，ILD层是由可流动CVD(FCVD)工艺形成的。在一个实例中，FCVD工艺包括在衬底102上沉积可流动材料(诸如液体化合物)以填充沟槽，和通过诸如退火的合适的技术将可流动材料转化为固体材料。在各个沉积工艺之后，实施化学机械平坦化(CMP)工艺以平坦化介电层114的顶面并且暴露伪栅极堆叠件110的顶面以用于随后的制造步骤。
在操作14中，方法10(图1)去除伪栅极堆叠件110。参照图3，从而分别在栅极结构101a和101b中形成两个沟槽116a和116b，从而通过沟槽116a和116b暴露鳍104a和104b。沟槽116a/116b由以上论述的结构围绕，诸如间隔部件112和ILD层114。在实施例中，操作14包括一个或多个蚀刻工艺，一个或多个蚀刻工艺被选择性地调整为去除伪栅极堆叠件110(图2)而基本上保留间隔部件112和ILD层114。蚀刻工艺可以包括合适的湿蚀刻、干(等离子体)蚀刻、和/或其他工艺。例如，干蚀刻工艺可以使用含氯气体、含氟气体、其他蚀刻气体或它们的组合。湿蚀刻溶液可以包括NH4OH、HF(氢氟酸)或稀释的HF、去离子水、TMAH(四甲基氢氧化铵)、其他合适的湿蚀刻溶液，或它们的组合。
在操作16中，方法10(图1)在沟槽116a/116b中形成栅极介电层122。参考图4，在本实施例中，方法10还在栅极介电层122下面形成界面层120。例如，界面层120可以包括介电材料，诸如氧化硅层(SiO2)或氮氧化硅(SiON)，并可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD、和/或其他合适的电介质形成。在本实施例中，栅极介电层122包括高k介电材料，诸如氧化铪(HfO2)、Al2O3、镧系元素氧化物、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或其他合适的材料。可以通过ALD和/或其他合适的方法形成栅极介电层122。
在操作18中，方法10(图1)在沟槽116a/116b中形成阻挡层124。参考图5，阻挡层124也被称为金属势垒层或金属阻挡层。阻挡层124形成在栅极介电层122上方，并且旨在保护栅极介电层122在后续步骤中不会引入金属杂质。例如，在本实施例中，栅极结构101a/101b将形成为包括一个或多个功函金属层。在没有阻挡层124的情况下，来自那些功函金属层的金属材料将扩散至栅极介电层122内，从而造成制造缺陷。在各个实施例中，阻挡层124包括金属元素。在本实施例中，阻挡层124包括氮化钽。在另一实施例中，阻挡层124包括氮化钛。在又一实施例中，阻挡层124包括氮化铌。其他各种材料是适合的。在实施例中，阻挡层124是通过ALD、PVD、CVD或其他合适的方法形成的。在本实施例中，阻挡层124具有约至约的厚度。
已经观察到，在一些情况下，单独的阻挡层124可能不会对栅极介电层122提供足够的保护。在一种情况下，在沟槽116a/116b中实施多个金属图案化工艺以在阻挡层124上方形成功函金属层。作为实例，这可以用于微调FinFET的阈值电压(Vt)。在另一情况下，当在器件区100b中形成p-FET时，将p型功函金属同时沉积到沟槽116a和116b内。随后将沟槽116a中的p型功函金属替换为n型功函金属以在器件区100a中形成n-FET。在上述两种情况下，在金属图案化/去除工艺期间，可能不期望地蚀刻阻挡层124，部分由于用于图案化/去除金属层的蚀刻剂的较差的蚀刻选择性。当阻挡层124被蚀刻和被损害时，金属材料将会污染栅极介电层122，导致器件缺陷。本发明提供了增强对栅极介电层122的保护的结构和方法。
在操作20中，方法10(图1)在阻挡层124上方形成氧化物层126。参考图6，在沟槽116a/116b中形成氧化物层126，从而覆盖阻挡层124。氧化物层126所带来的好处将在后续步骤解释。氧化物层126可以通过各种工艺形成。
在实施例中，通过用氧气流(flow of oxygen)处理阻挡层124来形成氧化物层126。更进一步的实施例中，阻挡层124和氧化物层126包含共同的金属元素。在实施例中，阻挡层124包括氮化钽而氧化物层126包括氧化钽。在另一实施例中，阻挡层124包括氮化钛而氧化物层126包括氧化钛。在又一实施例中，阻挡层124包括氮化铌而氧化物层126包括氧化铌。在实施例中，以干蚀刻工具实施阻挡层124的氧处理。可选地，以干灰化工具实施阻挡层124的氧处理。在实施例中，氧处理的实施条件为：在约1.5毫托的压力下、约30摄氏度至约60摄氏度的温度以及约1mL/min至约100mL/min的氧流量(诸如约30mL/min)并且持续约5秒至约30秒。氧化物层126可以形成为具有约至约的厚度。然而，其他厚度也可能是合适的。
在另一实施例中，由一个或多个沉积工艺形成氧化物层126。在更进一步的实施例中，阻挡层124和氧化物层126可以包含相同的或不同的金属元素。例如，在约1托至约100托的压力、约250摄氏度至约400摄氏度的温度以及将四乙氧基钽二甲基乙醇胺作为前体气体并且将氩气作为载气的条件下，可以在阻挡层124上方沉积氧化钽(例如，Ta2O5)层。例如，前体气体的流量可以设置为约20标准立方厘米每分钟(sccm)。在实施例中，可以类似地实施氧化钛或氧化铌的沉积。然而，也可以使用其他合适的沉积技术。
在各个实施例中，可以调整各个层120、122、124和126的厚度以分别用于pFET器件以及用于nFET器件。
在操作22中，方法10(图1)在氧化物层126上方形成功函金属层128。参考图7，在沟槽116a/116b中形成功函金属层128，从而覆盖氧化物层126。功函金属层128可以是p型或n型功函金属层。示例性p型功函金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p型功函材料、或它们的组合。示例性n型功函金属包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函材料或它们的组合。功函金属层128可以包括多个层，并且可以通过CVD、PVD、和/或其他合适的工艺沉积。在本实施例中，功函金属层128包括适合于在器件区100b中形成pFET的p型功函材料。例如，当氧化物层126包括氧化钽时，含钛材料可以用于功函金属层128。虽然功函金属层128不旨在用于器件区100a中的nFET，但是它仍然沉积到沟槽116a和116b内。一个考虑因素是，选择性地沉积功函金属层128可能需要器件100的部分被诸如光刻胶(或抗蚀剂)的有机材料覆盖，其可能会在沉积期间污染功函金属层。因此，将功函金属层128同时沉积至沟槽116a/116b内简化了工艺并且提高了膜纯度。
在操作24中，方法10(图1)从沟槽116a中去除功函金属层128。这涉及到多个步骤，这将结合图8至图11进行解释。
参考图8，方法10形成覆盖器件区100b的掩蔽元件130。在实施例中，掩蔽元件130包括通过光刻工艺图案化的光刻胶并且可以进一步包括位于光刻胶下面的层，诸如底部抗反射涂层(BARC)。光刻工艺可以包括在衬底102上面形成光刻胶层、曝光光刻胶成一图案、实施曝光后烘烤工艺、以及显影光刻胶以去除它的位于器件区100a上方的部分并且形成掩蔽元件130。
参考图9，方法10实施蚀刻工艺以从沟槽116a中去除功函金属层128。蚀刻工艺使用蚀刻剂132。在实施例中，该蚀刻剂132包括磷酸(或正磷酸)，诸如水溶液(例如，H2O)中的85％重量百分比(85wt.％)的H3PO4。在更进一步的实施例中，蚀刻剂132是磷酸与其他组分的混合物，其他组分诸如过氧化氢(H2O2)、硝酸(HNO3)、硫酸(H2SO4)、去离子水(DIW)、氢氧化铵(NH4OH)、臭氧(O3)、氢氟酸(HF)、盐酸(HCl)、其他酸性溶液和有机氧化剂、或它们的组合。在实施例中，磷酸在该混合物中的比例为约1:5至约1:50。
在各个实施例中，可以在约20摄氏度至约80摄氏度的温度下实施蚀刻工艺。氧化物层126防止蚀刻剂132蚀刻阻挡层124。在各个实施例中，一旦去除功函金属层128，由于磷酸螯合，自组装的单层便形成在氧化物层126的表面上。该单层防止磷酸穿透氧化物层126。在实施例中，氧化物层126包括氧化钽(例如，Ta2O5)。在更进一步的实施例中，单层可以包括紧密堆积的配位至氧化钽上的十八磷酸盐(ODP)分子，其中多于一个的磷酸盐头部基团可以配位至一个钽离子并且形成单配位基和双配位基复合物以保护氧化的层，如下面的化学式所示：
Marcus Textor等人在Langmuir 2000,16,3257-3271中发表的题目为“Structural Chemis try of Self-Assembled Monolayers ofOctadecylphosphoric Acid on Tantalum Oxide Surfaces”和Dorothee Brovelli等人在Langmuir 1999,15,4324-4327中发表的题目为“Highly Oriented,Self-Assembled Alkanephosphate Monolayers on Tantalum(V)OxideSurfaces”中讨论了这种单层的形成。
在另一个实施例中，氧化物层126包括氧化钛(例如，TiO2)或氧化铌(例如，Nb2O5)。当去除功函金属层128后，磷酸盐单层可以类似地形成在氧化物层126的表面上。S.Tosatti等人在Langmuir 2002,18,3537-3548中发表的题目为“Self-Assembled Monolayers of Dodecyl andHydroxy-dodecyl Phosphates on Both Smooth and Rough Titanium andTitanium Oxide Surfaces”和Flávio A.Pavan等人在J.Braz.Chem.Soc.,Vol.16,No.4,815-820(2005)中发表的题目为“Adsorption of Phosphoric Acidon Niobium Oxide Coated Cellulose Fiber:Preparation,Characterization andIon Exchange Property”讨论了这种磷酸盐单层的形成。
由于氧化物层126与蚀刻剂132的组分的键合，沟槽116a中的功函金属层128的蚀刻自动停止于氧化物层126。在实施例中，该方法10还包括冲洗工艺以从沟槽116a去除蚀刻残留物，诸如磷酸盐单层。例如，冲洗工艺可以使用含有DIW、碳化的DIW(诸如具有二氧化碳的DIW)或具有稀释的NH4OH的DIW的溶液。可以在约20摄氏度至约80摄氏度的温度下实施冲洗工艺。在实施例中，该方法10进一步包括干燥工艺以干燥氧化物层126的表面。例如，干燥工艺可以包括在氮气流的存在下旋转干燥器件100。例如，干燥工艺可以包括异丙醇(IPA)干燥工艺。如图10所示，已从沟槽116a去除功函金属层128，从而暴露位于沟槽116a中的氧化物层126的表面。之后，方法10使用诸如光刻胶剥离或灰化的工艺从器件区100b去除掩蔽元件130。在实施例中，可以在以上论述的冲洗工艺和干燥工艺之前实施掩蔽元件130的去除。
在操作24之后，如图11所示，功函金属层128从沟槽116a去除但是仍保留在沟槽116b中。参考图11，沟槽116a中的氧化物层126基本上保持完整，并且阻挡层124在功函金属图案化工艺期间未被蚀刻。有利地，氧化物层126和阻挡层124提供金属阻挡能力以确保栅极介电层122的纯度。
在操作26中，方法10(图1)在沟槽116a中形成功函金属层134。参考图12，在本实施例中，功函金属层134包括适合于在器件区100a中形成nFET的n型功函材料。例如，它可以由含铝材料形成。在一个实例中，功函金属层134的厚度为约至约如图12所示，功函金属层134形成在沟槽116a中而未形成在沟槽116b中。这可以通过类似于在上文中结合操作22和24论述的工艺的金属图案化工艺实现。例如，类似于操作22，功函金属层134可以首先沉积在沟槽116a和116b中，然后类似于操作24，从沟槽116b去除功函金属层134，从而保留位于沟槽116a中的功函金属层134。在各个实施例中，可以在功函金属层128之前或之后形成功函金属层134。在操作26之后，如图14所示，每个栅极结构101a、101b均形成为具有界面层120、栅极介电层122、阻挡层124、氧化物层126和相应的功函金属层134和128，图14是沿着相应的鳍104a/104b的鳍宽度方向截取的器件100的示意性截面图。
在操作28中，方法10(图1)实施进一步的操作以形成最终的器件。例如，方法10可以在沟槽116a/116b的剩余空间中形成填充层136(图13)。填充层136可以包括铝(Al)、钨(W)、钴(Co)、铜(Cu)、和/或其他合适的材料。填充层136可以通过CVD、PVD、镀和/或其他合适的工艺形成。可以实施CMP工艺以从栅极结构101a/101b去除多余的材料，从而平坦化器件100的顶面。下面可以实施另外的操作。例如，操作28可以形成电连接源极/漏极部件108a/108b和栅极结构101a/101b的接触件和通孔并且形成将FinFET连接至器件100的其他部分的金属互连件以形成完整的IC。
虽然不打算限制，本发明的一个或多个实施例提供了半导体器件及其形成方法的许多益处。例如，本发明的实施例提供了用于在“后栅极”工艺中图案化功函金属层的方法。根据本发明，在栅极介电层上方形成阻挡层并且在阻挡层上方形成氧化物层。氧化物层阻止在金属图案化工艺中使用的各种蚀刻剂到达阻挡层。结果，阻挡层保持其阻挡能力以保护栅极介电层免受功函金属层的污染。本发明的各个实施例可以很容易地集成到现有的用于16纳米和更小的工艺节点的FinFET制造流程内。例如，在各个实施例中，可以通过以现有的蚀刻或灰化工具实施的氧处理工艺或通过沉积方法形成氧化物层。例如，金属图案化工艺可以使用含磷酸的蚀刻剂并且可以以任何现有的湿蚀刻工具实施。
在一个示例性方面中，本发明涉及一种形成半导体器件的方法。该方法包括：接收衬底、形成在衬底上方的伪栅极堆叠件和围绕伪栅极堆叠件的结构。该方法还包括去除伪栅极堆叠件，从而在结构中生成沟槽。该方法还包括在沟槽中形成栅极介电层；在栅极介电层上方形成阻挡层；在阻挡层上方形成氧化物层；以及在氧化物层上方形成第一功函金属层。在实施例中，该方法还包括通过含有磷酸的蚀刻剂去除第一功函金属层和在氧化物层上方形成第二功函金属层，其中，第二功函金属层与第一功函金属层不同。
在另一个示例性方面中，本发明涉及一种形成半导体器件的方法。该方法包括接收衬底和位于衬底上方的第一栅极结构和第二栅极结构，其中，第一栅极结构和第二栅极结构包括第一沟槽和第二沟槽。该方法还包括在第一沟槽和第二沟槽中形成栅极介电层；在栅极介电层上方形成阻挡层；以及在阻挡层上方形成氧化物层，其中，氧化物层包括：氧化钽、氧化钛和氧化铌中的一种。该方法还包括在氧化物层上方形成第一功函金属层。
在另一个示例性方面中，本发明涉及一种半导体器件。该半导体器件包括：衬底；以及位于衬底上方的第一栅极结构和第二栅极结构。每个第一栅极结构和第二栅极结构均包括：位于衬底上方的栅极介电层、位于栅极介电层上方的阻挡层和位于阻挡层上方的氧化物层。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
接收衬底、形成在所述衬底上方的伪栅极堆叠件和围绕所述伪栅极堆叠件的结构；
去除所述伪栅极堆叠件，从而在所述结构中生成沟槽；
在所述沟槽中形成栅极介电层；
在所述栅极介电层上方形成阻挡层；
在所述阻挡层上方形成氧化物层；以及
在所述氧化物层上方形成第一功函金属层。
2.根据权利要求1所述的方法，其中，形成所述氧化物层包括用氧处理所述阻挡层。
3.根据权利要求1所述的方法，其中，形成所述氧化物层包括在所述阻挡层上方沉积所述氧化物层。
4.根据权利要求1所述的方法，其中，所述阻挡层包括氮化钽并且所述氧化物层包括氧化钽。
5.根据权利要求1所述的方法，其中，所述阻挡层包括氮化钛并且所述氧化物层包括氧化钛。
6.根据权利要求1所述的方法，其中，所述阻挡层包括氮化铌并且所述氧化物层包括氧化铌。
7.根据权利要求1所述的方法，其中，所述氧化物层包括氧化钽、氧化钛和氧化铌中的一种。
8.根据权利要求1所述的方法，还包括：
通过含有磷酸的蚀刻剂去除所述第一功函金属层。
9.一种形成半导体器件的方法，包括：
接收衬底和位于所述衬底上方的第一栅极结构和第二栅极结构，其中，所述第一栅极结构和所述第二栅极结构包括第一沟槽和第二沟槽；
在所述第一沟槽和所述第二沟槽中形成栅极介电层；
在所述栅极介电层上方形成阻挡层；
在所述阻挡层上方形成氧化物层，其中，所述氧化物层包括：氧化钽、氧化钛和氧化铌中的一种；以及
在所述氧化物层上方形成第一功函金属层。
10.一种半导体器件，包括：
衬底；以及
第一栅极结构和第二栅极结构，位于所述衬底上方，
其中：
每个所述第一栅极结构和所述第二栅极结构均包括：
栅极介电层，位于所述衬底上方，
阻挡层，位于所述栅极介电层上方；和
氧化物层，位于所述阻挡层上方。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216356A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 在不同材料的高k介电层上形成的自保护层
CN111106000A (zh) * 2018-10-26 2020-05-05 台湾积体电路制造股份有限公司 形成半导体器件的方法
US11114347B2 (en) 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160139814A (ko) * 2015-05-28 2016-12-07 삼성전자주식회사 반도체 소자 및 그 제조방법
US10049940B1 (en) 2017-08-25 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for metal gates with roughened barrier layer
US10269569B2 (en) * 2016-11-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacture
US10522650B2 (en) * 2016-11-29 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacture
CN108155235B (zh) * 2016-12-02 2020-12-25 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
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US10170317B1 (en) 2017-09-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layer
US10546925B2 (en) 2017-11-02 2020-01-28 International Business Machines Corporation Vertically stacked nFET and pFET with dual work function
US11043567B2 (en) * 2017-11-30 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10541317B2 (en) 2018-03-01 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a metal gate using monolayers
KR102481284B1 (ko) 2018-04-10 2022-12-27 삼성전자주식회사 반도체 장치의 제조 방법
US10529629B2 (en) * 2018-04-30 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming metal gates
US10504789B1 (en) * 2018-05-30 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Pre-deposition treatment for FET technology and devices formed thereby
US10644125B2 (en) 2018-06-14 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gates and manufacturing methods thereof
US11075113B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Metal capping layer and methods thereof
US11031500B2 (en) * 2018-07-31 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Gate resistance improvement and method thereof
US10923565B2 (en) 2018-09-27 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact air gap formation
US11257923B2 (en) * 2018-10-12 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Tuning threshold voltage in field-effect transistors
US10770563B2 (en) 2018-10-24 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and patterning method for multiple threshold voltages
US11107907B2 (en) * 2018-10-30 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
US11289578B2 (en) * 2019-04-30 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Selective etching to increase threshold voltage spread
CN112242299A (zh) * 2019-07-18 2021-01-19 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11417748B2 (en) * 2019-10-30 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of fabricating a semiconductor device
US11309190B2 (en) * 2020-01-17 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11527621B2 (en) * 2020-08-05 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Gate electrode deposition and structure formed thereby
US20220293471A1 (en) * 2021-03-10 2022-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Fin Field-Effect Transistor Device and Method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661957A (zh) * 2008-08-26 2010-03-03 台湾积体电路制造股份有限公司 具有掺杂导电金属氧化物作为栅电极的cmos器件结构和方法
US20110121399A1 (en) * 2009-11-20 2011-05-26 Park Hong-Bae Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same
CN102103994A (zh) * 2009-12-16 2011-06-22 台湾积体电路制造股份有限公司 高介电常数介电层和/或金属栅极元件的制造方法
US20120119204A1 (en) * 2010-11-17 2012-05-17 International Business Machines Corporation Replacement Gate Having Work Function at Valence Band Edge
CN103377899A (zh) * 2012-04-25 2013-10-30 中芯国际集成电路制造(上海)有限公司 金属栅极制造方法和cmos制造方法
CN103681672A (zh) * 2012-08-31 2014-03-26 三星电子株式会社 半导体器件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732346B2 (en) 2007-02-27 2010-06-08 United Mircoelectronics Corp. Wet cleaning process and method for fabricating semiconductor device using the same
US8415254B2 (en) 2008-11-20 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for removing dummy poly in a gate last process
US8048733B2 (en) 2009-10-09 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a gate structure
US8487378B2 (en) 2011-01-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Non-uniform channel junction-less transistor
US9337192B2 (en) 2011-09-24 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stack having TaAlCN layer
US20130075831A1 (en) 2011-09-24 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stack having tialn blocking/wetting layer
US8887106B2 (en) 2011-12-28 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
US8586436B2 (en) 2012-03-20 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US8826213B1 (en) 2013-03-11 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Parasitic capacitance extraction for FinFETs
US8943455B2 (en) 2013-03-12 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
US9461144B2 (en) 2014-06-13 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for semiconductor device fabrication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101661957A (zh) * 2008-08-26 2010-03-03 台湾积体电路制造股份有限公司 具有掺杂导电金属氧化物作为栅电极的cmos器件结构和方法
US20110121399A1 (en) * 2009-11-20 2011-05-26 Park Hong-Bae Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same
CN102103994A (zh) * 2009-12-16 2011-06-22 台湾积体电路制造股份有限公司 高介电常数介电层和/或金属栅极元件的制造方法
US20120119204A1 (en) * 2010-11-17 2012-05-17 International Business Machines Corporation Replacement Gate Having Work Function at Valence Band Edge
CN103377899A (zh) * 2012-04-25 2013-10-30 中芯国际集成电路制造(上海)有限公司 金属栅极制造方法和cmos制造方法
CN103681672A (zh) * 2012-08-31 2014-03-26 三星电子株式会社 半导体器件及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216356A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 在不同材料的高k介电层上形成的自保护层
CN109216356B (zh) * 2017-06-30 2021-04-20 台湾积体电路制造股份有限公司 半导体器件结构、半导体器件及其形成方法
US11114347B2 (en) 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
CN111106000A (zh) * 2018-10-26 2020-05-05 台湾积体电路制造股份有限公司 形成半导体器件的方法
CN111106000B (zh) * 2018-10-26 2022-10-04 台湾积体电路制造股份有限公司 形成半导体器件的方法
US11508582B2 (en) 2018-10-26 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cut metal gate processes

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