TWI528551B - 半導體元件結構及其形成方法 - Google Patents

半導體元件結構及其形成方法 Download PDF

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TWI528551B
TWI528551B TW103144712A TW103144712A TWI528551B TW I528551 B TWI528551 B TW I528551B TW 103144712 A TW103144712 A TW 103144712A TW 103144712 A TW103144712 A TW 103144712A TW I528551 B TWI528551 B TW I528551B
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forming
layer
gate stack
semiconductor substrate
source
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TW103144712A
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TW201532276A (zh
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張哲誠
陳臆仁
張永融
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台灣積體電路製造股份有限公司
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

半導體元件結構及其形成方法
本揭露書係有關於半導體元件結構及其製法，且特別是有關於具有閘極堆疊之半導體元件結構。
半導體積體電路(IC)工業已經歷快速成長。積體電路材料與設計上的技術演進已開創積體電路之世代。每一世代相較於前一世代，具有更小且更複雜之電路。
在積體電路之演變過程中，通常功能性密度(即，每晶片面積所具有之內連元件數)已隨著幾何尺寸(即，使用製程所能製作之最小元件尺寸(或線寬))之縮減而增加。此縮小化製程一般藉著增加製作效率及降低相關成本而獲益。
然而，這些演進已增加處理與製造積體電路之複雜度。由於特徵尺寸(feature size)持續縮減，製程亦持續變得更難以進行。因此，為了形成具有越來越小的可靠半導體元件，正面臨著挑戰。
本揭露書提供一種半導體元件結構的形成方法，包括：於一半導體基底上形成一閘極堆疊；於該閘極堆疊之一側壁上形成一密封結構；於該半導體基底、該密封結構、及該閘極堆疊上形成一虛置遮蔽層；於該虛置遮蔽層上進行一離子 佈植製程以於該導體基底中形成源極及汲極區；以及在形成該些源極及汲極區之後，移除該虛置遮蔽層。
本揭露書提供一種半導體元件結構的形成方法，包括：於一半導體基底上形成一第一閘極堆疊及一第二閘極堆疊；分別於該第一閘極堆疊及該第二閘極堆疊之側壁上形成密封結構；於該些密封結構上形成一虛置遮蔽層；相繼於該虛置遮蔽層上進行離子佈植製程以分別於該半導體基底中及於該第一閘極堆疊及該第二閘極堆疊之相對側相繼形成第一源極及汲極區及第二源極及汲極區；以及在形成該些第一源極及汲極區及該些第二源極及汲極區之後，移除該虛置遮蔽層。
本揭露書提供一種半導體元件結構，包括：一半導體基底；一閘極堆疊，於該半導體基底之上；一密封結構，於該閘極堆疊之一側壁上，其中該密封結構與該閘極堆疊間之一寬度比值為約0.05至約0.7；以及一蝕刻停止層，於該半導體基底、該閘極堆疊、及該密封結構之上，其中該蝕刻停止層直接接觸該密封結構。
10a、10b‧‧‧閘極堆疊
12N、12P‧‧‧井區
100‧‧‧半導體基底
102‧‧‧隔離結構
104‧‧‧閘極介電層
106a、106b‧‧‧閘極電極
108a、108b‧‧‧密封結構
110a、110b‧‧‧摻雜區
111‧‧‧凹陷
112‧‧‧源極/汲極應力源
112’‧‧‧源極及汲極區
116‧‧‧摻雜區
118a、118b‧‧‧開口
120a、120b‧‧‧金屬閘極電極
202‧‧‧抗反射介電層
204‧‧‧虛置遮蔽層
217‧‧‧蝕刻停止層
219‧‧‧絕緣層
304a、304b‧‧‧閘極介電層
P‧‧‧間距
W1、W2、W3‧‧‧寬度
第1A-1H圖顯示根據一些實施例之半導體元件結構的製程剖面圖。
第2圖顯示根據一些實施例之半導體元件結構的剖面圖。
第3圖顯示根據一些實施例之半導體元件結構的剖面圖。
以下將詳細說明本揭露書之許多實施例的製作與 使用方式。然應注意的是，這些實施例可以多種特定背景表現。所討論之特定實施例僅用作說明，並不限制本揭露書之範圍。
應明白的是，以下揭露提供許多不同的實施例或範例，用以實施本揭露書之不同特徵。以下的揭露內容是敘述構件及其排列方式的特定範例，以求簡化揭露書之說明。當然，這些僅為舉例，並非用以限定。再者，在以下敘述提及在第二製程前進行第一製程，可包括第二製程於第一製程之後立刻進行之實施例，且亦可包括附加製程於第一製程與第二製程之間進行的實施例。為了簡化與清楚化，許多構件可能被任意地繪製成不同的尺寸比例。再者，以下述及一第一構件位於一第二構件上或之上時，包括第一構件與第二構件直接接觸之實施例，且亦可包括附加構件形成於第一構件與第二構件之間的實施例，使得第一構件與第二構件可能不彼此直接接觸。
以下敘述了實施例之一些變化。在許多圖式及說明用之實施例中，相似標號用以標示相似元件。附加的製程可於方法之前、期間、及之後加入，且所述的一些製程可於方法的其中實施例中被置換或消去。
第1A-1H圖顯示根據一些實施例之半導體元件結構的製程剖面圖。如第1A圖所示，提供半導體基底100。在一些實施例中，半導體基底100為半導體晶圓(例如，矽晶圓)或半導體晶圓之一部分。在一些實施例中，半導體基底100包括元素半導體，其包括單晶、多晶、或非晶結構之矽或鍺。在一些其他實施例中，半導體基底100包括化合物半導體，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體(例如， SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP)、或前述之組合。在一些實施例中，半導體基底100包括多層半導體、絕緣層上覆半導體(SOI)(例如，絕緣層上覆矽或絕緣層上覆鍺)、或前述之組合。
在一些實施例中，於半導體基底100中形成隔離結構102以於半導體基底100中定義各種主動區。隔離結構102使相鄰之元件(例如，電晶體)彼此電性隔離。隔離結構102例如包括氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(FSG)、低介電常數材料、其他適合的材料、或前述之組合。隔離結構102可藉由使用隔離技術而形成，例如是局部矽氧化(LOCOS)、淺溝槽隔離(STI)或其相似製程。在一些實施例中，隔離結構102之形成包括藉著微影製程而將半導體基底100圖案化、於半導體基底100中蝕刻出溝槽(例如，藉著使用乾式蝕刻、濕式蝕刻、電漿蝕刻、或前述之組合)、於溝槽中填充介電材料(例如，藉著使用化學氣相沉積製程)。在一些實施例中，所填充之溝槽具有多層結構，例如是熱氧化襯層填充以氮化矽或氧化矽。
在一些實施例中，於半導體基底100中相繼形成P井區12P及N井區12N，如第1A圖所示。在一些實施例中，進行不同的離子佈植製程以分別形成P井區12P及N井區12N。藉著使用不同的佈植遮罩層，P井區12P及N井區12N相繼於不同的離子佈植製程中形成。
在一些實施例中，第一佈植遮罩層(未顯示)係用以覆蓋半導體基底100之第一部分。第一佈植遮罩層具有開口，其露出半導體基底100之另一部分。在一些實施例中，第一佈 植遮罩層為圖案化光阻層。在一些其他實施例中，第一佈植遮罩層為圖案化介電層，例如是氮化矽層。之後，於半導體基底100之露出部分上進行第一離子佈植製程以形成井區，例如是P井區12P。例如，將P型摻質佈植進入半導體基底100之露出部分以形成P井區12P。接著，移除第一佈植遮罩層。
之後，在一些實施例中，使用第二佈植遮罩層(未顯示)覆蓋P井區12P。第二佈植遮罩層具有開口，其露出半導體基底100先前被第一佈植遮罩層所覆蓋之部分。在一些實施例中，第二佈植遮罩層為圖案化光阻層。在一些其他實施例中，第二佈植遮罩層為圖案化介電層，例如是氮化矽層。之後，進行第二離子佈植製程以形成井區，例如是N井區12N。例如，將N型摻質佈植進入半導體基底100之露出部分以形成N井區12N。
之後，在一些實施例中，進行退火製程以導入所佈植之摻質。在一些其他實施例中，N井區12N形成於P井區12P之前。在一些其他實施例中，若半導體基底100為P型半導體基底，不形成P井區。在一些其他實施例中，若半導體基底100為N型半導體基底，不形成N井區。
如第1A圖所示，根據一些實施例，於半導體基底100上形成閘極堆疊。為了簡化圖式，僅繪出兩閘極堆疊10a及10b。半導體元件結構可包括較少的或更多的閘極堆疊。每一閘極堆疊10a及10b包括閘極介電層104及閘極電極，例如第1A圖所示之閘極電極106a及106b。在一些實施例中，閘極介電層104係由氧化矽、氮氧化矽、高介電常數材料(high-K材料)、或 前述之組合所製成。高介電常數材料可包括氧化鉿(HfO2)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、其他適合的高介電常數材料、或前述之組合。高介電常數材料可更包括金屬氧化物、金屬氮化物、金屬矽玻璃、過渡金屬-氧化物、過渡金屬-氮化物、過渡金屬-矽玻璃(transition metal-silicates)、金屬氮氧化物、金屬鋁酸鹽(metal aluminates)、鋯矽玻璃、鋯鋁酸鹽、氧化矽、氮化矽、氮氧化矽、氧化鋯、氧化鈦、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的材料、或前述之組合。
在一些實施例中，閘極介電層104係藉著適合的製程而沉積，例如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、遠距離電漿化學氣相沉積(RPCVD)、電漿輔助化學氣相沉積(PECVD)、金屬有機化學氣相沉積(MOCVD)、濺鍍、電鍍、其他可應用製程、或前述之組合。
之後，於閘極介電層104上沉積閘極電極層。在一些實施例中，閘極電極層係由多晶矽所製成，且例如藉由使用化學氣相沉積(CVD)製程或其他適合的製程而形成。
之後，例如藉著使用微影製程及蝕刻製程而將閘極介電層104及閘極電極層圖案化，因而形成出閘極堆疊，其包含閘極堆疊10a及10b。閘極電極層因而被圖案化成數個閘極電極，其包含閘極電極106a及106b，如第1A圖所示。
之後，如第1A圖所示，根據一些實施例，於閘極堆疊10a及10b之側壁上形成一或更多的密封結構，例如是密封結構108a及108b。密封結構108a及108b可用以在後續製程進行 時保護閘極堆疊10a及10b免於受損。在一些實施例中，密封結構108a及108b係由介電材料所製成。介電材料例如包括氮化矽、氧化矽、氮氧化矽、其他適合的材料、或前述之組合。在一些實施例中，藉著使用適合的製程(例如是化學氣相沉積(CVD)製程)而於閘極堆疊10a及10b及半導體基底100上沉積密封層。之後，進行蝕刻製程(例如，乾式蝕刻製程)以部分移除密封層。保留於閘極堆疊10a及10b之相對側壁上之密封層形成了密封結構108a及108b。
之後，如第1A圖所示，根據一些實施例，於半導體基底100中形成摻雜區110a及110b。進行不同的離子佈植製程以相繼形成摻雜區110a及110b。在一些實施例中，使用佈植遮罩層(未顯示)覆蓋N井區12N。之後，進行亦以閘極堆疊10a為佈植遮罩之佈植製程以形成摻雜區110a。在一些實施例中，將N型摻質佈植進入P井區12P中以形成摻雜區110a。相似地，摻雜區110b係藉著使用另一佈植製程而形成於N井區12N之中。亦可使用另一佈植遮罩層(未顯示)來輔助形成摻雜區110b。因此，P型摻質被佈植進入N井區12N中以形成摻雜區110b，而不會被佈植到P井區12P之中。
摻雜區110a及110b分別位於閘極堆疊10a及10b之相對策，且位於半導體基底100之中。在一些實施例中，摻雜區110a之一部分係接近閘極堆疊10a，且在密封結構108a下方。在一些實施例中，摻雜區110a係作為輕摻雜源極/汲極區(LDS/D region)。在一些實施例中，摻雜區110b之一部分係接近閘極堆疊10b，且在密封結構108b下方。在一些實施例中， 摻雜區110b係作為輕摻雜源極/汲極區(LDS/D region)。在一些實施例中，離子佈植製程係傾斜一角度進行，使得所形成之摻雜區110a及110b分別延伸至閘極堆疊10a及10b之下。
如第1B圖所示，根據一些實施例，移除一部分的半導體基底100以於半導體基底100中形成凹陷111。如第1B圖所示，凹陷111自半導體基底100之表面延伸進入N井區12N。如第1B圖所示，摻雜區110b被部分移除。在一些實施例中，摻雜區110b位於凹陷111之間。在一些實施例中，進行微影製程及蝕刻製程以形成凹陷111。本揭露書具有許多變化。在一些實施例中，凹陷111係於形成摻雜區110b之前形成。
如第1C圖所示，根據一些實施例，於凹陷111中磊晶成長或形成源極/汲極應力源112。根據一些實施例，源極/汲極應力源112包括SiGe或其他可應用材料。在一些實施例中，源極/汲極應力源112用以對閘極堆疊10b下的通道區提供應力，以利於增加載子移動率。在一些實施例中，源極/汲極應力源112在其成長或形成期間同時被摻雜。或者，在源極/汲極應力源112成長或形成之後，進行後續的佈植製程以摻雜源極/汲極應力源112。然而，在一些實施例中，未形成源極/汲極應力源112。未形成凹陷111。
如第1D圖所示，根據一些實施例，於半導體基底100、密封結構108a及108b、及閘極堆疊10a及10b之上沉積虛置遮蔽層204。在一些實施例中，虛置遮蔽層204用作暫時性的主要間隙壁(temporary main spacer)，其用於後續的佈植製程。
在一些實施例中，虛置遮蔽層204係由光阻材料所 製成。光阻材料可包括碳、氫、氧、其他適合材料、或前述之組合之混合物。在一些實施例中，虛置遮蔽層204包括光敏感高分子。光敏感高分子可包括甲基丙烯酸甲酯(PMMA)、丙烯酸樹脂(acrylic resin)、甲基丙烯酸甲酯樹脂(methacrylate resin)、混合樹脂(hybrid resin)、其他適合的光敏感高分子、或前述之組合。在一些實施例中，虛置遮蔽層204包括光酸產生劑(photo acid generator)，例如硫鹽(sulfonium salt)、重氮甲烷(diazomethane)、或其他適合的光酸產生劑。在一些實施例中，虛置遮蔽層204包括氫氧化十六三甲基銨(cetyltrimethyl ammonium hydroxide)。
在一些實施例中，虛置遮蔽層204係使用旋塗製程(spin-on process)、化學氣相沉積(CVD)製程、其他可應用製程、或前述之組合而沉積。可根據需求調整虛置遮蔽層204之厚度。在一些實施例中，虛置遮蔽層204之厚度為約5奈米至約20奈米。在一些其他實施例中，虛置遮蔽層204之厚度為約7奈米至約15奈米。
在一些實施例中，在沉積虛置遮蔽層204之前，先沉積抗反射介電(anti-reflection dielectric，ARD)層202。在一些實施例中，抗反射介電層202係由氮化矽、氮化鈦、其他可應用材料、或前述之組合所製成。在一些實施例中，抗反射介電層202之厚度為約10Å至約50Å。然而，在一些其他實施例中，不需要或沒有形成抗反射介電層202。
如第1E圖所示，根據一些實施例，進行佈植製程以於半導體基底100中形成摻雜區116。虛置遮蔽層204用作佈 植遮罩。因此，形成了摻雜區116(例如，源極/汲極區，S/D region)，其鄰接摻雜區110a(例如，輕摻雜源極/汲極區，LDS/D region)。在一些實施例中，佈植了N型摻質以形成摻雜區116。在一些實施例中，使用佈植遮罩層(未顯示)以確保N型摻質不被佈植進入源極/汲極應力源112。在形成摻雜區116之後，移除佈植遮罩。在一些實施例中，摻雜區116為重摻雜源極/汲極區(heavily-doped S/D region)。在於源極/汲極區上進形佈植製程之後，可進行退火製程(例如，快速熱製程，rapid thermal process(RTP))以修復源極/汲極區中矽的結晶結構，並活化源極/汲極區中之摻質。如第1E圖所示，在一些實施例中，摻雜區116不被密封結構108a所覆蓋。
在一些實施例中，進行另一佈植製程以對源極/汲極應力源112摻雜適合的摻質。在一些實施例中，將P型摻質佈植進入源極/汲極應力源112。因此，於閘極堆疊10b之相對側上形成源極及汲極區112’，如第1E圖所示。用以形成源極及汲極區112’之佈植製程可於形成摻雜區116之前或之後進行。相似地，可使用佈植遮罩層(未顯示)以確保摻質被佈植到適合的位置。
如第1F圖所示，根據一些實施例，移除虛置遮蔽層204及抗反射介電層202(若有形成)。在一些實施例中，虛置遮蔽層204被完全移除。在一些實施例中，虛置遮蔽層204係由光阻材料所製成。因此，虛置遮蔽層204可使用灰化製程(ashing process)或剝除製程(stripping process)而輕易地移除。在一些實施例中，虛置遮蔽層204用作暫時性的主要間隙壁，且可輕 易移除。在一些實施例中，在移除虛置遮蔽層204之後，不再有區域被虛置遮蔽層204(暫時性的主要間隙壁)所佔據。因此，增加了接觸落點區域(contact landing area)。在一些實施例中，不需為了形成主要間隙壁而形成介電層，並小心地蝕刻及調整輪廓。可顯著地減少製程時間與成本。根據一些實施例，在設計閘極堆疊之圖案時，不需定義形成主要間隙壁所需之區域。可設計更為密集的圖案。可減低閘極堆疊之間的間距(pitches between gate stacks)。
之後，如第1G圖所示，根據一些實施例，於半導體基底100、閘極堆疊10a及10b、及密封結構108a及108b上沉積蝕刻停止層217。在一些實施例中，蝕刻停止層217包括氮化矽層。在一些實施例中，蝕刻停止層217係順應性地沉積於半導體基底100之上。在一些實施例中，蝕刻停止層217係藉著使用適合的製程而形成，例如化學氣相沉積製程。在一些實施例中，蝕刻停止層217亦可作為應力源層(stressor layer)，其增加閘極堆疊下通道區中之載子移動率，因而增進所形成半導體元件之效能。
如第1G圖所示，根據一些實施例，蝕刻停止層217直接接觸密封結構108a及108b。在一些實施例中，在密封結構(108a或108b)與蝕刻停止層217之間沒有主要間隙壁或中間層。在一些實施例中，密封結構(108a或108b)的整個外表面(entire outer surface)直接接觸蝕刻停止層217。
之後，如第1G圖所示，根據一些實施例，於蝕刻停止層217上沉積絕緣層219。在一些實施例中，絕緣層219係 由適合的介電材料所製成。適合的介電材料可包括氧化矽、氮氧化矽、硼矽玻璃(borosilicate glass，BSG)、磷矽玻璃(phosphoric silicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)、氟化矽玻璃(fluorinated silicate glass，FSG)、低介電常數材料(low-k material)、多孔介電材料、其他可應用材料、或前述之組合。根據一些實施例，進行適合的製程以形成絕緣層219，例如化學氣相沉積製程、高密度電漿化學氣相沉積製程(HDPCVD)、旋塗製程、濺鍍製程、或前述之組合。
在一些實施例中，進行平坦化製程以薄化絕緣層219。在平坦化製程之後，絕緣層219具有大抵平坦之表面，有利於後續的製程步驟。平坦化製程例如包括化學機械研磨(chemical mechanical polishing，CMP)製程。在一些實施例中，接著進行一或更多的金屬閘極置換製程而以適合的金屬材料置換閘極電極106a及/或106b。然而，本揭露書之實施例不限於此。在一些其他實施例中，不置換閘極電極106a及106b。在一些其他實施例中，閘極電極106a及106b之其中之一未被置換。
如第1G圖所示，根據一些實施例，在將絕緣層219平坦化之後，移除閘極電極106a及106b(其用作虛置閘極電極)以形成開口118a及118b。在一些實施例中，進行蝕刻製程以同時移除閘極電極106a及106b。在一些其他實施例中，閘極電極106a及106b係於不同的蝕刻製程中分別移除。
在一些實施例中，使用濕式蝕刻製程移除閘極電 極106a及106b。例如，可使用蝕刻溶液，其包含NH4OH溶液、稀釋氫氟酸(dilute HF)、其他適合的蝕刻溶液、或前述之組合。在一些實施例中，使用乾式蝕刻製程移除閘極電極106a及106b。蝕刻劑例如包括氟基及/或氯基蝕刻劑(fluorine and/or chlorine based etchants)。
如第1H圖所示，根據一些實施例，相繼於開口118a及118b中形成金屬閘極電極120a及120b。在一些實施例中，每一金屬閘極電極120a及120b包括功函數層(work function layer(s))及閘極電極層。閘極電極層用以於功函數層與後續所形成耦接至閘極電極層之接觸(contact)之間提供電性連接。在一些實施例中，閘極電極層由適合的金屬材料所製成。適合的金屬材料可包括鋁、鎢、金、鉑、鈷、其他適合的金屬材料、前述之合金、或前述之組合。
功函數層對電晶體提供所需之功函數以增進元件效能，包括增進臨界電壓(threshold voltage)。在形成NMOS電晶體的實施例中，功函數層可為N型金屬，其能夠提供適合於元件之功函數值(work function value)。功函數值例如是等於或小於約4.5eV。N型金屬可包括金屬、金屬碳化物、金屬氮化物、或前述之組合。例如，N型金屬包括鉭、氮化鉭、或前述之組合。在一些實施例中，金屬閘極電極120a包括N型金屬。
另一方面，在形成PMOS電晶體的實施例中，功函數層可為P型金屬，其能夠提供適合於元件之功函數值。功函數值例如是等於或大於約4.8eV。P型金屬可包括金屬、金屬碳化物、金屬氮化物、其他適合的材料、或前述之組合。例如， P型金屬包括鈦、氮化鈦、其他適合的材料、或前述之組合。在一些實施例中，金屬閘極電極120b包括N型金屬。
功函數層亦可由鉿、鋯、鈦、鉭、鋁、金屬碳化物(例如，碳化鉿、碳化鋯、碳化鈦、碳化鋁)、鋁化物(aluminides)、釕(ruthenium)、鈀(palladium)、鉑、鈷、鎳、導電金屬氧化物、或前述之組合所製成。
在一些實施例中，金屬閘極電極120a形成於金屬閘極電極120b之前。在一些實施例中，形成了遮罩層(未顯示)以覆蓋及/或填充開口118b，以確保金屬閘極電極120a形成在開口118a之中而不形成於開口118b之中。遮罩層亦可稱為阻擋層(blocking layer)。在一些實施例中，遮罩層係由多晶矽、非晶矽、氮化矽、氧化矽、旋塗玻璃(spin-on glass)、其他適合的材料、或前述之組合所製成。
在一些實施例中，於絕緣層219上沉積硬遮罩材料(hard mask material)以填充並滿出開口118a及118b。之後，進行平坦化製程以移除開口118a和118b外之硬遮罩材料。在一些實施例中，形成遮罩構件(rmask element)(未顯示)以覆蓋保留於開口118b中之硬遮罩材料，使得保留於開口118a中之硬遮罩材料露出。在一些實施例中，遮罩構件為圖案化光阻層。之後，根據一些實施例，藉著使用適合的蝕刻劑移除開口118a中之硬遮罩材料。接著，移除遮罩構件。因此，在一些實施例中，保留於開口118b中之硬遮罩材料形成了覆蓋及/或填充開口118b之遮罩層。在一些實施例中，遮罩層用以確保金屬閘極電極120a形成在開口118a之中而不形成於開口118b之中。
在一些實施例中，藉著使用適合的沉積製程將功函數層(例如，N型金屬)沉積在絕緣層219及開口118a的側壁與底部上。適合的沉積製程可包括物理氣相沉積製程、電鍍製程、化學氣相沉積製程、其他可應用的製程、或前述之組合。之後，藉著使用物理氣相沉積製程、電鍍製程、化學氣相沉積製程、或其相似製程於功函數層上沉積閘極電極層。接著，將閘極電極層及功函數層圖案化以移除在開口118a外的部分。在一些實施例中，進行平坦化製程(例如，化學機械研磨製程)以移除開口118a外之部分。因此，形成了金屬閘極電極120a。之後，移除覆蓋及/或填充開口118b之遮罩層。
之後，如第1H圖所示，根據一些實施例，於開口118b中形成金屬閘極電極120b。相繼形成功函數層(例如，P型金屬)及閘極電極層以填充開口118b，並將之圖案化以形成金屬閘極電極120b。然應了解的是，本揭露書之實施例不限於此。在一些其他實施例中，金屬閘極電極120b係形成於金屬閘極電極120a之前。
本揭露書之實施例具有許多變化。如前所述，閘極電極106a及106b可分別於不同的蝕刻製程中移除。在一些實施例中，於第一蝕刻製程中移除閘極電極106a，而閘極電極106b則以遮罩層(未顯示)覆蓋而保留。之後，於開口118a中形成金屬閘極電極120a。閘極電極106b係在形成金屬閘極電極120a之後才移除。之後，於開口118b中形成金屬閘極電極120b。
在一些其他實施例中，進行第一置換製程而以金 屬閘極電極120b置換閘極電極106b。之後，進行第二置換製程而以金屬閘極電極120a置換閘極電極106a。
如第1H圖所示，閘極堆疊10a具有厚度或寬度W1。在一些實施例中，寬度W1為約10奈米至約40奈米。如第1H圖所示，在一些實施例中，密封結構108a具有厚度或寬度W2，其為約5奈米至約15奈米。在一些其他實施例中，寬度W2為約7奈米至約10奈米。寬度W2為密封結構108a之底部部分的寬度。
在一些實施例中，閘極堆疊10a之寬度W1大於密封結構108a之寬度W2。在一些實施例中，密封結構108a與閘極堆疊10a間之寬度比值(width ratio)(W2/W1)為約0.05至約0.7。在一些其他實施例中，寬度比值(W2/W1)為約0.1至約0.5。
如前所述，虛置遮蔽層204係用作暫時性的主要間隙壁，且在形成源極/汲極區之後移除。用作接觸落點(contact landing)之區域不被任何的主要間隙壁所佔據。因此，增加了接觸落點區域(contact landing area)。如第1H所示，接觸落點區域大抵等於寬度W3。在一些實施例中，寬度W3係量測自密封結構108a之較低表面至隔離結構102之外緣。在一些實施例中，寬度W3為約20奈米至約50奈米。在一些其他實施例中，寬度W3為約30奈米至約40奈米。因此，由於沒有主要間隙壁佔據接觸落點區域，可較容易地於較大的接觸落點區域上形成接觸(contact)。因此，增進了效能及良率。
如第1H圖所示，半導體元件結構具有閘極-閘極間距P(gate-to-gate pitch)。由於無空間被主要間隙壁或暫時性間隙壁(虛置遮蔽層204，其已被移除)所佔據，因此相較於其他具 有主要間隙壁之半導體元件結構，閘極-閘極間距P被縮減了。在一些實施例中，閘極-閘極間距P為約30奈米至約90奈米。在一些其他實施例中，閘極-閘極間距P為約40奈米至約70奈米。
如第1H圖所示，根據一些實施例，金屬閘極電極120a及120b分別直接接觸密封結構108a及108b。例如，密封結構108a及108b分別直接接觸金屬閘極電極120a及120b之功函數層。然而，在一些其他實施例中，有其他材料層介於金屬閘極電極與密封結構之間，將在下文中更詳細地敘述。
第2圖顯示根據一些實施例之半導體元件結構的剖面圖。在一些實施例中，亦以其他閘極介電層置換閘極介電層104。如第2圖所示，根據一些實施例，相繼於開口118a及118b之底部及側壁上形成閘極介電層304a及304b以置換閘極介電層104。在一些其他實施例中，閘極介電層304a及304b係圖案化自相同的介電層。在這些情形下，閘極介電層304a及304b之材質是相同的。在一些實施例中，在形成閘極介電層304a及304b之後，形成遮蔽層(未顯示)以覆蓋及/或填充其中一開口(118a或118b)以輔助後續金屬閘極電極120a及120b之形成。相似於第1H圖所示之實施例，相繼形成金屬閘極電極120a及120b。
閘極介電層304a及304b可包括高介電常數材料(high-k rmaterial)。高介電常數材料可包括氧化鉿(HfO2)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鉭鉿(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、其他適合的高介電常數材料、或前述之組合。高介電常數材料可更包括金屬氧化物、金屬氮 化物、金屬矽玻璃、過渡金屬-氧化物、過渡金屬-氮化物、過渡金屬-矽玻璃(transition metal-silicates)、金屬氮氧化物、金屬鋁酸鹽(rmetal aluminates)、鋯矽玻璃、鋯鋁酸鹽、氧化矽、氮化矽、氮氧化矽、氧化鋯、氧化鈦、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他適合的材料、或前述之組合。
如第2圖所示，根據一些實施例，金屬閘極電極120a或120b不直接接觸密封結構108a或108b。閘極介電層304a(或304b)隔離金屬閘極電極120a(或120b)與密封結構108a(或108b)。在一些實施例中，部分的輕摻雜源極/汲極區(例如，摻雜區110a及110b)分別被密封結構108a及108b所覆蓋。
本揭露書之實施例具有許多變化。例如，輕摻雜源極/汲極區(例如，摻雜區110a或110b)不限於被密封結構所覆蓋。第3圖顯示根據一些實施例之半導體元件結構的剖面圖。如第3圖所示，根據一些實施例，輕摻雜源極/汲極區之端點部分與密封結構(例如，密封結構108a或108b)之外表面係彼此對齊或大抵彼此對齊。在一些實施例中，輕摻雜源極/汲極區(例如，摻雜區110a或110b)不被密封結構108a或108b所覆蓋或不延伸至密封結構108a或108b之下。
提供了形成半導體元件結構之實施例。將虛置遮蔽層(例如，光阻層)用作暫時性主要間隙壁，以輔助用以形成半導體元件結構之源極及汲極區(例如，重摻雜源極及汲極區)的佈植製程。之後，可輕易地移除虛置遮蔽層使得無主要間隙壁保留於半導體元件結構之閘極堆疊上。因此，縮減了閘極-閘極間距，且增加了接觸落點區域。由於不需為了形成主要間 隙壁而形成介電層，並小心地蝕刻及調整其輪廓，可顯著地減少製程時間與成本。因此，增進了半導體元件結構之良率與可靠度。
根據一些實施例，提供了一種半導體元件結構的形成方法。方法包括於半導體基底上形成閘極堆疊，並於閘極堆疊之側壁上形成密封結構。方法還包括於半導體基底、密封結構、及閘極堆疊上形成虛置遮蔽層。方法更包括於虛置遮蔽層上進行離子佈植製程以於半導體基底中形成源極及汲極區。此外，方法包括在形成源極及汲極區之後，移除虛置遮蔽層。
根據一些實施例，提供了一種半導體元件結構的形成方法。方法包括於半導體基底上形成第一閘極堆疊及第二閘極堆疊，並分別於第一閘極堆疊及第二閘極堆疊之側壁上形成密封結構。方法還包括於密封結構上形成虛置遮蔽層。方法更包括相繼於虛置遮蔽層上進行離子佈植製程以分別於半導體基底中及於第一閘極堆疊及第二閘極堆疊之相對側相繼形成第一源極及汲極區及第二源極及汲極區。此外，方法包括在形成第一源極及汲極區及第二源極及汲極區之後，移除虛置遮蔽層。
根據一些實施例，提供了一種半導體元件結構。半導體元件結構包括半導體基底及於半導體基底上之閘極堆疊。半導體元件結構還包括於閘極堆疊之側壁上之密封結構，且密封結構與閘極堆疊間之寬度比值為約0.05至約0.7。半導體元件結構更包括於半導體基底、閘極堆疊、及密封結構上之蝕刻停止層。蝕刻停止層直接接觸密封結構。
雖然已詳細敘述實施例及其優點，應可明白的是，可在不脫離所附申請專利範圍所界定之實施例的精神及範圍的情形下，做出各種改變、置換、及變化。再者，本申請之範圍，非用以限制至說明書所述之特定實施例的製程、機器、製作、物質成分、手段、方法、及步驟。所屬技術領域具有通常知識者將可輕易地自本揭露書領會到，可根據本揭露書使用現存或未來將發展的製程、機器、製作、物質成分、手段、方法、或步驟，其如同在此所述相應實施例，能執行相同功能或達成相同結果。因此，所附申請專利範圍，用以在其範圍中包含這些製程、機器、製作、物質成分、手段、方法、或步驟。此外，每一申請專利範圍構成不同的實施例，且許多申請專利範圍與實施例之組合係在本揭露書之範圍之內。
10a、10b‧‧‧閘極堆疊
12N、12P‧‧‧井區
100‧‧‧半導體基底
102‧‧‧隔離結構
104‧‧‧閘極介電層
108a、108b‧‧‧密封結構
110a、110b‧‧‧摻雜區
112’‧‧‧源極及汲極區
116‧‧‧摻雜區
120a、120b‧‧‧金屬閘極電極
217‧‧‧蝕刻停止層
219‧‧‧絕緣層
P‧‧‧間距
W1、W2、W3‧‧‧寬度

Claims (10)

  1. 一種半導體元件結構的形成方法，包括：於一半導體基底上形成一閘極堆疊；於該閘極堆疊之一側壁上形成一密封結構；於該半導體基底、該密封結構、及該閘極堆疊上形成一虛置遮蔽層；於該虛置遮蔽層上進行一離子佈植製程以於該半導體基底中形成源極及汲極區；以及在形成該些源極及汲極區之後，移除該虛置遮蔽層。
  2. 如申請專利範圍第1項所述之半導體元件結構的形成方法，其中該虛置遮蔽層包括一光阻材料。
  3. 如申請專利範圍第2項所述之半導體元件結構的形成方法，更包括：在形成該虛置遮蔽層之前，於該半導體基底、該密封結構、及該閘極堆疊上形成一抗反射介電(ARD)層；以及移除該抗反射介電層。
  4. 如申請專利範圍第1項所述之半導體元件結構的形成方法，更包括於該半導體基底、該密封結構、及該閘極堆疊上形成一蝕刻停止層。
  5. 如申請專利範圍第1項所述之半導體元件結構的形成方法，其中該密封結構與該閘極堆疊間之一寬度比值為約0.05至約0.7。
  6. 如申請專利範圍第1項所述之半導體元件結構的形成方法，其中該虛置遮蔽層被完全移除。
  7. 一種半導體元件結構的形成方法，包括：於一半導體基底上形成一第一閘極堆疊及一第二閘極堆疊；分別於該第一閘極堆疊及該第二閘極堆疊之側壁上形成密封結構；於該些密封結構上形成一虛置遮蔽層；相繼於該虛置遮蔽層上進行離子佈植製程以分別於該半導體基底中及於該第一閘極堆疊及該第二閘極堆疊之相對側相繼形成第一源極及汲極區及第二源極及汲極區；以及在形成該些第一源極及汲極區及該些第二源極及汲極區之後，移除該虛置遮蔽層。
  8. 如申請專利範圍第7項所述之半導體元件結構的形成方法，其中該些第一源極及汲極區及該些第二源極及汲極區佈植有不同的摻質。
  9. 一種半導體元件結構，包括：一半導體基底；一閘極堆疊，於該半導體基底之上；一密封結構，於該閘極堆疊之一側壁上，其中該密封結構與該閘極堆疊間之一寬度比值為約0.05至約0.7；以及一蝕刻停止層，於該半導體基底、該閘極堆疊、及該密封結構之上，其中該蝕刻停止層直接接觸該密封結構。
  10. 如申請專利範圍第9項所述之半導體元件結構，其中該密封結構與該蝕刻停止層之間不具有中間層。
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