CN107026194A - 半导体装置与形成半导体装置的方法 - Google Patents

半导体装置与形成半导体装置的方法 Download PDF

Info

Publication number
CN107026194A
CN107026194A CN201710061615.9A CN201710061615A CN107026194A CN 107026194 A CN107026194 A CN 107026194A CN 201710061615 A CN201710061615 A CN 201710061615A CN 107026194 A CN107026194 A CN 107026194A
Authority
CN
China
Prior art keywords
gate
layer
dielectric
top surface
work
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710061615.9A
Other languages
English (en)
Inventor
林志翰
张哲诚
曾鸿辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202110437210.7A priority Critical patent/CN113140625A/zh
Publication of CN107026194A publication Critical patent/CN107026194A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种形成半导体装置的方法，包括接收装置，装置具有基板及环绕栅极沟槽的第一介电层。方法更包括在栅极沟槽中沉积栅极介电层及栅极功函数(work function，WF)层，及在由栅极功函数层环绕的空间中形成硬遮罩(hard mask，HM)层。方法更包括使栅极功函数层凹陷以使得栅极沟槽中的栅极功函数层的顶表面在第一介电层的顶表面下方。在使栅极功函数层凹陷之后，方法更包括移除栅极沟槽中的硬遮罩层。在移除硬遮罩层之后，方法更包括在栅极沟槽中沉积金属层。

Description

半导体装置与形成半导体装置的方法
技术领域
本揭露涉及一种半导体装置及其制造方法，特别涉及上一种用于场效晶体管(field-effect transistor；FET)的金属栅极，及形成金属栅极的方法。
背景技术
半导体集成电路(integrated circuit；IC)工业已经历指数增长。IC材料及设计的技术进步已产生数代IC，其中每一代均具有与前一代相比较小且较复杂的电路。在IC进化过程中，功能密度(即每芯片面积的互连装置数目)已大体上增加，同时几何尺寸(即可使用制造制程产生的最小元件(或线))已减小。此缩小制程大体藉由增加生产效率及降低相关联的成本来提供益处。此缩小亦已增加IC处理及制造的复杂性。
一些IC设计中的一个发展为用高介电常数/金属栅极(high-k/metal gate；HK/MG)替代传统多晶硅栅极。典型HK/MG包括高介电常数栅极介电层、功函数(work function；WF)金属层及低电阻金属填充层。此结构应改良晶体管密度及切换速度，同时降低切换功率及栅极泄漏。随着技术节点继续缩小，在HK/MG的制造中出现一些困难。困难中的一者为金属填充层可具有较小占地面积，因此栅极接触件难以适当地降落在金属填充层上。
发明内容
本揭露有关一种形成半导体装置的方法，包含接收一装置，装置具有一基板及一第一介电层，第一介电层位在基板上，且第一介电层环绕一栅极沟槽；沉积一栅极介电层于栅极沟槽中；沉积一栅极功函数层于栅极沟槽中且在栅极介电层上；形成一硬遮罩层于一间隔中，间隔位在栅极沟槽中且由栅极功函数层所环绕；使栅极功函数层凹陷以使得栅极沟槽中的栅极功函数层的一顶表面在第一介电层的一顶表面下方；在使栅极功函数层凹陷之后，移除栅极沟槽中的硬遮罩层；以及在移除硬遮罩层之后，沉积一金属层于栅极沟槽中。
本揭露更有关一种形成半导体装置的方法，包含：接收一装置，装置具有一基板、一栅极间隔物及一第一介电层，栅极间隔物在基板上且提供一栅极沟槽，第一介电层在基板上且环绕栅极间隔物；沉积一栅极介电层于栅极沟槽的一底部及多个侧壁上；沉积一栅极功函数层于栅极沟槽中且在栅极介电层上；形成一硬遮罩层于基板上且填入由栅极功函数层所环绕的一间隔；蚀刻硬遮罩层以使得栅极沟槽中的硬遮罩层的一顶表面在第一介电层的一顶表面下方；蚀刻栅极功函数层以使得栅极沟槽中的栅极功函数层的一顶表面在第一介电层的一顶表面下方；蚀刻栅极介电层以使得栅极沟槽中的栅极介电层的一顶表面在第一介电层的一顶表面下方；移除栅极沟槽中的硬遮罩层，从而提供由栅极功函数层环绕的一第一间隔及在栅极功函数层及栅极介电层的各别顶表面与第一介电层的顶表面之间的第二间隔；及填入一金属层于第一间隔及第二间隔中。
本揭露更有关一种半导体装置，包含：一基板；一第一介电层，位在基板上且环绕一栅极沟槽；一栅极介电层，位在栅极沟槽的一底部及多个侧壁上；一栅极功函数层位在栅极介电层上且在栅极沟槽中，其中栅极功函数层的一顶表面低于第一介电层的一顶表面；以及一金属层，填入栅极沟槽中的一第一间隔及一第二间隔，其中第一间隔系由栅极功函数层环绕且第二间隔在栅极功函数层的顶表面与第一介电层的顶表面之间。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
本揭露最佳是在结合随附的附图解读时自以下详细描述来理解。应强调，根据工业中的标准实务，各种特征并非按比例绘制且仅用于说明目的。事实上，出于论述清晰的目的，可任意增加或减小各种特征的尺寸。
图1说明根据本揭露的一实施例构建的具有金属栅极结构的半导体装置；
图2A及图2B显示根据本揭露的各种态样的形成半导体装置的方法的方框图；
图3A说明根据一实施例的在根据图2A及图2B的方法的制造阶段期间的半导体装置的部分透视图；
图3B、图3C、图3D、图3D-1、图3E、图3F、图3G、图3H、图3I、图3J、图3K及图3L说明根据一些实施例的根据图2A及图2B的方法形成靶材半导体装置的截面图；
图4显示根据本揭露的各种态样的形成半导体装置的方法的方框图；以及
图5A、图5B及图5C说明根据一些实施例的根据图4的方法形成靶材半导体装置的截面图。
其中，附图标记
1 线
100 半导体装置
102 基板
104 鳍
104a 源极/汲极区域
104b 通道区域
106 隔离结构
108 栅极间隔物
110 介电层
112 栅极沟槽
114 介面层
116 栅极介电层
118 功函数层
120 间隔
120-1 间隔
122 硬遮罩层
124 间隔
128 金属填充层
128L 下部
128U 上部
130 金属栅极
132 介电层
134 栅极接触件
200 方法
202 操作
204 操作
206 操作
208 操作
210 操作
212 操作
214 操作
216 操作
218 操作
220 操作
222 操作
400 方法
408 操作
D1 深度
D2 尺寸
D3 尺寸
S110 顶表面
S116 顶表面
S118 顶表面
S122 顶表面
S128 顶表面
W1 尺寸
W2 尺寸
W3 尺寸
具体实施方式
以下揭露内容提供许多不同实施例或实例用于实施所提供的标的物的不同特征。下文描述元件及布置的特定实例以简化本揭露。当然，此些仅为实例且并不意欲为限制性。举例而言，以下描述中在第二特征上方或第二特征上形成第一特征可包括以直接接触形成第一特征及第二特征的实施例，且亦可包括可在第一特征与第二特征之间形成额外特征以使得第一特征与第二特征可不直接接触的实施例。另外，本揭露可在各种实例中重复元件符号及/或字母。此重复是出于简明性及清晰的目的，且本身并不指示所论述的各种实施例及/或配置之间的关系。
此外，为便于描述，本文可使用空间相对性术语(诸如「之下」、「下方」、「下部」、「上方」、「上部」及类似者)来描述附图中所说明的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了附图中所描绘的定向外，空间相对性术语意欲包含在使用或操作中的装置的不同定向。设备可以其他方式定向(旋转90度或其他定向)且因此可同样地解释本文所使用的空间相对性描述词。
本揭露大体上是关于半导体装置及制造。详言之，本揭露是关于用于场效晶体管(field-effect transistor；FET)的金属栅极，诸如高介电常数金属栅极(HK/MG)，及形成金属栅极的方法。
图1显示根据本揭露的一实施例的具有金属栅极130(由虚线包围)的半导体装置100。参考图1，装置100包括基板102、安置在基板102上的栅极间隔物108及环绕栅极间隔物108的介电层110。装置100更包括栅极介电层116、功函数(work function；WF)层118及在由栅极间隔物108界定的空间中所沉积的金属填充层128。金属填充层128的下部是由WF层118环绕。栅极介电层116、WF层118及金属填充层128为金属栅极130的层。在一实施例中，尽管未显示，但装置100可包括其他特征，诸如在栅极介电层116下方的介面层。栅极介电层116可包括高介电常数介电材料，因此使得金属栅极130成为HK/MG。装置100更包括在栅极间隔物108、介电层110及栅极沟槽128上的另一介电层132。装置100更包括穿透介电层132且降落在金属栅极130上(特定而言在金属填充层128上)的栅极接触件134。
仍参考图1，金属填充层128的顶表面高于栅极介电层116及WF层118的各别顶表面。金属填充层128具有与栅极介电层116及WF层118相比相对较大的占地面积(自俯视图检视)。因此，栅极接触件134直接接触金属填充层128，但不直接接触栅极介电层116或WF层118。在实施例中，金属填充层128包括低电阻金属。归因于金属填充层128的较大占地面积，装置100提供低栅极接触电阻。特定而言，与金属填充层128具有较小占地面积且栅极接触件134直接接触WF层118或栅极介电层116的情况下的栅极接触电阻相比，装置100提供较低的栅极接触电阻。此外，金属填充层128的较大占地面积有利地放大用于制造栅极接触件134的制程窗。
参考图2A及图2B，其中显示根据本揭露的各种态样形成半导体装置(诸如装置100)的方法200。方法200为实例，且不意欲将本揭露限制超出权利要求范围中明确叙述的范畴。可在方法200之前、在其期间及在其之后提供额外操作，且所描述的一些操作可经替代、消除或重新安置以实现方法的额外实施例。下文结合图3A至图3L描述方法200。图3A显示半导体装置100的一部分的透视图，而图3B至图3L显示根据本揭露的态样的在各种制造阶段期间的沿着图3A的「1-1」线的半导体装置100的部分的截面图。
如将显示，装置100为鳍式FET装置。此不一定将实施例限制于任何装置类型、任何装置数目、任何区域数目或任何结构或区域配置。举例而言，所提供的标的物可应用在制造平坦FET装置及其他类型的多栅极FET装置中用于在栅极接触件制造期间减少栅极接触电阻及用于扩大制程窗。此外，装置100可为在IC或其一部分的处理期间制造的中间装置，其可包括静态随机存取记忆体(static random access memory；SRAM)及/或其他逻辑电路、被动元件(诸如电阻器、电容器及电感器)及主动元件(诸如p型FET(p-type FET；PFET)、n型FET(n-type FET；NFET)、鳍式FET、金属氧化物半导体场效晶体管(metal-oxidesemiconductor field effect transistor；MOSFET)、互补金属氧化物半导体(complementary metal-oxide semiconductor；CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管)、其他记忆体单元及其组合。
参考图2A，在操作202处，方法200提供或具备处于一个处理状态的装置100。共同地参考图3A及图3B，装置100包括基板102、在基板102上的鳍104及在基板102上的隔离结构106。鳍104突出至隔离结构106之外。鳍104包括通道区域104b及两个源极/汲极区域104a。在本实施例中，装置100更包括安置在鳍104及隔离结构106上的栅极间隔物108。在一替代实施例中，可省略栅极间隔物108。进一步在本实施例中，装置100包括环绕栅极间隔物108(至少在其侧壁上)的介电层110。栅极间隔物108的内部侧壁界定出栅极沟槽112，其实质上沿着「z」方向与通道区域104b对准。下文进一步描述装置100的各种元件。
在本实施例中，基板102为硅基板。或者，基板102可包括另一元素半导体，诸如锗；化合物半导体，包括碳化硅、镓砷、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其组合。在又一替代方案中，基板102为绝缘体上半导体(semiconductor-on-insulator；SOI)基板。基板102可包括磊晶特征、经应变以达成效能增强及/或具有其他适宜的增强特征。
鳍104包括半导体材料且适用于在其上形成鳍式FET装置，诸如p型鳍式FET或n型鳍式FET。鳍104可使用适宜的制程(包括微影术及蚀刻制程)制造。微影术制程可包括形成上覆基板102的光阻剂(光阻)层、使光阻曝露于图案、执行曝露后烘焙制程及使光阻显影以形成包括光阻的遮罩元件。遮罩元件随后用于向基板102中蚀刻凹陷，同时使鳍104保留在基板102上。蚀刻制程可包括干式蚀刻、湿式蚀刻、反应性离子蚀刻(reactive ionetching；RIE)及/或其他适宜的制程。举例而言，干式蚀刻制程可实施含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴气体(例如，HBr及/或CHBR3)、含碘气体、其他适宜的气体及/或等离子体及/或其组合。举例而言，湿式蚀刻制程可包括在稀释氢氟酸(diluted hydrofluoric acid；DHF)；氢氧化钾(KOH)溶液；氨水；含有氢氟酸(HF)、硝酸(HNO3)及/或醋酸(CH3COOH)的溶液或其他适宜的湿式蚀刻剂中蚀刻。在一些实施例中，鳍104可藉由双图案化微影术(double-patterninglithography；DPL)制程形成。在基板102上形成鳍104的方法的多个其他实施例可为适宜的。
隔离结构106可由氧化硅、氮化硅、氮氧化硅、氟硅酸盐玻璃(fluoride-dopedsilicate glass；FSG)、低介电常数介电材料及/或其他适宜的绝缘材料形成。在一实施例中，隔离结构106是由在基板102中蚀刻沟槽(例如以鳍104形成制程的一部分的形式)形成。可随后用隔离材料填充沟槽，接着执行化学机械平坦化(chemical mechanicalplanarization；CMP)制程。隔离结构106亦可包括场氧化物、硅的局部氧化(LOCalOxidation of Silicon；LOCOS)及/或其他适宜的结构。隔离结构106可包括例如具有一或多个热氧化物内衬层的多层结构。
栅极间隔物108可包括氧化硅、氮化硅、碳化硅氮化物(SiCN)、氮氧化硅(SiON)、碳化硅氮氧化物(SiCON)或其他适宜的介电材料。栅极间隔物108可藉由沉积及蚀刻制程形成。沉积处理可为化学气相沉积(chemical vapor deposition；CVD)、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomic layer deposition；ALD)或其他适宜的沉积技术。在一个实例中，蚀刻制程可为各向异性干式蚀刻制程。在方法200包括栅极替换制程的一实施例中，栅极间隔物108首先在虚设栅极的侧壁上形成，且虚设栅极随后经移除，从而提供在栅极间隔物108的相对侧壁之间的栅极沟槽112。栅极沟槽112具有沿着「x」方向的尺寸W1，其亦为通道长度方向。尺寸W1的值取决于鳍式FET装置100的类型(例如，SRAM装置或逻辑装置)以及用于形成鳍式FET装置100的制程节点(例如，22nm、10nm、7nm等)。
介电层110可包括一或多种介电材料，诸如正硅酸四乙酯(TEOS)氧化物、未经掺杂的硅酸盐玻璃，或经掺杂的氧化硅，诸如硼磷硅玻璃(borophosphosilicate glass；BPSG)、熔融硅石玻璃(fused silica glass；FSG)、磷硅玻璃(phosphosilicate glass；PSG)、掺杂硼的硅玻璃(boron doped silicon glass；BSG)及/或其他适宜的介电材料。介电层110可藉由等离子体增强CVD(plasma enhanced CVD；PECVD)制程、可流动CVD(flowable CVD；FCVD)或其他适宜的沉积技术沉积。在一实施例中，装置100更包括在介电层110下面的蚀刻终止层(未显示)，且蚀刻终止层可包括氮化硅、氧化硅、氮氧化硅及/或其他材料。
在操作204处，方法200(图2A)在栅极沟槽112中沉积栅极介电层116。参考图3C，在栅极沟槽112的底表面及侧壁表面上沉积栅极介电层116。在本实施例中，在沉积栅极介电层116之前，方法200在栅极沟槽112中及在通道区域104b上沉积介面层114。介面层114可包括介电材料，诸如氧化硅层(SiO2)或氮氧化硅(SiON)，且可藉由化学氧化、热氧化、ALD、CVD及/或其他适宜的技术形成。在一替代实施例中，省略介面层114。
继续如图3C中所示的本实施例，在介面层114上沉积栅极介电层116。栅极介电层116可包括高介电常数介电材料，诸如氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、其他适宜的金属氧化物或其组合。栅极介电层116可藉由ALD及/或其他适宜的方法形成。
在操作206，方法200(图2A)在栅极沟槽112的底部及侧壁上沉积栅极WF层118。参考图3D，栅极WF层118经沉积在栅极介电层116上且部分填充栅极沟槽112。取决于鳍式FET100的类型，栅极WF层118可为p型或n型功函数层。p型功函数层包括有效功函数足够大的金属，其选自(但不限于)以下各者组成的群：氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或其组合。n型功函数层包括有效功函数足够低的金属，其系选自(但不限于)以下各者组成的群：钛(Ti)、铝(Al)、碳化钽(TaC)、碳化钽氮化物(TaCN)、氮化钽硅(TaSiN)或其组合。栅极WF层118可包括多个层且可藉由CVD、PVD及/或其他适宜的制程沉积。在一实施例中，方法200执行CMP制程以移除栅极介电层116及栅极WF层118在栅极沟槽112之外的多余的材料，从而使装置100的顶表面平坦化。
仍参考图3D，栅极WF层118提供具有沿着「x」方向的尺寸W2的间隔120。如将随后显示，将向间隔120中沉积金属填充层(诸如图1的金属填充层128)。在本实施例中，宽度W2等于或大于用于沉积金属填充层128的临界尺寸。随着制程节点变得较小，间隔120亦可变得较小。如图3D-1中所示，在一实例中，在沉积栅极WF层118之后，如由栅极WF层118环绕的间隔120-1具有小于临界尺寸的尺寸W3。因此，金属填充层128可能未经适当地填充至间隔120-1中，因为其轮廓狭窄。继续此实例，方法200经由图案化及蚀刻制程扩展间隔120-1以使得间隔120-1放大，如图3D中所示。图案化制程可包括微影术，且蚀刻制程可经选择性调适以蚀刻栅极WF层118。
在操作208处，方法200(图2A)在层108、110、116及118上沉积硬遮罩(hard mask；HM)层122且填充间隔120。参考图3E，HM层122可包括介电材料，诸如氧化硅(SiO2)、氮化硅(SiN)、碳氮化硅(SiCN)、碳氮氧化硅(SiCON)、氮氧化硅(SiON)、其他适宜的介电材料或其组合。HM层122可藉由ALD、热氧化、化学氧化、CVD、PVD或其他沉积技术形成。在一实施例中，HM层122为光阻且系藉由包括旋涂的制程形成。在各种实施例中，HM层122具有相对于栅极间隔物108、介电层110、栅极介电层116及功函数层118的蚀刻选择性。在一实施例中，HM层122经沉积在包括PFET与NFET两者的装置100的全部表面上。
在操作210处，方法200(图2A)回蚀HM层122。参考图3F，移除HM层122的覆盖栅极间隔物108、介电层110、栅极介电层116及功函数层118的部分。此外，使在间隔120中的HM层122的部分(图3D)凹陷以使得HM层122的顶表面S122位在介电层110的顶表面S110下方沿着「z」方向一尺寸D1之处。在装置100包括PFET与NFET两者的一实施例中，HM层122可经回蚀在PFET(或NFET)区域中，同时其受NFET(或PFET)区域中的遮罩元件保护。此使得能够对于PFET及NFET的效能作独立调适。此等独立的PFET及NFET调适可类似地在包括随后论述的操作212、214、216及218之后续操作中应用。在实施例中，操作210可使用湿式蚀刻、干式蚀刻、原子层蚀刻(atomic layer etching；ALE)、反应性离子蚀刻或其他回蚀技术。此外，在一实施例中，操作210使用选择性蚀刻，其经调适以蚀刻HM层122同时使层栅极间隔物108、介电层110、栅极介电层116及功函数层118保持实质上不变。此外，HM层122的蚀刻为自对准的，亦即HM层122在除如前述的PFET及NFET的独立调适之外不使用微影术图案化制程的情况下经蚀刻。在一个实例中，操作210可使用计时器模式控制深度D1。
在操作212，方法200(图2A)使栅极WF层118在栅极沟槽112中凹陷。参考图3G，使栅极WF层118凹陷以使得栅极WF层118的顶表面S118位在介电层110的顶表面S110下方沿着「z」方向一尺寸D2之处。自俯视图，在栅极WF层118/硬遮罩层122的各别顶表面与顶表面S110之间的间隔124具有与间隔120(图3D)相比较大的占地面积。在实施例中，沿着「z」方向，表面S118可高于或低于表面S122。或者，表面S118可处于与表面S122实质上相同的位准。操作212可包括干式蚀刻、湿式蚀刻、ALE或其他蚀刻技术。此外，操作212包括蚀刻制程，其经选择性调适以蚀刻栅极WF层118同时使栅极间隔物108、介电层110、栅极介电层116及硬遮罩层122保持实质上不变。HM层122保护栅极WF层118的底表面及部分侧壁免受蚀刻制程损害。在一个实例中，操作212可使用计时器模式控制尺寸D2。如将显示，尺寸D2系关于金属填充层128的厚度(图1)。此外，栅极WF层118的蚀刻为自对准的，亦即在不使用微影术图案化制程的情况下使栅极WF层118凹陷在栅极沟槽112内。
在操作214处，方法200(图2B)使栅极介电层116凹陷在栅极沟槽112中。参考图3H，使栅极介电层116凹陷以使得栅极介电层116的顶表面S116位在顶表面S110下方沿着「z」方向一尺寸D3之处。操作214沿着「x」方向进一步扩展间隔124。在实施例中，沿着「z」方向，表面S116可高于或低于表面S118。或者，表面S116可处于与表面S118实质上相同的位准。操作214可包括干式蚀刻、湿式蚀刻、ALE或其他蚀刻技术。此外，操作214包括蚀刻制程，其经选择性调适以蚀刻栅极介电层116同时使栅极间隔物108、介电层110、功函数层118及硬遮罩层122保持实质上不变。在一个实例中，操作214可使用计时器模式控制尺寸D3。如将显示，在一些实施例中，尺寸D3是关于金属填充层128的厚度(图1)。此外，栅极介电层116的蚀刻为自对准的，亦即在不使用微影术图案化制程的情况下使栅极介电层116凹陷在栅极沟槽112内。
在方法200的一实施例中，不执行操作214，且方法200自操作212继续至操作216而不使栅极介电层116凹陷。在方法200的另一实施例中，操作212及214是在一个制造步骤中执行，亦即同时蚀刻栅极WF层118及栅极介电层116。继续此实施例，使用包括用于两个层的蚀刻剂的同一配方蚀刻层116及118。举例而言，配方可同时使用含氟气体(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)以蚀刻栅极WF层118，及使用含氯气体(例如，Cl2、CHCl3、CCl4及/或BCl3)以蚀刻栅极介电层116。
在操作216处，方法200(图2B)自栅极沟槽112移除HM层122。参考图3I，其中显示移除HM层122之后的装置100。在栅极沟槽112内，装置100包括凹陷的栅极WF层118及凹陷的栅极介电层116。在栅极沟槽112中提供间隔且其包括间隔120及124。在各种实施例中，操作216的许多方面类似于操作210的彼等方面。特定而言，操作216使用选择性蚀刻，其经调适以蚀刻HM层122同时使栅极间隔物108、介电层110、栅极介电层116数层118保持实质上不变。操作216可执行清洁制程，其清洁环绕间隔120及124的各种表面。
在操作218处，方法200(图2B)在栅极沟槽112中沉积金属填充层(或金属层)128。参考图3J，金属填充层128填充间隔120及124。金属填充层128可包括铝(Al)、钨(W)、钴(Co)、铜(Cu)及/或其他适宜的材料。金属填充层128可藉由CVD、PVD、电镀及/或其他适宜的制程沉积。在一实施例中，操作218更包括CMP制程，其移除在栅极沟槽112之外的多余的金属材料且使装置100的顶表面平坦化。因此，金属填充层128的顶表面S128实质上与表面S110共面。仍参考图3J，金属填充层128具有两个部分：由栅极WF层118环绕的下部128L，及在下部128L上且在各别顶表面S118及S116上的上部128U。自俯视图，上部128U具有与下部128L相比较大的占地面积(或面积)。
在操作220处，方法200(图2B)在金属填充层128上形成栅极接触件134。参考图3K，栅极接触件134穿透介电层132且与金属填充层128电接触。在一实施例中，操作220涉及多种制程，包括沉积、CMP、微影术及蚀刻制程。举例而言，操作220在栅极间隔物108、介电层110及金属填充层128上沉积介电层132，且对介电层132执行CMP制程。介电层132可包括类似于介电层110的介电材料的介电材料，且可藉由PECVD制程、FCVD制程或其他适宜的沉积技术沉积。在实施例中，介电层132可包括一或多个材料层。随后，操作220经由微影术图案化及蚀刻制程在介电层132中形成开口。开口曝露出金属填充层128。归因于金属填充层128的增大的占地面积，操作220在微影图案化制程中具有较大制程窗。随后，操作220在开口中形成栅极接触件134。如图3K中所示，栅极接触件134完全落在金属填充层128上。由于金属填充层128为低电阻材料，因此总栅极接触电阻减小。
在一实施例中，栅极接触件134包括阻障层及在阻障层上的栅极通孔。阻障层可包括钽(Ta)、氮化钽(TaN)或另一适宜的金属扩散阻障材料；可使用CVD、PVD、ALD或其他适宜的制程沉积。栅极通孔使用导电材料，诸如铝(Al)、钨(W)、铜(Cu)、钴(Co)、其组合或其他适宜的材料；且可使用适宜的制程沉积，诸如CVD、PVD、电镀及/或其他适宜的制程。
图3L显示装置100的另一实施例，其未经历如上文所论述的操作214。参考图3L，在此实施例中，金属填充层128的上部128U是由栅极介电层116环绕；因此，其具有与在图3K中相比较小的占地面积。然而，其占地面积仍大于下部128L的占地面积。
在操作222处，方法200(图2B)继续至其他步骤以完成装置100的制造。举例而言，操作222可形成连接装置100的多个元件(例如，p型鳍式FET、n型鳍式FET、其他类型的FET、电阻器、电容器及电感器)以形成完整IC的金属互连件。
图4说明方法400的流程图，方法400可视为方法200的一实施例。方法400的许多方面类似于方法200的多种方面。因此，下文结合图5A至图5C对其简要论述。
参考图4，方法400自操作206继续至操作408，操作408在由WF层118环绕的间隔120中沉积HM层122(图5A)。在一实施例中，操作408包括操作208及210，如上文所论述，其中操作210仅稍微使HM层122凹陷在栅极沟槽112内(亦即，深度D1极小)。在另一实施例中，操作408包括操作208，其用于在各种栅极间隔物108、介电层110、栅极介电层116及功函数层118(参见图3E)上沉积HM层122。且更包括操作210，其使用CMP制程以回蚀HM层122，从而使HM层122的一部分保留在栅极沟槽112中，如图5A中所示。
方法400(图4)自操作408继续至操作212，操作212使WF层118凹陷在栅极沟槽112中，如图5B中所示。因此，顶表面S118在顶表面S110下方。在本实施例中，WF层118的凹陷为自对准的，亦即不使用微影术图案化制程。此为表面S118在(或低于)表面S122下方的实例。此外，操作212使用关于图3G论述的选择性蚀刻制程。
方法400(图4)自操作212继续至操作214，操作214使栅极介电层116凹陷在栅极沟槽112中，如图5C中所示。因此，顶表面S116在顶表面S110下方。在本实施例中，栅极介电层116的凹陷为自对准的，亦即不使用微影术图案化制程。此外，操作214使用关于图3H论述的选择性蚀刻制程。在实施例中，方法400可跳过操作214，如上文所论述。在替代实施例中，方法400可在一个制造步骤中执行操作212及214，如上文所论述。
方法400(图4)继续至操作216，其自栅极沟槽112移除HM层122。在一实施例中，此与方法200(图2B)的操作216相同。因此，装置100提供第一间隔120及第二间隔124，如图3I中所示。其后，方法400(图4)继续至操作218以沉积金属填充层128，如上文关于图2B及图3J所论述。
尽管不意欲为限制性，但本揭露的一或多个实施例为半导体装置及其形成提供许多益处。举例而言，本揭露的实施例在沉积金属填充层之前，使栅极功函数层及栅极介电层凹陷。所得金属填充层具有增大的上部，其提供与典型金属栅极相比较大的占地面积。此有利地放大用于栅极接触件图案化制程的制程窗。此亦有利地减小栅极接触电阻。此外，栅极功函数层及栅极介电层的凹陷为自对准的，亦即不使用微影术图案化制程。本揭露的实施例可容易地整合至现有制造流程中用于改良金属栅极制程及改良装置效能。
在一个示例性态样中，本揭露有关一种形成半导体装置的方法，包含接收一装置，装置具有一基板及一第一介电层，第一介电层位在基板上，且第一介电层环绕一栅极沟槽；方法更包括，沉积一栅极介电层于栅极沟槽中；方法更包括，沉积一栅极功函数层于栅极沟槽中且在栅极介电层上；方法更包括，形成一硬遮罩层于一间隔中，间隔位在栅极沟槽中且由栅极功函数层所环绕；方法更包括，使栅极功函数层凹陷以使得栅极沟槽中的栅极功函数层的一顶表面在第一介电层的一顶表面下方；方法更包括，在使栅极功函数层凹陷之后，移除栅极沟槽中的硬遮罩层。方法更包括，在移除硬遮罩层之后，沉积一金属层于栅极沟槽中。
在一些实例中，上述讨论的方法是更包含，在沉积金属层之前，使栅极介电层凹陷以使得栅极沟槽中的栅极介电层的一顶表面在第一介电层的顶表面下方。在一些实例中，上述讨论的方法更包含，形成一栅极接触件于金属层上，且与金属层电连接。在一些实例中，上述讨论的方法更包含，使栅极功函数层凹陷包括一选择性蚀刻制程，选择性蚀刻制程经调适以蚀刻栅极功函数层并同时使第一介电层及硬遮罩层保持实质上不变。在一些实例中，上述讨论的方法中，使栅极功函数层凹陷更使栅极介电层凹陷以使得栅极沟槽中的栅极介电层的一顶表面在第一介电层的顶表面下方。在一些实例中，上述讨论的方法中，移除硬遮罩层包括一选择性蚀刻制程，选择性蚀刻制程经调适以蚀刻硬遮罩层并同时使第一介电层、栅极介电层及栅极功函数层保持实质上不变。在一些实例中，上述讨论的方法更包含，在形成硬遮罩层之前，蚀刻栅极功函数层以提供所述间隔。在一些实例中，上述讨论的方法中形成硬遮罩层包括，沉积一硬遮罩材料于基板上且填入所述间隔；以及回蚀硬遮罩材料。在一些实例中，上述讨论的方法中，回蚀硬遮罩材料包括一选择性蚀刻制程，选择性蚀刻制程经调适以蚀刻硬遮罩材料，并同时使第一介电材料、栅极介电材料及栅极功函数材料保持实质上不变。在一些实例中，上述讨论的方法中，回蚀硬遮罩材料包括一化学机械平坦化(chemical mechanical planarization；CMP)制程。在一些实例中，上述讨论的方法中，装置更包括一栅极间隔物，以作为栅极沟槽的多个侧壁。
在另一示例性态样中，本揭露涉及形成半导体装置的方法。方法包括接收一装置，装置具有一基板、一栅极间隔物及一第一介电层，栅极间隔物在基板上且提供一栅极沟槽，第一介电层在基板上且环绕栅极间隔物。方法更包括沉积一栅极介电层于栅极沟槽的一底部及多个侧壁上，及沉积一栅极功函数层于栅极沟槽中且在栅极介电层上。方法更包括形成一硬遮罩层于基板上且填入由栅极功函数层所环绕的一间隔，及蚀刻硬遮罩层以使得栅极沟槽中的硬遮罩层的一顶表面在第一介电层的一顶表面下方。方法更包括蚀刻栅极功函数层以使得栅极沟槽中的栅极功函数层的一顶表面在第一介电层的一顶表面下方。方法更包括蚀刻栅极介电层以使得栅极沟槽中的栅极介电层的一顶表面在第一介电层的一顶表面下方。方法更包括移除栅极沟槽中的硬遮罩层，从而提供由栅极功函数层环绕的一第一间隔及在栅极功函数层及栅极介电层的各别顶表面与第一介电层的顶表面之间的第二间隔。方法更包括填入一金属层于第一间隔及第二间隔中。
在一些实例中，上述讨论的方法中，硬遮罩层的蚀刻及硬遮罩层的移除中的每一者均包括一选择性蚀刻制程，选择性蚀刻制程经调适以蚀刻硬遮罩层，同时使栅极间隔物、第一介电层、栅极介电层及栅极功函数层保持实质上不变。在一些实例中，上述讨论的方法中，蚀刻栅极功函数层包括一选择性蚀刻制程，选择性蚀刻制程经调适以蚀刻栅极功函数层同时使栅极间隔物、第一介电层及硬遮罩层保持实质上不变。在一些实例中，上述讨论的方法中，蚀刻栅极功函数层及蚀刻栅极介电层是在一个制造步骤中执行。
在另一示例性态样中，本揭露涉及半导体装置。半导体装置包括基板；在基板上且环绕栅极沟槽的第一介电层；在栅极沟槽的底部及侧壁上的栅极介电层；及在栅极沟槽中的栅极介电层上的栅极功函数层，其中栅极功函数层的一顶表面低于第一介电层的一顶表面。半导体装置更包括填入栅极沟槽中的第一间隔及第二间隔的金属层，其中第一间隔是由栅极功函数层环绕且第二间隔在栅极功函数层的顶表面与第一介电层的顶表面之间。在一些实例中，上述讨论的装置更包含一栅极间隔物，以作为栅极沟槽的此等侧壁。在一些实例中，上述讨论的装置中，栅极介电层的一顶表面低于第一介电层的顶表面，且金属层填入一第三间隔，第三间隔位于栅极介电层的顶表面与第一介电层的顶表面之间。在一些实例中，上述讨论的装置中，栅极介电层包含一高介电常数介电材料，且金属层包含以下其中的一者：铝(Al)、钨(W)、铜(Cu)及钴(Co)。在一些实例中，上述讨论的装置更包含，与金属层直接接触的一栅极接触件，栅极接触件不与栅极功函数层直接接触。
前述内容概述若干实施例的特征以使得一般技术者可较佳地理解本揭露的态样。一般技术者应理解，其可容易地使用本揭露作为设计或修改其他制程及结构的基础用于进行本文中所介绍的实施例的相同的目的及/或达成相同的优点。一般技术者亦应意识到，此等等效构建不偏离本揭露的精神及范畴，且其可在本文中进行各种变化、替代及修饰而不偏离本揭露的精神及范畴。

Claims (10)

1.一种形成半导体装置的方法，其特征在于，包含：
接收一装置，该装置具有一基板及一第一介电层，该第一介电层位在该基板上，且该第一介电层环绕一栅极沟槽；
沉积一栅极介电层于该栅极沟槽中；
沉积一栅极功函数层于该栅极沟槽中且在该栅极介电层上；
形成一硬遮罩层于一间隔中，该间隔位在该栅极沟槽中且由该栅极功函数层所环绕；
使该栅极功函数层凹陷以使得该栅极沟槽中的该栅极功函数层的一顶表面在该第一介电层的一顶表面下方；
在使该栅极功函数层凹陷之后，移除该栅极沟槽中的该硬遮罩层；以及
在移除该硬遮罩层之后，沉积一金属层于该栅极沟槽中。
2.根据权利要求1所述的方法，其特征在于，更包含：
在沉积该金属层之前，使该栅极介电层凹陷以使得该栅极沟槽中的该栅极介电层的一顶表面在该第一介电层的该顶表面下方。
3.根据权利要求1所述的方法，其特征在于，更包含：
形成一栅极接触件于该金属层上，且与该金属层电连接。
4.根据权利要求1所述的方法，其中使该栅极功函数层凹陷更使该栅极介电层凹陷以使得该栅极沟槽中的该栅极介电层的一顶表面在该第一介电层的该顶表面下方。
5.一种形成半导体装置的方法，其特征在于，包含：
接收一装置，该装置具有一基板、一栅极间隔物及一第一介电层，该栅极间隔物在该基板上且提供一栅极沟槽，该第一介电层在该基板上且环绕该栅极间隔物；
沉积一栅极介电层于该栅极沟槽的一底部及多个侧壁上；
沉积一栅极功函数层于该栅极沟槽中且在该栅极介电层上；
形成一硬遮罩层于该基板上且填入由该栅极功函数层所环绕的一间隔；
蚀刻该硬遮罩层以使得该栅极沟槽中的该硬遮罩层的一顶表面在该第一介电层的一顶表面下方；
蚀刻该栅极功函数层以使得该栅极沟槽中的该栅极功函数层的一顶表面在该第一介电层的一顶表面下方；
蚀刻该栅极介电层以使得该栅极沟槽中的该栅极介电层的一顶表面在该第一介电层的一顶表面下方；
移除该栅极沟槽中的该硬遮罩层，从而提供由该栅极功函数层环绕的一第一间隔及在该栅极功函数层及该栅极介电层的该各别顶表面与该第一介电层的该顶表面之间的第二间隔；以及
填入一金属层于该第一间隔及该第二间隔中。
6.根据权利要求5所述的方法，其特征在于，该硬遮罩层的该蚀刻及该硬遮罩层的该移除中的每一者均包括一选择性蚀刻制程，该选择性蚀刻制程经调适以蚀刻该硬遮罩层，同时使该栅极间隔物、该第一介电层、该栅极介电层及该栅极功函数层保持实质上不变。
7.根据权利要求5所述的方法，其特征在于，蚀刻该栅极功函数层包括一选择性蚀刻制程，该选择性蚀刻制程经调适以蚀刻该栅极功函数层同时使该栅极间隔物、该第一介电层及该硬遮罩层保持实质上不变。
8.一种半导体装置，其特征在于，包含：
一基板；
一第一介电层，位在该基板上且环绕一栅极沟槽；
一栅极介电层，位在该栅极沟槽的一底部及多个侧壁上；
一栅极功函数层位在该栅极介电层上且在该栅极沟槽中，其中该栅极功函数层的一顶表面低于该第一介电层的一顶表面；以及
一金属层，填入该栅极沟槽中的一第一间隔及一第二间隔，其特征在于，该第一间隔是由该栅极功函数层环绕且该第二间隔在该栅极功函数层的该顶表面与该第一介电层的该顶表面之间。
9.根据权利要求8所述的半导体装置，其特征在于，更包含一栅极间隔物，以作为该栅极沟槽的该些侧壁。
10.根据权利要求8所述的半导体装置，其特征在于，该栅极介电层的一顶表面低于该第一介电层的该顶表面，且该金属层填入一第三间隔，该第三间隔位于该栅极介电层的该顶表面与该第一介电层的该顶表面之间。
CN201710061615.9A 2016-01-29 2017-01-26 半导体装置与形成半导体装置的方法 Pending CN107026194A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110437210.7A CN113140625A (zh) 2016-01-29 2017-01-26 形成半导体装置的方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662288507P 2016-01-29 2016-01-29
US62/288,507 2016-01-29
US15/287,509 US10283605B2 (en) 2016-01-29 2016-10-06 Self-aligned metal gate etch back process and device
US15/287,509 2016-10-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202110437210.7A Division CN113140625A (zh) 2016-01-29 2017-01-26 形成半导体装置的方法

Publications (1)

Publication Number Publication Date
CN107026194A true CN107026194A (zh) 2017-08-08

Family

ID=59387054

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201710061615.9A Pending CN107026194A (zh) 2016-01-29 2017-01-26 半导体装置与形成半导体装置的方法
CN202110437210.7A Pending CN113140625A (zh) 2016-01-29 2017-01-26 形成半导体装置的方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202110437210.7A Pending CN113140625A (zh) 2016-01-29 2017-01-26 形成半导体装置的方法

Country Status (4)

Country Link
US (2) US10283605B2 (zh)
KR (2) KR101951088B1 (zh)
CN (2) CN107026194A (zh)
TW (1) TWI648772B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111293118A (zh) * 2018-12-10 2020-06-16 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283605B2 (en) * 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device
CN107301950A (zh) 2016-04-14 2017-10-27 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US10629749B2 (en) 2017-11-30 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of treating interfacial layer on silicon germanium
KR102521897B1 (ko) 2017-12-26 2023-04-18 삼성디스플레이 주식회사 표시 패널, 표시 장치 및 표시 패널 제조 방법
US10361200B1 (en) 2018-03-07 2019-07-23 International Business Machines Corporation Vertical fin field effect transistor with integral U-shaped electrical gate connection
US10529823B2 (en) 2018-05-29 2020-01-07 International Business Machines Corporation Method of manufacturing a semiconductor device having a metal gate with different lateral widths between spacers
US11107907B2 (en) * 2018-10-30 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for manufacturing the same
US20210408235A1 (en) * 2020-06-25 2021-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with silicide gate fill structure
TWI833658B (zh) * 2023-03-10 2024-02-21 南亞科技股份有限公司 具有封蓋層的半導體元件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104061A (zh) * 2009-12-21 2011-06-22 台湾积体电路制造股份有限公司 用于场效应晶体管的栅极电极以及场效应晶体管
US20130015510A1 (en) * 2011-07-11 2013-01-17 Jiang Yan Transistor, Semiconductor Device, and Method for Manufacturing the Same
CN104299897A (zh) * 2013-07-17 2015-01-21 格罗方德半导体公司 具改善阈值电压表现的取代金属栅极的集成电路及其制法
CN104810368A (zh) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos晶体管及其形成方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
TWI345833B (en) * 2007-11-23 2011-07-21 Inotera Memories Inc Method of fabricating a semiconductor device
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US8080302B2 (en) 2008-09-19 2011-12-20 Macneil Ip Llc All vehicle mats
CA2732394C (en) 2008-10-20 2014-05-13 Research In Motion Limited Method and system for rendering of labels
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8629511B2 (en) * 2012-05-15 2014-01-14 International Business Machines Corporation Mask free protection of work function material portions in wide replacement gate electrodes
CN103545215B (zh) 2012-07-17 2016-06-29 中国科学院微电子研究所 半导体器件及其制造方法
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9018711B1 (en) * 2013-10-17 2015-04-28 Globalfoundries Inc. Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
US9306032B2 (en) * 2013-10-25 2016-04-05 United Microelectronics Corp. Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
KR102055333B1 (ko) 2014-01-29 2020-01-22 에스케이하이닉스 주식회사 듀얼일함수 매립게이트형 트랜지스터 및 그 제조 방법, 그를 구비한 전자장치
US10283605B2 (en) * 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104061A (zh) * 2009-12-21 2011-06-22 台湾积体电路制造股份有限公司 用于场效应晶体管的栅极电极以及场效应晶体管
US20130015510A1 (en) * 2011-07-11 2013-01-17 Jiang Yan Transistor, Semiconductor Device, and Method for Manufacturing the Same
CN104299897A (zh) * 2013-07-17 2015-01-21 格罗方德半导体公司 具改善阈值电压表现的取代金属栅极的集成电路及其制法
CN104810368A (zh) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos晶体管及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111293118A (zh) * 2018-12-10 2020-06-16 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US10811506B2 (en) 2020-10-20
TWI648772B (zh) 2019-01-21
US20190259849A1 (en) 2019-08-22
KR20180097174A (ko) 2018-08-30
US10283605B2 (en) 2019-05-07
KR20170091005A (ko) 2017-08-08
TW201737324A (zh) 2017-10-16
CN113140625A (zh) 2021-07-20
KR101951088B1 (ko) 2019-02-21
US20170222005A1 (en) 2017-08-03

Similar Documents

Publication Publication Date Title
US11349015B2 (en) Dual metal via for contact resistance reduction
US11721544B2 (en) Cut metal gate process for reducing transistor spacing
US10685873B2 (en) Etch stop layer for semiconductor devices
CN107026194A (zh) 半导体装置与形成半导体装置的方法
US10276676B1 (en) Methods of forming metal gate isolation
CN109585446B (zh) 半导体装置
CN110875189A (zh) 半导体装置的形成方法
US20220352037A1 (en) Methods Of Forming Metal Gate Spacer
US20210384352A1 (en) Methods of Forming Contact Features in Field-Effect Transistors
US11244899B2 (en) Butted contacts and methods of fabricating the same in semiconductor devices
US20220359686A1 (en) Butted Contacts And Methods Of Fabricating The Same In Semiconductor Devices
US12002756B2 (en) Butted contacts and methods of fabricating the same in semiconductor devices
US11769770B2 (en) Methods of forming a semiconductor device having an air spacer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170808