CN108231790A - 显示装置及其制造方法 - Google Patents

显示装置及其制造方法 Download PDF

Info

Publication number
CN108231790A
CN108231790A CN201611147363.3A CN201611147363A CN108231790A CN 108231790 A CN108231790 A CN 108231790A CN 201611147363 A CN201611147363 A CN 201611147363A CN 108231790 A CN108231790 A CN 108231790A
Authority
CN
China
Prior art keywords
display device
polysilicon
data line
pixel
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611147363.3A
Other languages
English (en)
Other versions
CN108231790B (zh
Inventor
宋艳芹
胡思明
杨楠
张九占
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan New Flat Panel Display Technology Center Co Ltd
Kunshan Govisionox Optoelectronics Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
Original Assignee
Kunshan New Flat Panel Display Technology Center Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CN201611147363.3A priority Critical patent/CN108231790B/zh
Application filed by Kunshan New Flat Panel Display Technology Center Co Ltd, Kunshan Guoxian Photoelectric Co Ltd filed Critical Kunshan New Flat Panel Display Technology Center Co Ltd
Priority to EP17881307.7A priority patent/EP3528286B1/en
Priority to US16/313,619 priority patent/US10797089B2/en
Priority to KR1020197012509A priority patent/KR102174662B1/ko
Priority to PCT/CN2017/115604 priority patent/WO2018108069A1/zh
Priority to JP2018567934A priority patent/JP6758427B2/ja
Priority to TW106143757A priority patent/TWI663718B/zh
Publication of CN108231790A publication Critical patent/CN108231790A/zh
Application granted granted Critical
Publication of CN108231790B publication Critical patent/CN108231790B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Abstract

本发明提供了一种显示装置及其制造方法，其中，所述显示装置的制造方法包括：提供一衬底；在所述衬底上形成一多晶硅层；图形化所述多晶硅层以形成多个多晶硅区块；对所述多个多晶硅区块进行离子注入；在所述多个多晶硅区块上形成一栅极绝缘层；在所述栅极绝缘层上形成一第一导电层；以及图形化所述第一导电层以形成多条数据线，所述多条数据线的部分线段与所述多个多晶硅区块的位置交叠以形成多个补偿电容。在本发明实施例提供的显示装置及其制造方法中，利用掺杂有杂质的多晶硅层与第一导电层的交叠区域形成补偿电容，以减少所述补偿电容的占用面积，从而避免扫描线无法与GIP电路连接的问题。

Description

显示装置及其制造方法
技术领域
本发明涉及显示技术领域，特别涉及一种显示装置及其制造方法。
背景技术
近年来，随着信息技术、无线移动通讯和信息家电的快速发展与应用，人们对电子产品的依赖性与日俱增，更带来各种显示技术及显示装置的蓬勃发展。显示装置具有完全平面化、轻、薄、省电等特点，因此得到了广泛的应用。
为了降低显示装置的制造成本并藉此实现窄边框的目的，在制造过程中通常采用GIP(Gate in Panel，门面板)技术，直接将栅极驱动电路(即GIP电路)集成于显示屏上。显示屏通常包括用于显示图像的显示区域和围绕显示区域的非显示区域，所述显示区域中设置有多条扫描线和多条数据线，所述扫描线和数据线交叉限定出多个呈矩阵排列的像素单元，所述非显示区域中设置有GIP电路，所述GIP电路通过扫描线与所述像素单元连接。
随着显示技术的发展，显示屏的形状也向多元化方向发展，除了传统的矩形之外，还有多边形、圆形等形状。例如，手表采用圆形的显示屏。在矩形的显示屏中，每行像素的个数以及每列像素的个数通常是一致的。而在多边形或圆形的显示屏中，每行像素的个数以及每列像素的个数是不一致的。
由于每列像素个数不一致，因此数据线上的寄生电容不一致，进而造成显示装置出现显示不均现象。为此，需要在显示装置中设置补偿电容，利用所述补偿电容对寄生电容进行补偿，才能获得显示均匀的图像。然而，现有的显示装置中补偿电容的占用面积较大，导致扫描线无法与GIP电路连接，不利于的窄边框实现。
基此，如何解决现有的显示装置由于补偿电容的占用面积过大，导致扫描线无法与GIP电路连接的问题，成了本领域技术人员亟待解决的一个技术问题。
发明内容
本发明的目的在于提供一种显示装置及其制造方法，以解决现有技术中显示装置由于补偿电容的占用面积过大，导致扫描线无法与GIP电路连接的问题。
为解决上述问题，本发明提供一种显示装置的制造方法，所述显示装置的制造方法包括：
提供一衬底；
在所述衬底上形成一多晶硅层；
图形化所述多晶硅层以形成多个多晶硅区块；
对所述多个多晶硅区块进行离子注入；
在所述多个多晶硅区块上形成一栅极绝缘层；
在所述栅极绝缘层上形成一第一导电层；以及
图形化所述第一导电层以形成多条数据线，所述多条数据线的部分线段与所述多个多晶硅区块的位置交叠以形成多个补偿电容。
可选的，在所述的显示装置的制造方法中，在图形化所述多晶硅层以形成多个多晶硅区块的同时，还包括：图形化所述多晶硅层以形成多个像素电容的第一极板以及多个薄膜晶体管的源极和漏极。
可选的，在所述的显示装置的制造方法中，在对所述多个多晶硅区块进行离子注入的同时，还包括：对所述多个像素电容的第一极板进行离子注入。
可选的，在所述的显示装置的制造方法中，在图形化所述第一导电层以形成多条数据线的同时，还包括：图形化所述第一导电层以形成所述多个像素电容的第二极板以及所述多个薄膜晶体管的栅极。
可选的，在所述的显示装置的制造方法中，在图形化所述第一导电层以形成多条数据线之后，还包括：在图形化的第一导电层上形成一第二导电层，并图形化所述第二导电层以形成多条像素连线和多条电源线。
可选的，在所述的显示装置的制造方法中，在图形化的第一导电层上形成第二导电层之前，在图形化所述第一导电层以形成多条数据线之后，还包括：在所述多个多晶硅区块上形成多个接触孔，所述接触孔用于连接所述电源线和多晶硅区块。
可选的，在所述的显示装置的制造方法中，根据所述数据线所连接的像素单元的数量调整所述数据线与所述多晶硅区块的交叠面积。
可选的，在所述的显示装置的制造方法中，若所述数据线所连接的像素单元的数量减少，则增加所述数据线与所述多晶硅区块的交叠面积；若所述数据线所连接的像素单元的数量增加，则减少所述数据线与所述多晶硅区块的交叠面积。
相应的，本发明还提供了一种显示装置，所述显示装置包括：衬底；依次形成于所述衬底上的图形化的多晶硅层、图形化的栅极绝缘层和图形化的第一导电层，所述图形化的多晶硅层包括多个多晶硅区块，所述图形化的第一导电层包括多条数据线，所述数据线的部分线段与所述多晶硅区块位置交叠而形成补偿电容。
可选的，在所述的显示装置中，还包括：多个像素单元，每个像素单元均包括薄膜晶体管和像素电容，所述薄膜晶体管的源极和漏极、所述像素电容的第一极板与所述多晶硅区块在同一工艺中制作，所述薄膜晶体管的栅极、所述像素电容的第二极板与所述数据线在同一工艺中制作。
可选的，在所述的显示装置中，还包括：多个测试电路，所述数据线的一端与所述像素单元连接，所述数据线的另一端与所述测试电路连接。
可选的，在所述的显示装置中，还包括：多个GIP电路、像素连线和电源线，所述像素连线与所述电源线设置为同层同材质；所述电源线与所述像素单元连接，用于向所述像素单元提供电源信号，所述像素连线用于连接所述像素单元和GIP电路。
可选的，在所述的显示装置中，所述补偿电容用于补偿所述数据线的寄生电容，所述补偿电容的电容补偿值与所述数据线与多晶硅区块的交叠面积成正比。
可选的，在所述的显示装置中，所述数据线与多晶硅区块的交叠面积与所述数据线所连接的像素单元的数量相关。
综上所述，在本发明提供的显示装置及其制造方法中，利用掺杂有杂质的多晶硅层与第一导电层的交叠区域形成补偿电容，以减少所述补偿电容的占用面积，从而避免扫描线无法与GIP电路连接的问题。
附图说明
图1是本发明实施例的显示装置的制造方法中步骤一对应的结构示意图；
图2是本发明实施例的显示装置的制造方法中步骤三对应的结构示意图；
图3是本发明实施例的显示装置的制造方法中步骤六对应的结构示意图；
图4是本发明实施例的显示装置的制造方法中接触孔工艺完成时的结构示意图；
图5是本发明实施例的显示装置的制造方法中第二导电层图形化完成时的结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出一种显示装置及其制造方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请结合参考图1至图5，所述显示装置的制造方法包括：
步骤一：提供一衬底100；
步骤二：在所述衬底100上形成一多晶硅层；
步骤三：图形化所述多晶硅层以形成多个多晶硅区块110；
步骤四：对所述多个多晶硅区块110进行离子注入；
步骤五：在所述多个多晶硅区块110上形成一栅极绝缘层(图中未示出)；
步骤六：在所述栅极绝缘层上形成一第一导电层；
步骤七：图形化所述第一导电层以形成多条数据线120，所述数据线120的部分线段与所述多晶硅区块110的位置交叠以形成补偿电容。
具体的，首先，如图1所示，提供一衬底100，所述衬底100包括显示区和围绕于所述显示区的非显示区，所述显示区用于设置像素阵列，所述像素阵列包括多个呈阵列方式排列的像素单元101，每个像素单元101包括像素电容和薄膜晶体管(图中未示出)，所述非显示区用于设置GIP电路140和测试电路150。
接着，如图2所示，在所述衬底100上形成多晶硅层，并通过刻蚀工艺对其进行图形化，以形成所述像素电容的第一极板(图中未示出)、所述薄膜晶体管的源极、漏极(图中未示出)和多个多晶硅区块110。
此后，采用硼离子或磷离子对所述像素电容的第一极板和多晶硅区块110进行离子注入工艺，通过离子注入工艺使得所述第一极板和多晶硅区块110均掺杂有杂质，由此提高所述第一极板和多晶硅区块110的导电性。
然后，在图形化的多晶硅层上形成一栅极绝缘层，并图形化所述栅极绝缘层。
之后，如图3所示，在图形化的栅极绝缘层上形成第一导电层，并通过刻蚀工艺对其进行图形化，以形成所述像素电容的第二极板(图中未示出)、所述薄膜晶体管的栅极(图中未示出)和多条数据线120，所述数据线120的一端与像素单元101连接，所述数据线120的另一端与测试电路150连接，且所述数据线120的部分线段与所述多晶硅区块110的位置交叠以形成补偿电容。
其中，所述补偿电容的电容补偿值与数据线120与多晶硅区块110的交叠面积成正比。
本实施例中，所述数据线120与多晶硅区块110的交叠面积根据所述数据线120所连接的像素单元101的数量进行调整。其中，所述数据线120所连接的像素单元101的数量越少，意味着所述数据线120上的寄生电容越小，因此所述数据线120对应的补偿电容的电容补偿值要求越高，即所述数据线120与多晶硅区块110的交叠面积要求越大。反之，所述数据线120所连接的像素单元101的数量越多，意味着所述数据线120上的寄生电容越大，因此所述数据线120对应的补偿电容的电容补偿值要求越低，即所述数据线120与多晶硅区块110的交叠面积要求越小。
在所述显示装置的制造过程中，若所述数据线120所连接的像素单元101的数量减少，则增加所述数据线120与多晶硅区块110的交叠面积；若所述数据线所连接的像素单元的数量增加，则减少所述数据线120与多晶硅区块110的交叠面积。
此后，如图4所示，在所述多个多晶硅区块110上进行接触孔工艺以形成多个接触孔110a，所述接触孔110a的底部暴露出所述多个多晶硅区块110。
最后，如图5所示，在图形化的第一导电层上形成第二导电层，并通过刻蚀工艺对其进行图形化，以形成电源线131和像素连线132，所述电源线131通过所述接触孔110a与所述多晶硅区块110连接，所述像素连线132用于连接像素单元与GIP电路140。
其中，所述第一导电层和第二导电层采用的材料，根据产品的实际要求进行选择，在此不做限定。所述第一导电层和第二导电层可以采用氧化铟锡(ITO)、铟锌氧化物(IZO)、掺锆的氧化锌(ZZO)、掺氟的氧化锡(FTO)或纳米银等透明导电材料，也可以采用银(Ag)、铝(Al)、钨、银合金、铝合金等非透明的导电材料。
至此，形成所述显示装置10。在所述显示装置10中，补偿电容的一侧极板由导电层构成，另一侧极板由多晶硅区块110构成。在传统的显示装置中，补偿电容的两侧极板通常都是由导电层构成的。
在本实施例提供的显示装置的制造方法中，利用所述多晶硅区块110构成补偿电容的一侧极板，不但能够缩小补偿电容占用的面积，而且制作工艺更加简单，仅采用2-Metal工艺(即形成两层金属层工艺)就能够完成显示装置的制作，因此不必采用3-Metal工艺(即形成三层金属层工艺)。
相应的，本发明还提供一种显示装置。请继续参考图5，所述显示装置10包括：衬底100；依次形成于所述衬底100上的图形化的多晶硅层、图形化的栅极绝缘层和图形化的第一导电层，所述图形化的多晶硅层包括多个多晶硅区块110，所述图形化的第一导电层包括多条数据线120，所述数据线120的部分线段与所述多晶硅区块110位置交叠而形成补偿电容。
具体的，所述显示装置10包括多条用于提供扫描信号的扫描线(图中未示出)和多条用于提供数据信号的数据线120，所述扫描线和数据线120交叉限定出多个呈矩阵排列的像素单元101，每个像素单元101均包括像素电容(图中未示出)和薄膜晶体管(图中未示出)。其中，所述像素电容的第二极板、所述薄膜晶体管的栅极与所述数据线120在同一工艺中制成，所述像素电容的第一极板、所述薄膜晶体管的源极和漏极与所述多晶硅区块110在同一工艺中制成。
请继续参考图5，图形化的多晶硅层与图形化的第一导电层部分位置交叠(即所述数据线120的部分线段与所述多晶硅区块110位置交叠)，位于交叠区域的多晶硅层与第一导电层分别构成补偿电容的两侧极板，所述多晶硅层与第一导电层之间的栅极绝缘层构成所述补偿电容的绝缘介质层。
本实施例中，所述补偿电容用于补偿所述数据线120的寄生电容，所述补偿电容的电容补偿值与所述数据线120与多晶硅区块110的交叠面积成正比。其中，所述数据线120与多晶硅区块110的交叠面积与所述数据线120所连接的像素单元101的数量相关。所述数据线120所连接的像素单元101的数量越多，则所述数据线120与多晶硅区块110的交叠面积越小，与所述数据线120相应的补偿电容的电容补偿值越小。所述数据线120所连接的像素单元101的数量越少，则所述数据线120与多晶硅区块110的交叠面积越大，与所述数据线120相应的补偿电容的电容补偿值越大。
当所述数据线120向所述像素单元101提供数据信号时，所述数据线120传输的数据信号同时施加到所述补偿电容的一侧极板上，对所述数据线120上的寄生电容进行补偿。由于，所述补偿电容的电容补偿值是根据所述数据线120所连接的像素单元101的数量设置的，因此即使所述显示装置10每列像素单元的个数不一致，也能够有效地补偿数据线120上的寄生电容，不会出现显示不均现象。
请结合参考图4和图5，所述显示装置10还包括多条电源线131，所述电源线131的一端与所述像素单元101连接，用于向所述像素单元101提供电源信号，所述多晶硅区块110上设置有多个接触孔110a，述电源线131通过所述接触孔110a与所述多晶硅区块110连接。
请继续参考图5，所述显示装置10还包括像素连线132和GIP电路140，所述像素连线用于连接所述像素单元101和GIP电路140。本实施例中，所述像素连线132和所述电源线131在同一工艺中制成。
请继续参考图5，所述显示装置10还包括测试电路150，所述数据线120的一端与所述像素单元101连接，所述数据线120的另一端与所述测试电路150连接，所述测试电路150用于提供测试信号，所述测试信号用于判断所述显示装置10是否正常显示。
本实施例提供的显示装置可以是液晶显示(LCD)装置、等离子体显示(PDP)装置、真空荧光显示(VFD)装置、有机发光显示(OLED)装置、柔性显示装置或者其他类型的显示装置，具体类型在此不作限制。
综上，在本发明实施例提供的显示装置及其制造方法中，利用掺杂有杂质的多晶硅层与第一导电层的交叠区域形成补偿电容，以减少所述补偿电容的占用面积，从而避免扫描线无法与GIP电路连接的问题。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (14)

1.一种显示装置的制造方法，其特征在于，包括：
提供一衬底；
在所述衬底上形成一多晶硅层；
图形化所述多晶硅层以形成多个多晶硅区块；
对所述多个多晶硅区块进行离子注入；
在所述多个多晶硅区块上形成一栅极绝缘层；
在所述栅极绝缘层上形成一第一导电层；以及
图形化所述第一导电层以形成多条数据线，所述多条数据线的部分线段与所述多个多晶硅区块的位置交叠以形成多个补偿电容。
2.如权利要求1所述的显示装置的制造方法，其特征在于，在图形化所述多晶硅层以形成多个多晶硅区块的同时，还包括：图形化所述多晶硅层以形成多个像素电容的第一极板以及多个薄膜晶体管的源极和漏极。
3.如权利要求2所述的显示装置的制造方法，其特征在于，在对所述多个多晶硅区块进行离子注入的同时，还包括：对所述多个像素电容的第一极板进行离子注入。
4.如权利要求2所述的显示装置的制造方法，其特征在于，在图形化所述第一导电层以形成多条数据线的同时，还包括：图形化所述第一导电层以形成所述多个像素电容的第二极板以及所述多个薄膜晶体管的栅极。
5.如权利要求1所述的显示装置的制造方法，其特征在于，在图形化所述第一导电层以形成多条数据线之后，还包括：在图形化的第一导电层上形成一第二导电层，并图形化所述第二导电层以形成多条像素连线和多条电源线。
6.如权利要求5所述的显示装置的制造方法，其特征在于，在图形化的第一导电层上形成第二导电层之前，在图形化所述第一导电层以形成多条数据线之后，还包括：在所述多个多晶硅区块上形成多个接触孔，所述接触孔用于连接所述电源线和多晶硅区块。
7.如权利要求1所述的显示装置的制造方法，其特征在于，根据所述数据线所连接的像素单元的数量调整所述数据线与所述多晶硅区块的交叠面积。
8.如权利要求7所述的显示装置的制造方法，其特征在于，若所述数据线所连接的像素单元的数量减少，则增加所述数据线与所述多晶硅区块的交叠面积；若所述数据线所连接的像素单元的数量增加，则减少所述数据线与所述多晶硅区块的交叠面积。
9.一种采用如权利要求1至8中任一项所述的显示装置的制造方法制成的显示装置，其特征在于，包括：衬底；依次形成于所述衬底上的图形化的多晶硅层、图形化的栅极绝缘层和图形化的第一导电层，所述图形化的多晶硅层包括多个掺杂有杂质的多晶硅区块，所述图形化的第一导电层包括多条数据线，所述数据线的部分线段与所述多晶硅区块位置交叠而形成补偿电容。
10.如权利要求9所述的显示装置，其特征在于，还包括：多个像素单元，每个像素单元均包括薄膜晶体管和像素电容，所述薄膜晶体管的源极和漏极、所述像素电容的第一极板与所述多晶硅区块在同一工艺中制作，所述薄膜晶体管的栅极、所述像素电容的第二极板与所述数据线在同一工艺中制作。
11.如权利要求10所述的显示装置，其特征在于，还包括：多个测试电路，所述数据线的一端与所述像素单元连接，所述数据线的另一端与所述测试电路连接。
12.如权利要求10所述的显示装置，其特征在于，还包括：多个GIP电路、像素连线和电源线，所述像素连线与所述电源线设置为同层同材质；所述电源线与所述像素单元连接，用于向所述像素单元提供电源信号，所述像素连线用于连接所述像素单元和GIP电路。
13.如权利要求9所述的显示装置，其特征在于，所述补偿电容用于补偿所述数据线的寄生电容，所述补偿电容的电容补偿值与所述数据线与多晶硅区块的交叠面积成正比。
14.如权利要求13所述的显示装置，其特征在于，所述数据线与多晶硅区块的交叠面积与所述数据线所连接的像素单元的数量相关。
CN201611147363.3A 2016-12-13 2016-12-13 显示装置及其制造方法 Active CN108231790B (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN201611147363.3A CN108231790B (zh) 2016-12-13 2016-12-13 显示装置及其制造方法
US16/313,619 US10797089B2 (en) 2016-12-13 2017-12-12 Display device having compensating capacitor and method of manufacturing the same
KR1020197012509A KR102174662B1 (ko) 2016-12-13 2017-12-12 디스플레이 장치 및 이를 위한 제조 방법
PCT/CN2017/115604 WO2018108069A1 (zh) 2016-12-13 2017-12-12 显示装置及其制造方法
EP17881307.7A EP3528286B1 (en) 2016-12-13 2017-12-12 Display device and manufacturing method therefor
JP2018567934A JP6758427B2 (ja) 2016-12-13 2017-12-12 ディスプレイデバイスおよびその製造方法
TW106143757A TWI663718B (zh) 2016-12-13 2017-12-13 顯示裝置及其製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611147363.3A CN108231790B (zh) 2016-12-13 2016-12-13 显示装置及其制造方法

Publications (2)

Publication Number Publication Date
CN108231790A true CN108231790A (zh) 2018-06-29
CN108231790B CN108231790B (zh) 2019-09-17

Family

ID=62557951

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611147363.3A Active CN108231790B (zh) 2016-12-13 2016-12-13 显示装置及其制造方法

Country Status (7)

Country Link
US (1) US10797089B2 (zh)
EP (1) EP3528286B1 (zh)
JP (1) JP6758427B2 (zh)
KR (1) KR102174662B1 (zh)
CN (1) CN108231790B (zh)
TW (1) TWI663718B (zh)
WO (1) WO2018108069A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103190A1 (zh) * 2018-11-21 2020-05-28 惠科股份有限公司 一种显示装置的驱动电路和显示装置
WO2022095665A1 (zh) * 2020-11-09 2022-05-12 京东方科技集团股份有限公司 显示基板和显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1628263A (zh) * 2002-06-07 2005-06-15 三星电子株式会社 薄膜晶体管阵列面板
CN102368499A (zh) * 2011-10-27 2012-03-07 深圳市华星光电技术有限公司 Tft阵列基板及液晶面板
CN102569343A (zh) * 2010-12-14 2012-07-11 三星移动显示器株式会社 有机发光显示装置及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4096585B2 (ja) * 2001-03-19 2008-06-04 セイコーエプソン株式会社 表示装置の製造方法及び表示装置並びに電子機器
KR20060041949A (ko) 2004-04-15 2006-05-12 미쓰비시덴키 가부시키가이샤 오프셋 보상기능을 갖는 구동회로 및 그것을 사용한 액정표시장치
KR100662989B1 (ko) * 2004-08-20 2006-12-28 삼성에스디아이 주식회사 검사회로부를 구비하는 표시장치
KR100647774B1 (ko) * 2004-11-04 2006-11-23 엘지.필립스 엘시디 주식회사 폴리 실리콘형 박막 트랜지스터 기판 및 제조 방법
US8363191B2 (en) * 2006-11-21 2013-01-29 Sharp Kabushiki Kaisha Active matrix substrate, display panel and display device
CN101286515A (zh) 2007-04-13 2008-10-15 群康科技(深圳)有限公司 薄膜晶体管基板及其制造方法
CN101779227B (zh) 2007-10-24 2012-03-28 夏普株式会社 显示面板和显示装置
JP2010249955A (ja) 2009-04-13 2010-11-04 Global Oled Technology Llc 表示装置
KR101825643B1 (ko) * 2011-01-10 2018-02-06 삼성디스플레이 주식회사 유기 발광 표시 장치
JP5997958B2 (ja) 2012-07-23 2016-09-28 株式会社ジャパンディスプレイ 表示装置及びアレイ基板
CN103296030B (zh) * 2012-07-25 2015-12-09 上海天马微电子有限公司 Tft-lcd阵列基板
JP6196456B2 (ja) 2013-04-01 2017-09-13 シナプティクス・ジャパン合同会社 表示装置及びソースドライバｉｃ
CN103915431B (zh) 2013-06-17 2017-10-20 上海天马微电子有限公司 一种tft阵列基板、显示装置及阵列基板制作方法
CN103325688A (zh) 2013-06-17 2013-09-25 深圳市华星光电技术有限公司 薄膜晶体管的沟道形成方法及补偿电路
US9190005B2 (en) * 2014-03-05 2015-11-17 Innolux Corporation Display panel
JP2015227974A (ja) 2014-06-02 2015-12-17 株式会社ジャパンディスプレイ 表示装置
CN104064601B (zh) 2014-06-30 2017-12-26 上海天马微电子有限公司 Tft、tft阵列基板及其制造方法、显示面板、显示装置
US10283040B2 (en) * 2015-02-03 2019-05-07 Sharp Kabushiki Kaisha Data signal line drive circuit, data signal line drive method and display device
KR102293411B1 (ko) * 2015-05-08 2021-08-25 삼성디스플레이 주식회사 비사각형 디스플레이
KR102507151B1 (ko) * 2015-08-27 2023-03-08 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 표시 장치 및 그 제조 방법
KR20170028464A (ko) * 2015-09-03 2017-03-14 삼성디스플레이 주식회사 표시 장치
CN105204248A (zh) 2015-10-10 2015-12-30 重庆京东方光电科技有限公司 一种阵列基板及显示装置
CN105513528B (zh) 2016-02-04 2018-06-22 京东方科技集团股份有限公司 电容补偿电路、显示基板、显示装置及电容补偿方法
KR102503164B1 (ko) * 2016-04-05 2023-02-24 삼성디스플레이 주식회사 표시 패널 및 이의 제조 방법
CN106449651B (zh) * 2016-09-12 2019-05-21 厦门天马微电子有限公司 像素结构及显示装置
KR102430809B1 (ko) * 2017-09-29 2022-08-09 엘지디스플레이 주식회사 양면 디스플레이

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1628263A (zh) * 2002-06-07 2005-06-15 三星电子株式会社 薄膜晶体管阵列面板
CN102569343A (zh) * 2010-12-14 2012-07-11 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN102368499A (zh) * 2011-10-27 2012-03-07 深圳市华星光电技术有限公司 Tft阵列基板及液晶面板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020103190A1 (zh) * 2018-11-21 2020-05-28 惠科股份有限公司 一种显示装置的驱动电路和显示装置
US11361724B2 (en) 2018-11-21 2022-06-14 HKC Corporation Limited Drive circuit of display device, and display device
WO2022095665A1 (zh) * 2020-11-09 2022-05-12 京东方科技集团股份有限公司 显示基板和显示装置
US11943981B2 (en) 2020-11-09 2024-03-26 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and display apparatus

Also Published As

Publication number Publication date
US10797089B2 (en) 2020-10-06
EP3528286A1 (en) 2019-08-21
EP3528286B1 (en) 2024-03-27
TWI663718B (zh) 2019-06-21
KR102174662B1 (ko) 2020-11-05
US20190326334A1 (en) 2019-10-24
JP2020500321A (ja) 2020-01-09
TW201838159A (zh) 2018-10-16
EP3528286A4 (en) 2019-11-27
CN108231790B (zh) 2019-09-17
JP6758427B2 (ja) 2020-09-23
KR20190054172A (ko) 2019-05-21
WO2018108069A1 (zh) 2018-06-21

Similar Documents

Publication Publication Date Title
US9759966B2 (en) Array substrate and method of manufacturing the same, and display device
WO2019153396A1 (zh) 柔性显示面板及柔性显示装置
CN105068373B (zh) Tft基板结构的制作方法
US20160372490A1 (en) Array substrate and manufacturing method thereof, and display panel
US20220320146A1 (en) Display panel, manufacturing method thereof, and display device
CN100363789C (zh) 液晶显示装置
CN103077944B (zh) 显示装置、阵列基板及其制作方法
CN103488015B (zh) 像素结构及具有此像素结构的显示面板
CN204179080U (zh) 显示装置
CN107946337B (zh) 显示设备
CN103472607A (zh) 显示面板与其制造方法
US20220037615A1 (en) Display substrate, manufacturing method thereof and display panel
US11244990B2 (en) Display control circuit and driving method thereof, display panel and manufacturing and controlling methods thereof
CN105161499A (zh) 一种显示基板及其制作方法和显示装置
CN104216182A (zh) 阵列基板及其制造方法和显示面板
CN110854157A (zh) 一种显示面板及其制作方法、显示装置
CN111403454A (zh) 显示面板
WO2022237017A1 (zh) 显示面板及其制作方法、显示装置
WO2019042011A1 (zh) 阵列基板及其制备方法、驱动方法、显示装置
CN104409462A (zh) 阵列基板及其制造方法、显示装置
GB2564234A (en) Flat display panel and method of manufactoring the same
KR100495701B1 (ko) 유기 전계 발광 표시장치의 제조방법
CN108231790B (zh) 显示装置及其制造方法
US20060012742A1 (en) Driving device for active matrix organic light emitting diode display and manufacturing method thereof
CN100452412C (zh) 像素结构与制造方法及含像素结构的光电装置与制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant