CN106449651B - 像素结构及显示装置 - Google Patents

像素结构及显示装置 Download PDF

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CN106449651B
CN106449651B CN201610816672.9A CN201610816672A CN106449651B CN 106449651 B CN106449651 B CN 106449651B CN 201610816672 A CN201610816672 A CN 201610816672A CN 106449651 B CN106449651 B CN 106449651B
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CN106449651A (zh
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蓝学新
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Tianma Microelectronics Co Ltd
Xiamen Tianma Microelectronics Co Ltd
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Tianma Microelectronics Co Ltd
Xiamen Tianma Microelectronics Co Ltd
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Priority to US15/413,273 priority patent/US20170179165A1/en
Priority to DE102017202467.4A priority patent/DE102017202467A1/de
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    • G02F2202/00—Materials and properties
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    • G02F2202/104—Materials and properties semiconductor poly-Si

Abstract

本申请公开一种像素结构及显示装置。一种像素结构包括：扫描线，所述扫描线具有分支结构；半导体图案，所述半导体图案与所述扫描线和所述分支结构相交，所述半导体图案包括：第一沟道区，位于所述扫描线下方；第二沟道区，位于所述分支结构下方；掺杂区，位于所述第一沟道区和所述第二沟道区两侧，其中，所述第二沟道区的宽度小于所述第一沟道区的宽度。该像素结构可以提升显示屏的显示性能。

Description

像素结构及显示装置
技术领域
本发明涉及液晶显示领域，具体而言，涉及一种像素结构及显示装置。
背景技术
随着显示技术的飞速发展，高PPI(Pixels Per Inch)、甚至超高PPI已经成为一种必然的趋势。图像分辨率一般用PPI(每英寸的像素数目)表示，PPI数值越高，代表显示屏能够以越高的密度(像素数)显示图像。显示屏显示的PPI越高，显示画面的细节就会越丰富，拟真度也就越高。但是，随着屏幕PPI的提高，像素排列越来越紧密，每个像素的尺寸也越来越小，这不仅给器件设计带来巨大挑战，同时也引发诸多令人头疼的难题。
在诸多制约高PPI技术的问题中，充电能力不足是挑战高PPI技术的一个原因。制约高PPI充电能力的因素主要有：液晶面板负载大，像素充电时间短，存在馈通(Feedthrough)电压，像素宽长比受限等，其中馈通这一项对于像素存储电容很小(小于32fF)的高PPI技术至关重要，如图1所示。
降低像素馈通电压的方法有以下几种：减小像素结构中沟道宽度和宽度，减小像素结构中栅极氧化物层电容，降低薄膜晶体管(TFT)液晶屏幕打开和关闭电压的压差，增大像素结构中的存储电容容量等。但是，对于高PPI产品来说，由于每一个像素节距很小，像素结构中的存储电容很难增大；减小像素结构中的沟道宽度或降低TFT液晶屏幕打开和关闭电压的压差意味着充电能力受到进一步压缩；减小像素结构中栅极氧化物层电容意味着膜厚加厚或介电常数减小，这不仅与器件薄小化的趋势相违背，还会使器件开态电流下降，引起充电能力下降；减小像素结构中沟道宽度，这个方法可以降低馈通电压，提高充电能力，但是也会增加栅延迟(Gate delay)，带来面板左右两侧充电能力不同等新问题。
因此，仍需开发能够降低馈通电压的方法和结构。
在所述背景技术部分公开的上述信息仅用于加强对本发明的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本申请提供一种像素结构，能够在不增加栅延迟的情况下降低馈通电压，从而提升器件充电能力，进而提升显示屏的显示性能。
本发明的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本发明的实践而习得。
根据本发明的一方面，提供一种像素结构，包括：扫描线，该扫描线具有分支结构；半导体图案，该半导体图案与扫描线和分支结构相交，半导体图案包括：第一沟道区，对应于扫描线；第二沟道区，对应于分支结构；掺杂区，位于第一沟道区和第二沟道区两侧，其中，第二沟道区的宽度小于第一沟道区的宽度。
在本公开的一种示例性实施例中，分支结构为L形分支。
在本公开的一种示例性实施例中，所述半导体图案包括直线部分，L形分支的第二部分和L形分支的第一部分相交，L形分支的第二部分与半导体图案直线部分垂直相交。
在本公开的一种示例性实施例中，半导体图案包括直线部分，L形分支的第二部分和扫描线与直线部分垂直相交。
在本公开的一种示例性实施例中，分支结构从扫描线垂直延伸。
在本公开的一种示例性实施例中，半导体图案至少包括第一部分和第二部分，第一部分与扫描线垂直相交，第二部分与分支结构垂直相交。
在本公开的一种示例性实施例中，第二沟道区的宽度为第一沟道区的宽度的1/5至4/5。
在本公开的一种示例性实施例中，半导体图案包括多晶硅图案。
在本公开的一种示例性实施例中，像素结构的宽度小于15um。
在本公开的一种示例性实施例中，还包括像素存储电容，像素存储电容的电容值小于150fF。
根据本发明的另一方面，提供一种显示装置，该装置包括如权利要求1-10中任一项所述的像素结构。
根据本发明的一种像素结构，能够在不增加门延迟的情况下降低馈通电压，提升器件充电能力，进而提升显示屏的显示性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本发明。
附图说明
通过参照附图详细描述其示例实施例，本发明的上述和其它目标、特征及优点将变得更加显而易见。
图1示意性示出馈通对像素充电的影响的曲线图。
图2是根据本发明的一示例性实施例的像素结构示意图。
图3是根据本发明的另一示例性实施例的像素结构示意图。
图4是根据本发明的另一示例性实施例的像素结构示意图。
图5是根据本发明的另一示例性实施例的像素结构示意图。
图6是根据本发明的另一示例性实施例的像素结构示意图。
图7是根据本发明的另一示例性实施例的像素结构示意图。
图8是根据本发明的另一示例性实施例的像素结构示意图。
图9是根据本发明的一示例性实施例的像素结构剖面示意图。
图10是根据本发明的一示例性实施例的像素结构仿真电路示意图。
图11是根据本发明的另一示例性实施例的像素结构仿真电路示意图。
图12是根据本发明的一示例性实施例的用于图6和图7的像素仿真电路的正帧充电曲线图。
图13是根据本发明的一示例性实施例的用于图6和图7的像素仿真电路的负帧充电曲线图。
具体实施例
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本发明将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。附图仅为本发明的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本发明的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本发明的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它组元、装置等。在其它情况下，不详细示出或描述公知结构、装置、材料以避免使得本发明的各方面变得模糊。
图2是根据本发明的一示例性实施例的像素结构示意图。
如图2所示，根据一示例性实施例的像素结构200包括：扫描线210、与扫描线210交叉的数据线220、半导体图案230、以及透明像素电极240。像素结构200可配置在一基板上(未绘出)。图中示出半导体图案230位于扫描线210之下，数据线220位于扫描线之下，但本发明不限于此。
半导体图案230还包括漏极接触233和源极接触234。
如图2所示，扫描线210具有一分支结构211。分支结构211从扫描线210垂直延伸，但本发明不限于此。
半导体图案230与扫描线210和分支结构211相交，从而半导体图案230包括：第一沟道区231，对应于扫描线210；第二沟道区232，对应于分支结构211；掺杂区235A、235B和235C，位于第一沟道区231和第二沟道区232两侧。
这样，如图2所示，第一沟道区231、第二沟道区232和掺杂区235A、235B、235C以及与第一沟道区231和第二沟道区232对应的部分扫描线210和分支结构211可用于构成多通道(多栅)薄膜晶体管230。
根据示例实施例，引入非对称双栅(或多栅)结构。例如，如图2所示，与半导体图案230交叉的分支结构211的宽度L2小于扫描线210的宽度L1，由于第一沟道区231，对应于扫描线210，所以第一沟道区231的宽度等于扫描线210的宽度L1，在本实施例中，用L1代表第一沟道区231的宽度以及扫描线210的宽度；第二沟道区232，对应于分支结构211，所以第二沟道区232的宽度等于分支结构211的宽度L2，在本实施例中，用L2代表第二沟道区232的宽度以及分支结构211的宽度；即，第二沟道区232的宽度小于第一沟道区231的宽度，从而在保证扫描线线宽不变的情况下，减小另一沟道区的宽度。这样，可以在不增加栅延迟的情况下，减小寄生电容，降低馈通电压。
在本发明实施例中，文中所提到的宽度只为了描述方便而使用，并非用以限定本发明，在本发明中的实施例中，长度与宽度的概念可以互相替换使用。
根据一些实施例，第二沟道区232的宽度也即为图2中L2，可以为第一沟道区231的宽度也即为图2中L1的1/5至4/5，以取得性能与成本的较好平衡。易于理解，本发明不限于此，第二沟道区232的宽度可以更小。只要工艺能力允许，可以一直减小第二沟道区232的宽度，只要TFT器件不失效。
根据一些实施例，半导体图案230，可由例如多晶硅材质制成，也就是说半导体图案230为一个多晶硅图案。
根据示例实施例，如图2所示，像素结构200还可包括源极接触233和漏极接触234。数据线220可电性连接源极接触234。透明像素电极240可电性连接漏极接触233。
根据示例实施例，如图2所示，半导体图案230还可包括电容电极237。
在示例实施例中，第二沟道232的宽度L2小于第一沟道231的宽度L1，可以有效减小像素结构中的寄生电容，使得示例实施例中的像素结构可以应用在像素结构宽度很小、像素存储电容很小的情况下。例如，根据一些实施例，像素结构宽度可小于15um。又例如，根据一些实施例，像素存储电容的电容值可小于150fF。采用现有技术，这是很难达到的。因此，根据本发明实施例的像素结构，适用于像素存储电容很小的高PPI技术，可以有效提升高PPI显示屏的充电能力，继而提升显示器的整体性能。
图3是根据本发明的另一示例性实施例的像素结构示意图。
如图3所示，该像素结构300包括：扫描线310、数据线320、半导体图案330、以及透明像素电极340。
图3所示的示例性实施例的像素结构与图2的像素结构基本相同。图3与图2不同处在于半导体图案330与扫描线310和分支结构311的延伸方向与图2不同。从而半导体图案330包括：第一沟道区331，对应于扫描线310；第二沟道区332，对应于分支结构311。
图4是根据本发明的另一示例性实施例的像素结构示意图。
如图4所示，该像素结构400包括：扫描线410、数据线420、半导体图案430、以及透明像素电极440。图4与图2不同处主要在于L形分支结构411以及半导体图案430包括直线部分。在图4中，L形分支结构411的第二部分和分支结构的411的第一部分相交，L形分支411的第二部分与半导体图案430的直线部分垂直相交，但本公开不限于此。半导体图案430与扫描线410和分支结构411相交，从而半导体图案430包括：第一沟道区431，对应于扫描线410；第二沟道区432，对应于分支结构411。图4与图2相同的部分在此不再赘述。
图5是根据本发明的另一示例性实施例的像素结构示意图。如图5所示，该像素结构500包括：扫描线510、数据线520、半导体图案530、以及透明像素电极540。图5与图2相同的部分在此不再赘述。
图5与图2不同处在于半导体图案530包含L形结构，半导体图案530包含的L形结构的一个边与扫描线510相交，半导体图案530包含的L形结构的另一个边和分支结构511相交，从而半导体图案530包括：第一沟道区531，对应于扫描线510；第二沟道区532，对应于分支结构511。
图6是根据本发明的另一示例性实施例的像素结构示意图。如图6所示，该像素结构600包括：扫描线610、数据线620、半导体图案630、以及透明像素电极640。图6与图2相同的部分在此不再赘述。
图6与图2不同处在于具有L形分支结构611的第二部分和分支结构的611的第一部分相交，L形分支611的第二部分与半导体图案630相交。半导体图案630与扫描线610和分支结构611相交，从而半导体图案630包括：第一沟道区631，对应于扫描线610；第二沟道区632，对应于分支结构611。第一沟道区631与第二沟道区632，均处于数据线620之下，但本发明不限于此。
图7是根据本发明的另一示例性实施例的像素结构示意图。如图7所示，该像素结构700包括：扫描线710、数据线720、半导体图案730、以及透明像素电极740。图7与图2相同的部分在此不再赘述。
如图7所示，扫描线710具有支结构711与712。分支结构711与分支结构712均从扫描线710垂直延伸，但本发明不限于此。
半导体图案730与扫描线710和分支结构711、分支结构712分别相交，从而半导体图案730包括：第一沟道区731，对应于扫描线710，扫描线710的宽度，也即为第一沟道区的宽度为L1”；第二沟道区732，对应于分支结构711，分支结构711的宽度，也即为第二沟道区的宽度为L2”；第三沟道区733，对应于分支结构712，分支结构712的宽度，也即为第三沟道区的宽度为L3”；掺杂区735A、735B位于第一沟道区731两侧、掺杂区735B、735C位于第二沟道区732两侧、掺杂区735C、735D位于第三沟道区733两侧。
如图7所示，第一沟道区731、第二沟道区732、第三沟道区733和掺杂区735A、735B、735C，735D以及与第一沟道区731，第二沟道区732和第三沟道区733对应的部分扫描线710、分支结构711以及分支结构712可用于构成多通道(多栅)薄膜晶体管730。
根据示例实施例，引入非对称多栅结构，例如，如图7所示，与半导体图案730交叉的至少一个分支结构711或者分支结构712的宽度小于扫描线710的宽度L1’，即，第二沟道区732的宽度L2”或者第三沟道区733的宽度L2”之中，至少一个沟道区的宽度小于第一沟道区731的宽度，从而在保证扫描线线宽不变的情况下，减小至少一沟道区的宽度。这样，可以在不增加栅延迟的情况下，减小寄生电容，降低馈通电压。
图8是根据本发明的另一示例性实施例的像素结构示意图。如图8所示，该像素结构800包括：扫描线810、数据线820、半导体图案830、以及透明像素电极840。图8与图7相同的部分在此不再赘述。
图8与图7不同处在于扫描线810具有分支结构811与分支结构812，其中分支结构812为L型分支结构，分支结构811与分支结构812均从扫描线810垂直延伸，但本发明不限于此。L形分支结构812的第二部分和分支结构的812的第一部分相交，L形分支812的第二部分与半导体图案830的直线部分垂直相交。半导体图案830与扫描线810和分支结构811、分支结构812分别相交，从而半导体图案830包括：第一沟道区831，对应于扫描线810；第二沟道区832，对应于分支结构811、第三沟道区833，对应于分支结构812。
图9是根据本发明的一示例性实施例示出的一种像素结构剖面示意图。图9A所示，该像素的剖面示意图包含扫描线层902、绝缘层904以及有源层906。根据示例实施例，扫描线层可包括扫描线9021以及扫描线分支结构9023。图9B所示，该像素的剖面示意图包含扫描线层902’、绝缘层904’以及有源层906’。根据示例实施例，其中扫描线层可还包括扫描线9021’以及扫描线分支结构9023’的剖面示意图。
图10是根据一示例性实施例示出的一种像素结构电路示意图。
如图10所示的电路图110，其中，Data为负帧电压，C1为像素存储电容，TFT1与TFT2为利用本发明公开中的像素结构中半导体电路所形成的等效电路。
参见图2示例，例如，可设置薄膜晶体管(TFT)开启电压VGH＝10V，薄膜晶体管(TFT)关闭电压VGL＝-7V，负帧电压Data为-5V，像素存储电容为0.32fF。扫描线210宽度为也即为上文所述的第一沟道231宽度L1为2um，扫描线分支211宽度也即为上文所述第二沟道232宽度L2的分别为3um、2um、1um。对图6实施例的正帧电压仿真结果如下表以及图13所示：
第二沟道宽度 充满电时电压 馈通电压损耗后电压 充电率
3um 5.00V 4.789V 95.78％
2um 5.00V 4.804V 96.08％
1um 5.00V 4.821V 96.42％
参见图3示例，例如，可设置薄膜晶体管(TFT)开启电压VGH＝10V，薄膜晶体管(TFT)关闭电压VGL＝-7V，负帧电压Data为-5V，像素存储电容为0.32fF。扫描线310宽度为也即为上文所述的第一沟道331宽度L1’为2um，扫描线分支311宽度也即为上文所述第二沟道332宽度L2’的分别为3um、2um、1um。对图6实施例的正帧电压仿真结果如下如下表以及图12所示：
第二沟道宽度 充满电时电压 馈通电压损耗后电压 充电率
3um 5.00V 4.789V 95.78％
2um 5.00V 4.826V 96.52％
1um 5.00V 4.856V 97.12％
在像素结构的正帧电压仿真中，设计目标是尽量减小馈通电压，也就是使得经过馈通电压损耗后的电压值尽量接近标准电压值5V。
从结果可以看到，在像素结构中，扫描线分支与扫描线宽度不同的情况下，对整个像素的正帧充电能力是有影响的。扫描线分支越宽，整体像素结构的充电能力越弱，即为，像素结构充电之后的结果越偏离5V。在本实施例中，在对此类结构的正帧电压的仿真表明，通过扫描线的宽度大于扫描线分支宽度这一实施例，即为第一沟道宽度大于第二沟道宽度这一实施例，能够有效降低馈通电压，提高器件充电能力。
图11是根据一示例性实施例示出的另一种像素结构电路示意图。
如图11所示的电路图120，其中，Data为负帧电压，C2为像素存储电容，TFT1与TFT2为利用本发明公开的像素结构中半导体电路所形成的等效电路。
参见图2示例，例如，可设置薄膜晶体管(TFT)开启电压VGH＝10V，薄膜晶体管(TFT)关闭电压VGL＝-7V，负帧电压Data为-5V，像素存储电容为32fF。扫描线210宽度为也即为上文所述的第一沟道231宽度L1为2um，扫描线分支211宽度也即为上文所述第二沟道232宽度L2的分别为3um、2um、1um。对图7实施例的负帧电压仿真结果如下表以及图13所示：
第二沟道宽度 充满电时电压 馈通电压损耗后电压 充电率
3um -5.00 -5.228 104.56％
2um -5.00 -5.169 103.38％
1um -5.00 -5.110 102.20％
参见图3示例，例如，可设置薄膜晶体管(TFT)开启电压VGH＝10V，薄膜晶体管(TFT)关闭电压VGL＝-7V，负帧电压Data为-5V，像素存储电容为32fF。扫描线310宽度为也即为上文所述的第一沟道331宽度L1’为2um，扫描线分支311宽度也即为上文所述第二沟道332宽度的分L2’别为3um、2um、1um。对图7实施例的负帧电压仿真结果如下表以及图13所示：
第二沟道宽度 充满电时电压 馈通电压损耗后电压 充电率
3um -5.00 -5.228 104.56％
2um -5.00 -5.142 102.84％
1um -5.00 -5.084 101.68％
在像素结构的负帧电压仿真中，设计目标是尽量减小馈通电压，也就是使得经过馈通电压损耗后的电压值尽量接近标准电压值-5V。
从结果可以看到，在像素结构中，扫描线分支与扫描线宽度不同的情况下，对整个像素的负帧充电能力也是有影响的。扫描线分支越宽，像素结构的充电能力越弱，即为，像素结构充电之后的结果越偏离-5V。在本实施例中，在对此类像素结构的负帧电压的仿真表明，通过扫描线的宽度大于扫描线分支宽度这一实施例，即为第一沟道宽度大于第二沟道宽度这一实施例，能够有效降低馈通电压，提高器件充电能力。
通过以上的详细描述，本领域的技术人员易于理解，根据本发明实施例的像素结构具有以下优点中的一个或多个。
根据一些实施例，本发明能够在不增加栅延迟的情况下降低馈通电压，从而提升器件充电能力，进而提升显示屏的显示性能。
以上具体地示出和描述了本发明的示例性实施例。应可理解的是，本发明不限于这里描述的详细结构、设置方式或实现方法；相反，本发明意图涵盖包含在所附权利要求的精神和范围内的各种修改和等效设置。

Claims (9)

1.一种像素结构，其特征在于，包括：
扫描线，所述扫描线具有分支结构；
半导体图案，所述半导体图案与所述扫描线和所述分支结构相交，所述半导体图案包括：
第一沟道区，对应于所述扫描线；
第二沟道区，对应于所述分支结构；
掺杂区，位于所述第一沟道区和所述第二沟道区两侧，
其中，所述第二沟道区的宽度小于所述第一沟道区的宽度；
所述分支结构为L形分支；
所述半导体图案包括直线部分，所述L形分支的第二部分和所述L形分支的第一部分相交，所述L形分支的第二部分与所述半导体图案直线部分垂直相交。
2.如权利要求1所述的像素结构，其特征在于，所述L形分支的所述第一部分从所述扫描线垂直延伸，所述L形分支的所述第二部分与所述半导体图案垂直相交。
3.如权利要求1所述的像素结构，其特征在于，所述分支结构从所述扫描线垂直延伸。
4.如权利要求3所述的像素结构，其特征在于，所述半导体图案至少包括第一部分和第二部分，所述第一部分与所述扫描线垂直相交，所述第二部分与所述分支结构垂直相交。
5.如权利要求1所述的像素结构，其特征在于，所述第二沟道区的宽度为所述第一沟道区的宽度的1/5至4/5。
6.如权利要求1所述的像素结构，其特征在于，所述半导体图案包括多晶硅图案。
7.如权利要求1所述的像素结构，其特征在于，所述像素结构的宽度小于15um。
8.如权利要求1所述的像素结构，其特征在于，还包括像素存储电容，所述像素存储电容的电容值小于150fF。
9.一种显示装置，其特征在于，包括如权利要求1-8中任一项所述的像素结构。
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