CN108231764A - 场效应晶体管的气隙间隙壁 - Google Patents

场效应晶体管的气隙间隙壁 Download PDF

Info

Publication number
CN108231764A
CN108231764A CN201711327372.5A CN201711327372A CN108231764A CN 108231764 A CN108231764 A CN 108231764A CN 201711327372 A CN201711327372 A CN 201711327372A CN 108231764 A CN108231764 A CN 108231764A
Authority
CN
China
Prior art keywords
dielectric gap
gap wall
wall
top surface
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711327372.5A
Other languages
English (en)
Other versions
CN108231764B (zh
Inventor
朴灿柔
成敏圭
金勋
谢瑞龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN108231764A publication Critical patent/CN108231764A/zh
Application granted granted Critical
Publication of CN108231764B publication Critical patent/CN108231764B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及场效应晶体管的气隙间隙壁，揭示场效应晶体管中的气隙间隙壁的结构以及在场效应晶体管中形成气隙间隙壁的方法。在半导体本体的顶部表面上形成栅极结构。邻近该栅极结构的垂直侧壁形成介电间隙壁。在该半导体本体的该顶部表面上形成半导体层。该半导体层相对该栅极结构的该垂直侧壁布置，以使该第一介电间隙壁的第一部分位于该半导体层与该栅极结构的该垂直侧壁之间的空间。移除位于该半导体层的顶部表面上方的该介电间隙壁的第二部分。在移除该介电间隙壁的该第二部分之处的空间中形成气隙间隙壁。

Description

场效应晶体管的气隙间隙壁
技术领域
本发明涉及半导体装置制造及集成电路，尤其涉及包括气隙间隙壁的场效应晶体管的结构以及形成具有气隙间隙壁的场效应晶体管的方法。
背景技术
场效应晶体管的装置结构包括源极、漏极，位于该源极与漏极之间的沟道，以及包括栅极电极及将该栅极电极与该沟道隔开的栅极介电质的栅极结构。向该栅极电极施加的栅极电压用以提供开关，以通过该沟道将该源极与漏极彼此选择性连接。金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor；MOSFET)的沟道位于支持栅极结构的衬底的顶部表面下方。
与平面场效应晶体管相比，鳍式场效应晶体管(fin-type field-effecttransistor；FinFET)是一种能够在集成电路中更加密集封装的MOSFET类型。FinFET可包括半导体鳍片，叠盖该半导体鳍片中的沟道的栅极电极，以及形成于该栅极结构周边的半导体鳍片的部分中的重掺杂源/漏区。FinFET的沟道被有效提升至衬底的顶部表面上方，从而栅极结构可包覆该沟道的多侧。栅极电极与鳍片之间的该包覆布置改进沟道的控制并降低当该FinFET处于其“关闭”状态时的漏电流。相应地，这支持较低阈值电压的使用并导致较好的性能及功率。
邻近场效应晶体管的栅极电极的侧壁可形成气隙间隙壁以降低栅极-源极电容，从而可导致性能提升。该气隙间隙壁的形成可能需要通过蚀刻制程移除伪间隙壁材料。在用以移除该伪间隙壁材料的该蚀刻制程执行期间可能难以控制蚀刻深度。如果蚀刻深度太大，则栅极介电材料可能通过该气隙间隙壁暴露。如果蚀刻深度太浅，则可能无法通过所述形成该气隙间隙壁优化性能的提升。
需要场效应晶体管的改进结构以及形成场效应晶体管的方法。
发明内容
在本发明的一个实施例中，一种方法包括在半导体本体的顶部表面上形成栅极结构，邻近该栅极结构的垂直侧壁形成介电间隙壁，以及在该半导体本体的该顶部表面上形成半导体层。该半导体层相对该栅极结构的该垂直侧壁布置，以使该介电间隙壁的第一部分水平位于该半导体层与该栅极结构的该垂直侧壁之间。该方法还包括移除位于该半导体层的顶部表面上方的该介电间隙壁的第二部分，以及在移除该介电间隙壁的该第二部分之处的空间中形成气隙间隙壁。
在本发明的一个实施例中，一种结构包括具有顶部表面的半导体本体，位于该半导体本体的该顶部表面上的栅极电极，以及位于该半导体本体的该顶部表面上的半导体层。该栅极电极具有垂直侧壁，且该半导体层具有顶部表面。该结构还包括位于该半导体层与该栅极电极的该垂直侧壁之间的介电间隙壁。该介电间隙壁自该半导体本体的该顶部表面延伸至该半导体层的该顶部表面。接触与该半导体层的该顶部表面连接。气隙间隙壁水平位于该接触与该栅极电极的该垂直侧壁之间。该气隙间隙壁垂直延伸至该半导体层的该顶部表面。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例，并与上面所作的本发明的概括说明以及下面所作的实施例的详细说明一起用以解释本发明的实施例。
图1显示依据本发明的实施例处于制程方法的初始阶段中的衬底的部分的透视图。
图2显示通常沿图1中的鳍片的其中之一的长度所作的剖视图。
图3至11显示处于继图2的制造阶段之后的该制程方法的连续阶段中的该衬底部分的剖视图。
具体实施方式
请参照图1、2并依据本发明的实施例，形成鳍片10、11并形成沟槽隔离14以电性隔离鳍片10与鳍片11以及鳍片10、11与其它附近鳍片(未显示)。鳍片10、11为半导体本体，其可通过光刻及蚀刻制程例如侧壁图像转移(sidewall imaging transfer；SIT)制程由衬底的半导体材料形成。衬底12可为由硅组成的块体衬底或绝缘体上半导体(semiconductor-on-insulator；SOI)衬底的硅装置层。沟槽隔离14可由例如通过化学气相沉积(chemicalvapor deposition；CVD)沉积的二氧化硅(SiO2)组成。独立于其形成方法，鳍片10、11的顶部表面13通常可被视为衬底12的顶部表面的延伸。
多个牺牲栅极结构16、18、20垂直突出于鳍片10的顶部表面13处的平面并叠盖鳍片10。在牺牲栅极结构16、18、20与鳍片11之间可存在类似的空间关系。牺牲栅极结构16、18、20可由半导体材料例如多晶硅组成，它们在其各自的顶部表面被多个硬掩膜层22、24、26覆盖。牺牲栅极结构16、18、20及分别覆盖牺牲栅极结构16、18、20的硬掩膜层22、24、26的该部分可通过沉积其构成材料的层堆叠并在存在图案化蚀刻掩膜(未显示)的情况下蚀刻来形成，硬掩膜层22、24、26的该部分充当硬掩膜以图案化牺牲栅极结构16、18、20。
硬掩膜层22及26分别由介电材料组成，该介电材料经选择以相对构成硬掩膜层24的介电材料被选择性移除。硬掩膜层22与硬掩膜层26可由氮化硅(Si3N4)薄层组成。硬掩膜层24可由二氧化硅(SiO2)薄层组成，其相对氮化硅呈现蚀刻选择性。
请参照图3，其中类似的附图标记表示图1、2中类似的特征，且在下一制造阶段，顺序沉积共形层28、30，其覆盖牺牲栅极结构16、18、20的垂直侧壁15、牺牲栅极结构16、18、20的顶部表面，以及牺牲栅极结构16、18、20的相邻对之间的间隙中的鳍片10的顶部表面13。共形层28包括用以定义位于邻近牺牲栅极结构16、18、20的垂直侧壁15以及/或者位于其上的介电间隙壁29的部分。共形层30也包括用以定义邻近牺牲栅极结构16、18、20的垂直侧壁15形成并通过介电间隙壁29与牺牲栅极结构16、18、20的垂直侧壁15隔开的介电间隙壁31的部分。在下一制造阶段中自共形层28、30成形间隙壁29、31。
外共形层30覆盖内共形层28，该内共形层位于外共形层30与牺牲栅极结构16、18、20的垂直侧壁15之间。在外共形层30之前沉积内共形层28，该内共形层28可由二氧化硅(SiO2)薄层组成。在内共形层28之后沉积外共形层30，该外共形层30可由相对二氧化硅呈现蚀刻选择性的氮化硅(Si3N4)薄层组成。内共形层28的厚度可大于外共形层30的厚度。
请参照图4，其中类似的附图标记表示图3中类似的特征，且在下一制造阶段，通过非等向性蚀刻制程例如反应离子蚀刻(reactive ionetching；RIE)成形外共形层30，从而形成间隙壁31，该蚀刻制程自水平表面例如牺牲栅极结构16、18、20的垂直侧壁15之间的间隙中的共形层28的顶部表面优先移除共形层30的介电材料。内共形层28保护覆盖各牺牲栅极结构16、18、20的硬掩膜层22、24、26的该部分以在此回蚀刻制程期间不被移除。
请参照图5，其中类似的附图标记表示图4中类似的特征，且在下一制造阶段，通过非等向性蚀刻制程例如反应离子蚀刻(RIE)成形内共形层28，从而形成间隙壁29，该蚀刻制程自水平表面例如牺牲栅极结构16、18、20的垂直侧壁15之间的间隙中的鳍片10的顶部表面移除共形层28的介电材料。该蚀刻制程相对构成介电间隙壁31的介电材料及构成鳍片10的半导体材料选择性优先移除共形层28的部分。本文中所使用的关于材料移除制程(例如，蚀刻)的术语“选择性”表示通过合适的蚀刻剂选择，目标材料的材料移除速率(也就是，蚀刻速率)大于暴露于该材料移除制程的至少另一种材料的移除速率。
内介电间隙壁29的厚度可大于外介电间隙壁31的厚度，其反映经成形以分别形成介电间隙壁29、31的共形层28、30的厚度之间的关系。间隙壁29、31相对鳍片10的顶部表面13可具有相同的高度，并自鳍片10的顶部表面13经过牺牲栅极结构16、18、20的顶部表面垂直延伸至硬掩膜层26的高度。
请参照图6，其中类似的附图标记表示图5中类似的特征，且在下一制造阶段，在间隙壁包覆的牺牲栅极结构16、18、20之间的间隙(也就是，开放空间)中的鳍片10上形成半导体层32。半导体层32可例如用以将鳍片10的源/漏区与相邻鳍片例如鳍片11(图1)的源/漏区合并。位于鳍片10的顶部表面13上的半导体层32可由外延半导体材料例如硅锗(SiGe)或硅(Si)组成，且可在生长期间经原位掺杂，以使所生长的半导体材料具有给定的导电类型。半导体层32可通过外延生长制程形成，例如选择性外延生长制程，其中，构成半导体材料成核以外延生长于半导体表面上(例如，鳍片10的顶部表面)，但不会成核以外延生长于绝缘体表面上(例如，硬掩膜层26及介电间隙壁31)。
半导体层32具有顶部表面33，其相对鳍片10的顶部表面13具有给定高度，由其层厚度确定。控制该层厚度可通过控制沉积条件来执行。在半导体层32的该外延生长之前的预清洗期间，外介电间隙壁31覆盖并保护内介电间隙壁29。例如，该预清洗可自鳍片10的表面移除原生氧化物，其也可能侵蚀内介电间隙壁29的材料(若该内介电间隙壁由二氧化硅组成且不被外介电间隙壁31掩蔽)。
请参照图7，其中类似的附图标记表示图6中类似的特征，且在下一制造阶段，自位于半导体层32的顶部表面33上方的牺牲栅极结构16、18、20的垂直侧壁15的部分移除外介电间隙壁31的部分。外介电间隙壁31的这些部分可通过蚀刻制程移除，例如湿化学蚀刻。也通过该蚀刻制程自牺牲栅极结构16、18、20的该顶部表面移除硬掩膜层26。外介电间隙壁31及硬掩膜层26的该移除相对构成内介电间隙壁29及硬掩膜层24的材料具有选择性。
在垂直位于半导体层32的顶部表面33下方且水平位于半导体层32与牺牲栅极结构16、18、20的其中相邻一者的垂直侧壁15之间的各空间中保留外介电间隙壁31的部分。外介电间隙壁31的这些部分自鳍片10的顶部表面13垂直延伸至半导体层32的顶部表面33。
在将外介电间隙壁31移除至半导体层32的顶部表面33以后，自半导体层32的顶部表面33上方的牺牲栅极结构16、18、20的垂直侧壁15的部分移除内介电间隙壁29。内介电间隙壁29的这些部分可通过蚀刻制程移除，例如湿化学蚀刻。也通过该蚀刻制程自牺牲栅极结构16、18、20的该顶部表面移除硬掩膜层24。内介电间隙壁29及硬掩膜层24的该移除相对构成鳍片10、牺牲栅极结构16、18、20、硬掩膜层22以及外介电间隙壁31的保留部分的材料具有选择性。
在该蚀刻制程序列以后，在牺牲栅极结构16、18、20的各相邻对的垂直侧壁15之间保留介电间隙壁29、31的相应部分。在垂直位于半导体层32的顶部表面33下方且水平位于牺牲栅极结构16、18、20与外介电间隙壁31之间的空间中保留内介电间隙壁29的部分。内介电间隙壁29的这些保留部分自鳍片10的顶部表面13垂直延伸至半导体层32的顶部表面33。介电间隙壁29、31的该保留部分位于牺牲栅极结构16、18、20与鳍片10的顶部表面13之间的接触界面附近，并在半导体层32的顶部表面33处及下方。自牺牲栅极结构16、18、20的垂直侧壁15的大部分移除介电间隙壁29、31两者的部分，以使牺牲栅极结构16、18、20的垂直侧壁15的部分被暴露且裸露于半导体层32的顶部表面33上方。
请参照图8，其中类似的附图标记表示图7中类似的特征，且在下一制造阶段，在半导体层32的顶部表面33的水平上方的牺牲栅极结构16、18、20的垂直侧壁15的该暴露部分以及硬掩膜层22的相应覆盖部分上形成侧间隙壁34。为形成侧间隙壁34，可沉积由介电材料组成的共形层，例如通过原子层沉积(atomic layer deposition；ALD)的氮化硅(Si3N4)，并通过非等向性蚀刻制程例如RIE成形该共形层，该蚀刻制程自水平表面例如半导体层32的该顶部表面优先移除该介电材料。构成侧间隙壁34的材料可经选择以相对侧间隙壁34可选择性移除牺牲栅极结构16、18、20。
侧间隙壁34、硬掩膜层22，以及外介电间隙壁31可由相同的介电材料组成，且该共同的组成可经选择以相对内介电间隙壁29的介电材料可选择性移除该共同组成的介电材料。侧间隙壁34可厚于外介电间隙壁31。在一个实施例中，侧间隙壁34的厚度可大于或等于自共形层28形成的介电间隙壁29与自共形层30形成的介电间隙壁31的总厚度。
请参照图9，其中类似的附图标记表示图8中类似的特征，且在下一制造阶段，沉积衬里层36，其覆盖牺牲栅极结构16、18、20的垂直侧壁15、牺牲栅极结构16、18、20的顶部表面上的硬掩膜层22，以及牺牲栅极结构16、18、20的相邻对之间的间隙中的半导体层32的顶部表面33。衬里层36可由介电材料组成，例如通过ALD沉积的氮化硅(Si3N4)。
沉积层间介电层38，其可由通过CVD沉积的二氧化硅(SiO2)组成。接着，执行蚀刻制程以相对层间介电层38选择性移除牺牲栅极结构16、18、20，从而定义栅极开口，随后将在该栅极开口中形成替代栅极电极。该蚀刻制程相对侧间隙壁34、层间介电层38，以及鳍片10的材料选择性移除构成牺牲栅极结构16、18、20的材料。在由牺牲栅极结构16、18、20空出的该栅极开口中形成替代栅极电极40、42、44。栅极电极40、42、44可由金属例如铝或钨以及用以调节阈值电压的一种或多种功函数金属层组成。在鳍片10的该顶部表面上的该栅极开口中可形成栅极介电质(未显示)。该栅极介电质可由介电材料组成，例如高k栅极介电材料如氧化铪。
在层间介电层38中的垂直接触开口中形成接触46，以接触该源/漏区的半导体层32。也在层间介电层38中的垂直接触开口中形成接触48，以接触栅极电极40、42、44的栅极电极。接触46、48可由例如钨(W)组成。由介电材料组成的覆盖层50覆盖栅极电极40、42、44的相应顶部表面。覆盖层50可由介电材料组成，例如氮化硅(Si3N4)，且可由与构成侧间隙壁34的介电材料相同的介电材料组成。
请参照图10，其中类似的附图标记表示图9中类似的特征，且在下一制造阶段，通过例如湿化学蚀刻相对栅极电极40、42、44、接触46、48、内介电间隙壁29，以及层间介电层38选择性移除侧间隙壁34及覆盖层50。通过移除侧间隙壁34及覆盖层50的该蚀刻制程可稍微凹入外介电间隙壁31。不过，相对侧间隙壁34的宽度的外介电间隙壁31的小的宽度以及在半导体层32与介电间隙壁29之间的设置用以限制移除及凹入介电间隙壁31的程度。蚀刻深度自动停止于间隙壁29的顶部表面，其与半导体层32的顶部表面33共面。这种蚀刻深度控制的精确度提供关于随后形成的气隙间隙壁的下边界的确定性及可重复性。间隙壁29自鳍片10的顶部表面13延伸至半导体层32的顶部表面33。
请参照图11，其中类似的附图标记表示图10中类似的特征，且在下一制造阶段，沉积介电层54，其以覆盖层56填充由覆盖层50空出的空间。覆盖层56覆盖并密封在移除侧间隙壁34空出的空间中所定义的气隙间隙壁58。气隙间隙壁58可以接近1(真空介电常数)的有效介电常数为特征，或者可由处于或接近大气压的空气填充，可由处于或接近大气压的另一种气体填充，或者可包含处于亚大气压的空气或另一种气体(例如，部分真空)。由于尺寸的区别，由移除侧间隙壁34空出的该空间的上开口在包含气隙间隙壁58的该空间可被介电层54填充之前封闭。不过，在该开口封闭之前，介电层54的部分60沉积于层间介电层38、栅极电极40、42、44、接触46、48以及介电间隙壁29、31的表面上作为围绕气隙间隙壁58的衬里。
气隙间隙壁58水平位于接触46与栅极电极40、42、44的垂直侧壁41之间。间隙壁29的存在提供预定的深度以在该预定深度上方移除侧间隙壁34，并提供对气隙间隙壁58相对栅极电极40、42、44的下边界的位置的控制。气隙间隙壁58在其底端与介电间隙壁29的顶部表面共同延伸，该顶部表面与半导体层32的顶部表面33共面。气隙间隙壁58的部分垂直位于半导体层32的顶部表面33与栅极电极40、42、44的相应顶部表面43之间。
图11的代表性实施例中的该装置结构是鳍式场效应晶体管(FinFET)，该晶体管的沟道区位于由鳍片10定义的该半导体本体的内部。在一个替代实施例中，可应用本发明的实施例以在平面场效应晶体管而不是鳍式场效应晶体管的装置构造中形成气隙间隙壁58。这些替代实施例的流程通常如图2至11中所示那样执行，除了没有鳍片10且所示制造阶段发生于衬底12的顶部表面上而不是发生于鳍片10的顶部表面上。在邻近牺牲栅极结构16、18、20并最终邻近栅极电极40、42、44的衬底12中及/或上可形成源/漏区。用以形成该场效应晶体管的衬底12的部分将表示由例如类似沟槽隔离14的沟道隔离区隔离的半导体本体。在一个替代实施例中，栅极结构16、18、20可不是牺牲的，以使流程不包括用栅极电极40、42、44替代栅极结构16、18、20。
上述方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。在后一种情况中，该芯片设于单芯片封装件中(例如塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。
本文中引用术语例如“垂直”、“水平”、“横向”等作为示例来建立参考框架，并非限制。术语例如“水平”及“横向”是指与半导体衬底的顶部表面平行的平面中的方向，而不论其实际的三维空间取向。术语例如“垂直”及“正交”是指垂直于该“水平”及“横向”方向的方向。术语例如“上方”及“下方”表示元件或结构相对彼此以及/或者相对该半导体衬底的顶部表面的定位，而不是相对标高。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接，或者可存在一个或多个中间元件。如果不存在中间元件，则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件，则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭示的实施例。

Claims (20)

1.一种方法，包括：
在半导体本体的顶部表面上形成栅极结构；
邻近该栅极结构的垂直侧壁形成第一介电间隙壁；
在该半导体本体的该顶部表面上形成相对该栅极结构的该垂直侧壁布置的半导体层，以使该第一介电间隙壁的第一部分水平位于该半导体层与该栅极结构的该垂直侧壁之间；
移除位于该半导体层的顶部表面上方的该第一介电间隙壁的第二部分；以及
在移除该第一介电间隙壁的该第二部分之处的空间中形成气隙间隙壁。
2.如权利要求1所述的方法，还包括：
用栅极电极替代该栅极结构；以及
形成延伸至该半导体层的该顶部表面的接触，
其中，该气隙间隙壁水平位于该接触与该栅极电极的垂直侧壁之间。
3.如权利要求2所述的方法，其中，在移除该第一介电间隙壁的该第二部分之处的该空间中形成该气隙间隙壁还包括：
在用该栅极电极替代该栅极结构之前，邻近该栅极结构的该垂直侧壁形成第二介电间隙壁，其位于该第一介电间隙壁的该第一部分上方以及该半导体层的该顶部表面上方。
4.如权利要求3所述的方法，其中，在移除该第一介电间隙壁的该第二部分之处的该空间中形成该气隙间隙壁还包括：
在形成该接触以后，相对该第一介电间隙壁的该第一部分选择性移除该第二介电间隙壁，以形成该气隙间隙壁。
5.如权利要求1所述的方法，其中，在移除该第一介电间隙壁的该第二部分之处的该空间中形成该气隙间隙壁还包括：
邻近该栅极结构的该垂直侧壁形成第二介电间隙壁，其位于该第一介电间隙壁的该第一部分上方以及该半导体层的该顶部表面上方。
6.如权利要求5所述的方法，在移除该第一介电间隙壁的该第二部分之处的该空间中形成该气隙间隙壁还包括：
在形成该第二介电间隙壁以后，形成延伸至该半导体层的该顶部表面的接触；以及
在形成该接触以后，相对该第一介电间隙壁的该第一部分选择性移除该第二介电间隙壁，以形成该气隙间隙壁。
7.如权利要求6所述的方法，还包括：
在形成该第二介电间隙壁以后，用栅极电极替代该栅极结构，
其中，该气隙间隙壁水平位于该接触与该栅极电极的垂直侧壁之间。
8.如权利要求1所述的方法，其中，该半导体本体为鳍片，且该半导体层形成于该鳍片的源/漏区上。
9.如权利要求1所述的方法，还包括：
在形成该第一介电间隙壁以后，邻近该栅极结构的该垂直侧壁形成第二介电间隙壁，
其中，该第一介电间隙壁的该第一部分水平位于该半导体层与该第二介电间隙壁的该第一部分之间。
10.如权利要求9所述的方法，还包括：
在移除该第一介电间隙壁的该第二部分之前，移除位于该半导体层的该顶部表面上方的该第二介电间隙壁的第二部分。
11.如权利要求9所述的方法，还包括：
在形成该第一介电间隙壁及该第二介电间隙壁之前，形成图案化硬掩膜层堆叠，其包括第一硬掩膜层、位于该第一硬掩膜层上的第二硬掩膜层，以及位于该第二硬掩膜层上的第三硬掩膜层，
其中，利用该硬掩膜层堆叠形成该栅极结构。
12.如权利要求11所述的方法，还包括：
在移除该第一介电间隙壁的该第二部分之前，移除位于该半导体层的该顶部表面上方的该第二介电间隙壁的第二部分，
其中，当移除该第二介电间隙壁的该第二部分时，移除该第三硬掩膜层。
13.如权利要求12所述的方法，其中，当自该栅极结构的该垂直侧壁移除该第二介电间隙壁的该第二部分时，该第一介电间隙壁的该第二部分掩蔽该硬掩膜层堆叠。
14.如权利要求12所述的方法，其中，当移除该第一介电间隙壁的该第二部分时移除该第二硬掩膜层，且还包括：
在移除该第一介电间隙壁的该第二部分之处的该空间中形成第三介电间隙壁，
其中，通过自该空间移除该第三介电间隙壁形成该气隙间隙壁。
15.一种结构，包括：
半导体本体，具有顶部表面，
栅极电极，位于该半导体本体的该顶部表面上，该栅极电极具有垂直侧壁；
半导体层，位于该半导体本体的该顶部表面上，该半导体层具有顶部表面；
第一介电间隙壁，位于该半导体层与该栅极电极的该垂直侧壁之间，该第一介电间隙壁自该半导体本体的该顶部表面延伸至该半导体层的该顶部表面；
接触，与该半导体层的该顶部表面连接；以及
气隙间隙壁，水平位于该接触与该栅极电极的该垂直侧壁之间，
其中，该气隙间隙壁垂直延伸至该半导体层的该顶部表面。
16.如权利要求15所述的结构，还包括：
第二介电间隙壁，位于该半导体层与该第一介电间隙壁之间，
其中，该第二介电间隙壁位于该半导体本体的该顶部表面上，且该第二介电间隙壁垂直位于该半导体层的该顶部表面下方。
17.如权利要求16所述的结构，其中，该第一介电间隙壁水平位于该第二介电间隙壁与该栅极电极的该垂直侧壁之间，该第一介电间隙壁由二氧化硅组成，且该第二介电间隙壁由氮化硅组成。
18.如权利要求16所述的结构，其中，该第一介电间隙壁位于该第二介电间隙壁与该栅极电极的该垂直侧壁之间，该第一介电间隙壁具有厚度，且该气隙间隙壁具有大于该第一介电间隙壁的该厚度的厚度。
19.如权利要求16所述的结构，其中，该第一介电间隙壁位于该第二介电间隙壁与该栅极电极的该垂直侧壁之间，该第一介电间隙壁由二氧化硅组成，且该第二介电间隙壁由氮化硅组成。
20.如权利要求15所述的结构，其中，该半导体本体为鳍片，且该半导体层为该鳍片的源/漏区的部分。
CN201711327372.5A 2016-12-13 2017-12-13 场效应晶体管的气隙间隙壁 Active CN108231764B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/376,831 US10319627B2 (en) 2016-12-13 2016-12-13 Air-gap spacers for field-effect transistors
US15/376,831 2016-12-13

Publications (2)

Publication Number Publication Date
CN108231764A true CN108231764A (zh) 2018-06-29
CN108231764B CN108231764B (zh) 2021-11-26

Family

ID=62489581

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711327372.5A Active CN108231764B (zh) 2016-12-13 2017-12-13 场效应晶体管的气隙间隙壁

Country Status (3)

Country Link
US (2) US10319627B2 (zh)
CN (1) CN108231764B (zh)
TW (1) TWI657538B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729233A (zh) * 2018-07-16 2020-01-24 台湾积体电路制造股份有限公司 具有气隙的半导体结构、其制造方法和气隙的密封方法
CN113192828A (zh) * 2021-04-29 2021-07-30 长鑫存储技术有限公司 半导体结构的制备方法和半导体结构
CN113451308A (zh) * 2020-03-24 2021-09-28 格芯(美国)集成电路科技有限公司 源极/漏极区具有外延半导体材料区段的晶体管

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522642B2 (en) * 2016-12-14 2019-12-31 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor device with air-spacer
US10290549B2 (en) * 2017-09-05 2019-05-14 Globalfoundries Inc. Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same
US10170582B1 (en) * 2017-09-13 2019-01-01 International Business Machines Corporation Uniform bottom spacer for vertical field effect transistor
KR102399071B1 (ko) * 2017-11-17 2022-05-17 삼성전자주식회사 반도체 장치
US10211092B1 (en) * 2018-01-28 2019-02-19 International Business Machines Corporation Transistor with robust air spacer
US10431500B1 (en) * 2018-03-27 2019-10-01 Globalfoundries Inc. Multi-step insulator formation in trenches to avoid seams in insulators
CN110581101B (zh) 2018-06-07 2022-01-11 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10608096B2 (en) * 2018-06-11 2020-03-31 International Business Machines Corporation Formation of air gap spacers for reducing parasitic capacitance
US10714342B2 (en) * 2018-07-31 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN110858578B (zh) * 2018-08-23 2021-07-13 联华电子股份有限公司 管芯封环及其制造方法
US10985076B2 (en) 2018-08-24 2021-04-20 International Business Machines Corporation Single metallization scheme for gate, source, and drain contact integration
WO2020052630A1 (en) * 2018-09-14 2020-03-19 Changxin Memory Technologies, Inc. Semiconductor device and methods for manufacturing thereof
US11508827B2 (en) * 2018-09-26 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Air spacer for a gate structure of a transistor
US10825721B2 (en) * 2018-10-23 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating cap on contact structure and method for forming the same
US10861746B2 (en) * 2018-11-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
US10910273B2 (en) * 2019-02-25 2021-02-02 International Business Machines Corporation Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
US11145540B2 (en) * 2019-08-08 2021-10-12 Nanya Technology Corporation Semiconductor structure having air gap dielectric and the method of preparing the same
KR20210038762A (ko) * 2019-09-30 2021-04-08 삼성전자주식회사 반도체 장치
US11355616B2 (en) 2019-10-31 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Air spacers around contact plugs and method forming same
TWI721690B (zh) * 2019-12-06 2021-03-11 華邦電子股份有限公司 記憶體結構及其製造方法
US11901220B2 (en) 2019-12-20 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Bilayer seal material for air gaps in semiconductor devices
CN113013100A (zh) * 2019-12-20 2021-06-22 台湾积体电路制造股份有限公司 用于形成半导体器件的方法
TWI717970B (zh) * 2020-01-14 2021-02-01 華邦電子股份有限公司 半導體結構以及其形成方法
US11101177B1 (en) 2020-02-19 2021-08-24 Winbond Electronics Corp. Semiconductor structure and method for forming the same
US11289585B2 (en) 2020-02-27 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of formation
TWI786548B (zh) * 2020-02-27 2022-12-11 台灣積體電路製造股份有限公司 半導體裝置及其形成方法
US11557510B2 (en) 2020-07-30 2023-01-17 Taiwan Semiconductor Manufacturing Co., Ltd. Spacers for semiconductor devices including backside power rails
US11374093B2 (en) * 2020-11-25 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and methods of forming the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180988B1 (en) * 1997-12-04 2001-01-30 Texas Instruments-Acer Incorporated Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
KR20010011638A (ko) * 1999-07-29 2001-02-15 김영환 반도체장치의 구조 및 그 제조방법
US20130217194A1 (en) * 2010-06-23 2013-08-22 Fujitsu Semiconductor Limited Mos transistor, manufacturing method thereof, and semiconductor device
US20150255561A1 (en) * 2012-10-22 2015-09-10 Globalfoundries Inc. Semiconductor device with low-k spacers
US20160225667A1 (en) * 2015-01-29 2016-08-04 Globalfoundries Inc. Semiconductor structure having source/drain gouging immunity
US9443956B2 (en) * 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
CN106104807A (zh) * 2014-03-10 2016-11-09 高通股份有限公司 其中限定有间隙的半导体器件
US9508829B1 (en) * 2015-11-13 2016-11-29 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859089A (en) 1997-07-01 1999-01-12 The Kerr Corporation Dental restorative compositions
US5869374A (en) 1998-04-22 1999-02-09 Texas Instruments-Acer Incorporated Method to form mosfet with an inverse T-shaped air-gap gate structure
US6127251A (en) 1998-09-08 2000-10-03 Advanced Micro Devices, Inc. Semiconductor device with a reduced width gate dielectric and method of making same
TW462122B (en) 2000-12-18 2001-11-01 United Microelectronics Corp Air gap semiconductor structure and the manufacturing method thereof
TW476135B (en) 2001-01-09 2002-02-11 United Microelectronics Corp Manufacture of semiconductor with air gap
US7442609B2 (en) * 2004-09-10 2008-10-28 Infineon Technologies Ag Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
US7741663B2 (en) 2008-10-24 2010-06-22 Globalfoundries Inc. Air gap spacer formation
US8637930B2 (en) * 2011-10-13 2014-01-28 International Business Machines Company FinFET parasitic capacitance reduction using air gap
KR101917815B1 (ko) * 2012-05-31 2018-11-13 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US8946791B2 (en) * 2012-08-31 2015-02-03 International Business Machines Corporation Finfet with reduced parasitic capacitance
US9275911B2 (en) * 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US8847401B2 (en) * 2012-10-31 2014-09-30 International Business Machines Corporation Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure
US8841711B1 (en) 2013-03-12 2014-09-23 Globalfoundries Inc. Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
JP6249888B2 (ja) * 2014-06-19 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置
US9484250B2 (en) * 2015-03-10 2016-11-01 International Business Machines Corporation Air gap contact formation for reducing parasitic capacitance
KR102452593B1 (ko) * 2015-04-15 2022-10-11 삼성전자주식회사 반도체 장치의 제조 방법
EP3326206B1 (en) * 2015-07-17 2021-11-24 Intel Corporation Method of manufacturing a transistor with airgap spacer
US9786737B2 (en) * 2015-12-03 2017-10-10 International Business Machines Corporation FinFET with reduced parasitic capacitance
US9716154B2 (en) * 2015-12-17 2017-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having a gas-filled gap
US10164029B2 (en) * 2015-12-18 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9627514B1 (en) * 2015-12-28 2017-04-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10573749B2 (en) * 2016-02-25 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
US9716158B1 (en) * 2016-03-21 2017-07-25 International Business Machines Corporation Air gap spacer between contact and gate region
US9735246B1 (en) * 2016-05-11 2017-08-15 International Business Machines Corporation Air-gap top spacer and self-aligned metal gate for vertical fets
US9608065B1 (en) * 2016-06-03 2017-03-28 International Business Machines Corporation Air gap spacer for metal gates
US9892961B1 (en) * 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180988B1 (en) * 1997-12-04 2001-01-30 Texas Instruments-Acer Incorporated Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
KR20010011638A (ko) * 1999-07-29 2001-02-15 김영환 반도체장치의 구조 및 그 제조방법
US20130217194A1 (en) * 2010-06-23 2013-08-22 Fujitsu Semiconductor Limited Mos transistor, manufacturing method thereof, and semiconductor device
US20150255561A1 (en) * 2012-10-22 2015-09-10 Globalfoundries Inc. Semiconductor device with low-k spacers
CN106104807A (zh) * 2014-03-10 2016-11-09 高通股份有限公司 其中限定有间隙的半导体器件
US9443956B2 (en) * 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
US20160225667A1 (en) * 2015-01-29 2016-08-04 Globalfoundries Inc. Semiconductor structure having source/drain gouging immunity
US9508829B1 (en) * 2015-11-13 2016-11-29 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110729233A (zh) * 2018-07-16 2020-01-24 台湾积体电路制造股份有限公司 具有气隙的半导体结构、其制造方法和气隙的密封方法
CN110729233B (zh) * 2018-07-16 2022-04-19 台湾积体电路制造股份有限公司 具有气隙的半导体结构、其制造方法和气隙的密封方法
US11398404B2 (en) 2018-07-16 2022-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with air gap and method sealing the air gap
US11688631B2 (en) 2018-07-16 2023-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with air gap and method sealing the air gap
CN113451308A (zh) * 2020-03-24 2021-09-28 格芯(美国)集成电路科技有限公司 源极/漏极区具有外延半导体材料区段的晶体管
CN113192828A (zh) * 2021-04-29 2021-07-30 长鑫存储技术有限公司 半导体结构的制备方法和半导体结构

Also Published As

Publication number Publication date
CN108231764B (zh) 2021-11-26
US20180166319A1 (en) 2018-06-14
US20190198381A1 (en) 2019-06-27
TWI657538B (zh) 2019-04-21
US10319627B2 (en) 2019-06-11
TW201834145A (zh) 2018-09-16
US10923389B2 (en) 2021-02-16

Similar Documents

Publication Publication Date Title
CN108231764A (zh) 场效应晶体管的气隙间隙壁
US10269983B2 (en) Stacked nanosheet field-effect transistor with air gap spacers
US10014390B1 (en) Inner spacer formation for nanosheet field-effect transistors with tall suspensions
US10510890B2 (en) Fin-type field effect transistor structure and manufacturing method thereof
CN109524468A (zh) 半导体器件
CN109411352A (zh) 纳米片场效应晶体管中的内间隙壁形成
US20200066894A1 (en) Nanosheet field-effect transistors formed with sacrificial spacers
TW201926708A (zh) 半導體裝置
CN103187304A (zh) 制造半导体器件和晶体管的方法
US9972495B1 (en) Low-K dielectric spacer for a gate cut
CN108400137A (zh) 垂直场效应晶体管与鞍形鳍式场效应晶体管的集成
CN108878535A (zh) 具有单扩散中断的鳍式场效应晶体管及方法
US10679894B2 (en) Airgap spacers formed in conjunction with a late gate cut
US11682591B2 (en) Method for forming transistor structures
US9793174B1 (en) FinFET device on silicon-on-insulator and method of forming the same
US10050125B1 (en) Vertical-transport field-effect transistors with an etched-through source/drain cavity
CN107026088A (zh) 半导体器件的制造方法
US20220238524A1 (en) Complementary metal-oxide-semiconductor device and method of manufacturing the same
US10211317B1 (en) Vertical-transport field-effect transistors with an etched-through source/drain cavity
CN114334827A (zh) 半导体结构及其形成方法
TWI798749B (zh) 積體電路裝置及其製造方法
CN105405890B (zh) 包括带电荷体侧墙的半导体器件及其制造方法
TWI728688B (zh) 具有擴散阻擋間隔件區段之場效電晶體
CN109427907A (zh) 半导体器件及其制造方法
CN116825637A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210301

Address after: California, USA

Applicant after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Applicant before: GF

GR01 Patent grant
GR01 Patent grant