TW201834145A - 場效應電晶體的氣隙間隙壁 - Google Patents

場效應電晶體的氣隙間隙壁 Download PDF

Info

Publication number
TW201834145A
TW201834145A TW106135332A TW106135332A TW201834145A TW 201834145 A TW201834145 A TW 201834145A TW 106135332 A TW106135332 A TW 106135332A TW 106135332 A TW106135332 A TW 106135332A TW 201834145 A TW201834145 A TW 201834145A
Authority
TW
Taiwan
Prior art keywords
dielectric spacer
spacer
top surface
dielectric
semiconductor layer
Prior art date
Application number
TW106135332A
Other languages
English (en)
Other versions
TWI657538B (zh
Inventor
燦柔 朴
成敏圭
勳 金
謝瑞龍
Original Assignee
美商格芯（美國）集成電路科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商格芯（美國）集成電路科技有限公司 filed Critical 美商格芯（美國）集成電路科技有限公司
Publication of TW201834145A publication Critical patent/TW201834145A/zh
Application granted granted Critical
Publication of TWI657538B publication Critical patent/TWI657538B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本發明揭示場效應電晶體中的氣隙間隙壁的結構以及在場效應電晶體中形成氣隙間隙壁的方法。在半導體本體的頂部表面上形成閘極結構。鄰近該閘極結構的垂直側壁形成介電間隙壁。在該半導體本體的該頂部表面上形成半導體層。該半導體層相對該閘極結構的該垂直側壁佈置，以使該第一介電間隙壁的第一部分位於該半導體層與該閘極結構的該垂直側壁之間的空間。移除位於該半導體層的頂部表面上方的該介電間隙壁的第二部分。在移除該介電間隙壁的該第二部分處的空間中形成氣隙間隙壁。

Description

場效應電晶體的氣隙間隙壁
本發明關於半導體裝置製造及積體電路，尤其關於包括氣隙間隙壁的場效應電晶體的結構以及形成具有氣隙間隙壁的場效應電晶體的方法。
場效應電晶體的裝置結構包括源極、汲極，位於該源極與汲極之間的溝道，以及包括閘極電極及將該閘極電極與該溝道隔開的閘極介電質的閘極結構。向該閘極電極施加的閘極電壓用以提供開關，以通過該溝道將該源極與汲極彼此選擇性連接。金屬氧化物半導體場效應電晶體(metal-oxide-semiconductor field-effect transistor；MOSFET)的溝道位於支援閘極結構的基板的頂部表面下方。
與平面場效應電晶體相比，鰭式場效應電晶體(fin-type field-effect transistor；FinFET)是一種能夠在積體電路中更加密集封裝的MOSFET類型。FinFET可包括半導體鰭片，疊蓋該半導體鰭片中的溝道的閘極電極，以及形成於該閘極結構周邊的半導體鰭片的部分中的 重摻雜源/汲區。FinFET的溝道被有效提升至基板的頂部表面上方，從而閘極結構可包覆該溝道的多側。閘極電極與鰭片之間的該包覆佈置改進溝道的控制並降低當該FinFET處於其“關閉”狀態時的漏電流。相應地，這支援較低閾值電壓的使用並導致較好的性能及功率。
鄰近場效應電晶體的閘極電極的側壁可形成氣隙間隙壁以降低閘極-源極電容，從而可導致性能提升。該氣隙間隙壁的形成可能需要通過蝕刻製程移除偽間隙壁材料。在用以移除該偽間隙壁材料的該蝕刻製程執行期間可能難以控制蝕刻深度。如果蝕刻深度太大，則閘極介電材料可能通過該氣隙間隙壁暴露。如果蝕刻深度太淺，則可能無法通過所述形成該氣隙間隙壁優化性能的提升。
需要場效應電晶體的改進結構以及形成場效應電晶體的方法。
在本發明的一個實施例中，一種方法包括在半導體本體的頂部表面上形成閘極結構，鄰近該閘極結構的垂直側壁形成介電間隙壁，以及在該半導體本體的該頂部表面上形成半導體層。該半導體層相對該閘極結構的該垂直側壁佈置，以使該介電間隙壁的第一部分水平位於該半導體層與該閘極結構的該垂直側壁之間。該方法更包括移除位於該半導體層的頂部表面上方的該介電間隙壁的第二部分，以及在移除該介電間隙壁的該第二部分處的空 間中形成氣隙間隙壁。
在本發明的一個實施例中，一種結構包括具有頂部表面的半導體本體，位於該半導體本體的該頂部表面上的閘極電極，以及位於該半導體本體的該頂部表面上的半導體層。該閘極電極具有垂直側壁，且該半導體層具有頂部表面。該結構更包括位於該半導體層與該閘極電極的該垂直側壁之間的介電間隙壁。該介電間隙壁自該半導體本體的該頂部表面延伸至該半導體層的該頂部表面。接觸與該半導體層的該頂部表面連接。氣隙間隙壁水平位於該接觸與該閘極電極的該垂直側壁之間。該氣隙間隙壁垂直延伸至該半導體層的該頂部表面。
10、11‧‧‧鰭片
12‧‧‧基板
13‧‧‧頂部表面
14‧‧‧溝槽隔離
15‧‧‧垂直側壁
16、18、20‧‧‧犧牲閘極結構
22、24、26‧‧‧硬遮罩層
28‧‧‧共形層、內共形層
30‧‧‧共形層、外共形層
29‧‧‧介電間隙壁、間隙壁、內介電間隙壁
31‧‧‧介電間隙壁、間隙壁、外介電間隙壁
32‧‧‧半導體層
33‧‧‧頂部表面
34‧‧‧側間隙壁
36‧‧‧襯裡層
38‧‧‧層間介電層
40、42、44‧‧‧替代閘極電極、閘極電極
41‧‧‧垂直側壁
43‧‧‧頂部表面
46、48‧‧‧接觸
50‧‧‧覆蓋層
54‧‧‧介電層
56‧‧‧覆蓋層
58‧‧‧氣隙間隙壁
60‧‧‧部分
包含於並構成本說明書的一部分的圖式說明本發明的各種實施例，並與上面所作的本發明的概括說明以及下面所作的實施例的詳細說明一起用以解釋本發明的實施例。
第1圖顯示依據本發明的實施例處於製程方法的初始階段中的基板的部分的透視圖。
第2圖顯示通常沿第1圖中的鰭片的其中之一的長度所作的剖視圖。
第3至11圖顯示處於繼第2圖的製造階段之後的該製程方法的連續階段中的該基板部分的剖視圖。
請參照第1、2圖並依據本發明的實施例， 形成鰭片10、11並形成溝槽隔離14以電性隔離鰭片10與鰭片11以及鰭片10、11與其它附近鰭片(未顯示)。鰭片10、11為半導體本體，其可通過光刻及蝕刻製程例如側壁圖像轉移(sidewall imaging transfer；SIT)製程由基板的半導體材料形成。基板12可為由矽組成的塊體基板或絕緣體上半導體(semiconductor-on-insulator；SOI)基板的矽裝置層。溝槽隔離14可由例如通過化學氣相沉積(chemical vapor deposition；CVD)沉積的二氧化矽(SiO2)組成。獨立于其形成方法，鰭片10、11的頂部表面13通常可被視為基板12的頂部表面的延伸。
多個犧牲閘極結構16、18、20垂直突出於鰭片10的頂部表面13處的平面並疊蓋鰭片10。在犧牲閘極結構16、18、20與鰭片11之間可存在類似的空間關係。犧牲閘極結構16、18、20可由半導體材料例如多晶矽組成，它們在其各自的頂部表面被多個硬遮罩層22、24、26覆蓋。犧牲閘極結構16、18、20及分別覆蓋犧牲閘極結構16、18、20的硬遮罩層22、24、26的該部分可通過沉積其構成材料的層堆疊並在存在圖案化蝕刻遮罩(未顯示)的情況下蝕刻來形成，硬遮罩層22、24、26的該部分充當硬遮罩以圖案化犧牲閘極結構16、18、20。
硬遮罩層22及26分別由介電材料組成，該介電材料經選擇以相對構成硬遮罩層24的介電材料被選擇性移除。硬遮罩層22與硬遮罩層26可由氮化矽(Si3N4)薄層組成。硬遮罩層24可由二氧化矽(SiO2)薄層組成，其 相對氮化矽呈現蝕刻選擇性。
請參照第3圖，其中類似的元件符號表示第1、2圖中類似的特徵，且在下一製造階段，順序沉積共形層28、30，其覆蓋犧牲閘極結構16、18、20的垂直側壁15、犧牲閘極結構16、18、20的頂部表面，以及犧牲閘極結構16、18、20的相鄰對之間的間隙中的鰭片10的頂部表面13。共形層28包括用以定義位於鄰近犧牲閘極結構16、18、20的垂直側壁15以及/或者位於其上的介電間隙壁29的部分。共形層30也包括用以定義鄰近犧牲閘極結構16、18、20的垂直側壁15形成並通過介電間隙壁29與犧牲閘極結構16、18、20的垂直側壁15隔開的介電間隙壁31的部分。在下一製造階段中自共形層28、30成形間隙壁29、31。
外共形層30覆蓋內共形層28，該內共形層位於外共形層30與犧牲閘極結構16、18、20的垂直側壁15之間。在外共形層30之前沉積內共形層28，該內共形層28可由二氧化矽(SiO2)薄層組成。在內共形層28之後沉積外共形層30，該外共形層30可由相對二氧化矽呈現蝕刻選擇性的氮化矽(Si3N4)薄層組成。內共形層28的厚度可大於外共形層30的厚度。
請參照第4圖，其中類似的元件符號表示第3圖中類似的特徵，且在下一製造階段，通過非等向性蝕刻製程例如反應離子蝕刻(reactive ion etching；RIE)成形外共形層30，從而形成間隙壁31，該蝕刻製程自水平表面例 如犧牲閘極結構16、18、20的垂直側壁15之間的間隙中的共形層28的頂部表面優先移除共形層30的介電材料。內共形層28保護覆蓋各犧牲閘極結構16、18、20的硬遮罩層22、24、26的該部分以在此回蝕刻製程期間不被移除。
請參照第5圖，其中類似的元件符號表示第4圖中類似的特徵，且在下一製造階段，通過非等向性蝕刻製程例如反應離子蝕刻(RIE)成形內共形層28，從而形成間隙壁29，該蝕刻製程自水準表面例如犧牲閘極結構16、18、20的垂直側壁15之間的間隙中的鰭片10的頂部表面移除共形層28的介電材料。該蝕刻製程相對構成介電間隙壁31的介電材料及構成鰭片10的半導體材料選擇性優先移除共形層28的部分。本文中所使用的關於材料移除製程(例如，蝕刻)的術語“選擇性”表示通過合適的蝕刻劑選擇，目標材料的材料移除速率(也就是，蝕刻速率)大於暴露於該材料移除製程的至少另一種材料的移除速率。
內介電間隙壁29的厚度可大於外介電間隙壁31的厚度，其反映經成形以分別形成介電間隙壁29、31的共形層28、30的厚度之間的關係。間隙壁29、31相對鰭片10的頂部表面13可具有相同的高度，並自鰭片10的頂部表面13經過犧牲閘極結構16、18、20的頂部表面垂直延伸至硬遮罩層26的高度。
請參照第6圖，其中類似的元件符號表示第5圖中類似的特徵，且在下一製造階段，在間隙壁包覆的犧牲閘極結構16、18、20之間的間隙(也就是，開放空 間)中的鰭片10上形成半導體層32。半導體層32可例如用以將鰭片10的源/汲區與相鄰鰭片例如鰭片11(第1圖)的源/汲區合併。位於鰭片10的頂部表面13上的半導體層32可由磊晶半導體材料例如矽鍺(SiGe)或矽(Si)組成，且可在生長期間經原位摻雜，以使所生長的半導體材料具有給定的導電類型。半導體層32可通過磊晶生長製程形成，例如選擇性磊晶生長製程，其中，構成半導體材料成核以磊晶生長於半導體表面上(例如，鰭片10的頂部表面)，但不會成核以磊晶生長於絕緣體表面上(例如，硬遮罩層26及介電間隙壁31)。
半導體層32具有頂部表面33，其相對鰭片10的頂部表面13具有給定高度，由其層厚度確定。控制該層厚度可通過控制沉積條件來執行。在半導體層32的該磊晶生長之前的預清洗期間，外介電間隙壁31覆蓋並保護內介電間隙壁29。例如，該預清洗可自鰭片10的表面移除原生氧化物，其也可能侵蝕內介電間隙壁29的材料(若該內介電間隙壁由二氧化矽組成且不被外介電間隙壁31掩蔽)。
請參照第7圖，其中類似的元件符號表示第6圖中類似的特徵，且在下一製造階段，自位於半導體層32的頂部表面33上方的犧牲閘極結構16、18、20的垂直側壁15的部分移除外介電間隙壁31的部分。外介電間隙壁31的這些部分可通過蝕刻製程移除，例如濕化學蝕刻。也通過該蝕刻製程自犧牲閘極結構16、18、20的該頂 部表面移除硬遮罩層26。外介電間隙壁31及硬遮罩層26的該移除相對構成內介電間隙壁29及硬遮罩層24的材料具有選擇性。
在垂直位於半導體層32的頂部表面33下方且水準位於半導體層32與犧牲閘極結構16、18、20的其中相鄰一者的垂直側壁15之間的各空間中保留外介電間隙壁31的部分。外介電間隙壁31的這些部分自鰭片10的頂部表面13垂直延伸至半導體層32的頂部表面33。
在將外介電間隙壁31移除至半導體層32的頂部表面33以後，自半導體層32的頂部表面33上方的犧牲閘極結構16、18、20的垂直側壁15的部分移除內介電間隙壁29。內介電間隙壁29的這些部分可通過蝕刻製程移除，例如濕化學蝕刻。也通過該蝕刻製程自犧牲閘極結構16、18、20的該頂部表面移除硬遮罩層24。內介電間隙壁29及硬遮罩層24的該移除相對構成鰭片10、犧牲閘極結構16、18、20、硬遮罩層22以及外介電間隙壁31的保留部分的材料具有選擇性。
在該蝕刻製程序列以後，在犧牲閘極結構16、18、20的各相鄰對的垂直側壁15之間保留介電間隙壁29、31的相應部分。在垂直位於半導體層32的頂部表面33下方且水準位於犧牲閘極結構16、18、20與外介電間隙壁31之間的空間中保留內介電間隙壁29的部分。內介電間隙壁29的這些保留部分自鰭片10的頂部表面13垂直延伸至半導體層32的頂部表面33。介電間隙壁29、 31的該保留部分位於犧牲閘極結構16、18、20與鰭片10的頂部表面13之間的接觸介面附近，並在半導體層32的頂部表面33處及下方。自犧牲閘極結構16、18、20的垂直側壁15的大部分移除介電間隙壁29、31兩者的部分，以使犧牲閘極結構16、18、20的垂直側壁15的部分被暴露且裸露於半導體層32的頂部表面33上方。
請參照第8圖，其中類似的元件符號表示第7圖中類似的特徵，且在下一製造階段，在半導體層32的頂部表面33的水準上方的犧牲閘極結構16、18、20的垂直側壁15的該暴露部分以及硬遮罩層22的相應覆蓋部分上形成側間隙壁34。為形成側間隙壁34，可沉積由介電材料組成的共形層，例如通過原子層沉積(atomic layer deposition；ALD)的氮化矽(Si3N4)，並通過非等向性蝕刻製程例如RIE成形該共形層，該蝕刻製程自水準表面例如半導體層32的該頂部表面優先移除該介電材料。構成側間隙壁34的材料可經選擇以相對側間隙壁34可選擇性移除犧牲閘極結構16、18、20。
側間隙壁34、硬遮罩層22，以及外介電間隙壁31可由相同的介電材料組成，且該共同的組成可經選擇以相對內介電間隙壁29的介電材料可選擇性移除該共同組成的介電材料。側間隙壁34可厚於外介電間隙壁31。在一個實施例中，側間隙壁34的厚度可大於或等於自共形層28形成的介電間隙壁29與自共形層30形成的介電間隙壁31的總厚度。
請參照第9圖，其中類似的元件符號表示第8圖中類似的特徵，且在下一製造階段，沉積襯裡層36，其覆蓋犧牲閘極結構16、18、20的垂直側壁15、犧牲閘極結構16、18、20的頂部表面上的硬遮罩層22，以及犧牲閘極結構16、18、20的相鄰對之間的間隙中的半導體層32的頂部表面33。襯裡層36可由介電材料組成，例如通過ALD沉積的氮化矽(Si3N4)。
沉積層間介電層38，其可由通過CVD沉積的二氧化矽(SiO2)組成。接著，執行蝕刻製程以相對層間介電層38選擇性移除犧牲閘極結構16、18、20，從而定義閘極開口，隨後將在該閘極開口中形成替代閘極電極。該蝕刻製程相對側間隙壁34、層間介電層38，以及鰭片10的材料選擇性移除構成犧牲閘極結構16、18、20的材料。在由犧牲閘極結構16、18、20空出的該閘極開口中形成替代閘極電極40、42、44。閘極電極40、42、44可由金屬例如鋁或鎢以及用以調節閾值電壓的一種或多種功函數金屬層組成。在鰭片10的該頂部表面上的該閘極開口中可形成閘極介電質(未顯示)。該閘極介電質可由介電材料組成，例如高k閘極介電材料如氧化鉿。
在層間介電層38中的垂直接觸開口中形成接觸46，以接觸該源/汲區的半導體層32。也在層間介電層38中的垂直接觸開口中形成接觸48，以接觸閘極電極40、42、44的閘極電極。接觸46、48可由例如鎢(W)組成。由介電材料組成的覆蓋層50覆蓋閘極電極40、42、44的 相應頂部表面。覆蓋層50可由介電材料組成，例如氮化矽(Si3N4)，且可由與構成側間隙壁34的介電材料相同的介電材料組成。
請參照第10圖，其中類似的元件符號表示第9圖中類似的特徵，且在下一製造階段，通過例如濕化學蝕刻相對閘極電極40、42、44、接觸46、48、內介電間隙壁29，以及層間介電層38選擇性移除側間隙壁34及覆蓋層50。通過移除側間隙壁34及覆蓋層50的該蝕刻製程可稍微凹入外介電間隙壁31。不過，相對側間隙壁34的寬度的外介電間隙壁31的小的寬度以及在半導體層32與介電間隙壁29之間的設置用以限制移除及凹入介電間隙壁31的程度。蝕刻深度自動停止於間隙壁29的頂部表面，其與半導體層32的頂部表面33共面。這種蝕刻深度控制的精確度提供關於隨後形成的氣隙間隙壁的下邊界的確定性及可重複性。間隙壁29自鰭片10的頂部表面13延伸至半導體層32的頂部表面33。
請參照第11圖，其中類似的元件符號表示第10圖中類似的特徵，且在下一製造階段，沉積介電層54，其以覆蓋層56填充由覆蓋層50空出的空間。覆蓋層56覆蓋並密封在移除側間隙壁34空出的空間中所定義的氣隙間隙壁58。氣隙間隙壁58可以接近1(真空介電常數)的有效介電常數為特徵，或者可由處於或接近大氣壓的空氣填充，可由處於或接近大氣壓的另一種氣體填充，或者可包含處於亞大氣壓的空氣或另一種氣體(例如，部分真 空)。由於尺寸的區別，由移除側間隙壁34空出的該空間的上開口在包含氣隙間隙壁58的該空間可被介電層54填充之前封閉。不過，在該開口封閉之前，介電層54的部分60沉積於層間介電層38、閘極電極40、42、44、接觸46、48以及介電間隙壁29、31的表面上作為圍繞氣隙間隙壁58的襯裡。
氣隙間隙壁58水準位於接觸46與閘極電極40、42、44的垂直側壁41之間。間隙壁29的存在提供預定的深度以在該預定深度上方移除側間隙壁34，並提供對氣隙間隙壁58相對閘極電極40、42、44的下邊界的位置的控制。氣隙間隙壁58在其底端與介電間隙壁29的頂部表面共同延伸，該頂部表面與半導體層32的頂部表面33共面。氣隙間隙壁58的部分垂直位於半導體層32的頂部表面33與閘極電極40、42、44的相應頂部表面43之間。
第11圖的代表性實施例中的該裝置結構是鰭式場效應電晶體(FinFET)，該電晶體的溝道區位於由鰭片10定義的該半導體本體的內部。在一個替代實施例中，可應用本發明的實施例以在平面場效應電晶體而不是鰭式場效應電晶體的裝置構造中形成氣隙間隙壁58。這些替代實施例的流程通常如第2至11圖中所示那樣執行，除了沒有鰭片10且所示製造階段發生於基板12的頂部表面上而不是發生於鰭片10的頂部表面上。在鄰近犧牲閘極結構16、18、20並最終鄰近閘極電極40、42、44的基板12中及/或上可形成源/汲區。用以形成該場效應電晶體的基板 12的部分將表示由例如類似溝槽隔離14的溝道隔離區隔離的半導體本體。在一個替代實施例中，閘極結構16、18、20可不是犧牲的，以使流程不包括用閘極電極40、42、44替代閘極結構16、18、20。
上述方法用於積體電路晶片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，該晶片設于單晶片封裝件中(例如塑膠承載件，其具有附著至主機板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，可將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。
本文中引用術語例如“垂直”、“水準”、“橫向”等作為示例來建立參考框架，並非限制。術語例如“水準”及“橫向”是指與半導體基板的頂部表面平行的平面中的方向，而不論其實際的三維空間取向。術語例如“垂直”及“正交”是指垂直于該“水準”及“橫向”方向的方向。術語例如“上方”及“下方”表示元件或結構相對彼此以及/或者相對該半導體基板的頂部表面的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵 可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭示的實施例。許多修改及變更對於所屬技術領域中具有通常知識者將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使所屬技術領域中具有通常知識者能夠理解本文中所揭示的實施例。

Claims (20)

  1. 一種方法，包括：在半導體本體的頂部表面上形成閘極結構；鄰近該閘極結構的垂直側壁形成第一介電間隙壁；在該半導體本體的該頂部表面上形成相對該閘極結構的該垂直側壁佈置的半導體層，以使該第一介電間隙壁的第一部分水平位於該半導體層與該閘極結構的該垂直側壁之間；移除位於該半導體層的頂部表面上方的該第一介電間隙壁的第二部分；以及在移除該第一介電間隙壁的該第二部分處的空間中形成氣隙間隙壁。
  2. 如申請專利範圍第1項所述之方法，更包括：用閘極電極替代該閘極結構；以及形成延伸至該半導體層的該頂部表面的接觸，其中，該氣隙間隙壁水平位於該接觸與該閘極電極的垂直側壁之間。
  3. 如申請專利範圍第2項所述之方法，其中，在移除該第一介電間隙壁的該第二部分處的該空間中形成該氣隙間隙壁更包括：在用該閘極電極替代該閘極結構之前，鄰近該閘極結構的該垂直側壁形成第二介電間隙壁，其位於該第一介電間隙壁的該第一部分上方以及該半導體層的 該頂部表面上方。
  4. 如申請專利範圍第3項所述之方法，其中，在移除該第一介電間隙壁的該第二部分處的該空間中形成該氣隙間隙壁更包括：在形成該接觸以後，相對該第一介電間隙壁的該第一部分選擇性移除該第二介電間隙壁，以形成該氣隙間隙壁。
  5. 如申請專利範圍第1項所述之方法，其中，在移除該第一介電間隙壁的該第二部分處的該空間中形成該氣隙間隙壁更包括：鄰近該閘極結構的該垂直側壁形成第二介電間隙壁，其位於該第一介電間隙壁的該第一部分上方以及該半導體層的該頂部表面上方。
  6. 如申請專利範圍第5項所述之方法，在移除該第一介電間隙壁的該第二部分處的該空間中形成該氣隙間隙壁更包括：在形成該第二介電間隙壁以後，形成延伸至該半導體層的該頂部表面的接觸；以及在形成該接觸以後，相對該第一介電間隙壁的該第一部分選擇性移除該第二介電間隙壁，以形成該氣隙間隙壁。
  7. 如申請專利範圍第6項所述之方法，更包括：在形成該第二介電間隙壁以後，用閘極電極替代該閘極結構， 其中，該氣隙間隙壁水平位於該接觸與該閘極電極的垂直側壁之間。
  8. 如申請專利範圍第1項所述之方法，其中，該半導體本體為鰭片，且該半導體層形成於該鰭片的源/汲區上。
  9. 如申請專利範圍第1項所述之方法，更包括：在形成該第一介電間隙壁以後，鄰近該閘極結構的該垂直側壁形成第二介電間隙壁，其中，該第一介電間隙壁的該第一部分水平位於該半導體層與該第二介電間隙壁的該第一部分之間。
  10. 如申請專利範圍第9項所述之方法，更包括：在移除該第一介電間隙壁的該第二部分之前，移除位於該半導體層的該頂部表面上方的該第二介電間隙壁的第二部分。
  11. 如申請專利範圍第9項所述之方法，更包括：在形成該第一介電間隙壁及該第二介電間隙壁之前，形成圖案化硬遮罩層堆疊，其包括第一硬遮罩層、位於該第一硬遮罩層上的第二硬遮罩層，以及位於該第二硬遮罩層上的第三硬遮罩層，其中，利用該硬遮罩層堆疊形成該閘極結構。
  12. 如申請專利範圍第11項所述之方法，更包括：在移除該第一介電間隙壁的該第二部分之前，移除位於該半導體層的該頂部表面上方的該第二介電間隙壁的第二部分，其中，當移除該第二介電間隙壁的該第二部分 時，移除該第三硬遮罩層。
  13. 如申請專利範圍第12項所述之方法，其中，當自該閘極結構的該垂直側壁移除該第二介電間隙壁的該第二部分時，該第一介電間隙壁的該第二部分掩蔽該硬遮罩層堆疊。
  14. 如申請專利範圍第12項所述之方法，其中，當移除該第一介電間隙壁的該第二部分時移除該第二硬遮罩層，且更包括：在移除該第一介電間隙壁的該第二部分處的該空間中形成第三介電間隙壁，其中，通過自該空間移除該第三介電間隙壁形成該氣隙間隙壁。
  15. 一種結構，包括：半導體本體，具有頂部表面，閘極電極，位於該半導體本體的該頂部表面上，該閘極電極具有垂直側壁；半導體層，位於該半導體本體的該頂部表面上，該半導體層具有頂部表面；第一介電間隙壁，位於該半導體層與該閘極電極的該垂直側壁之間，該第一介電間隙壁自該半導體本體的該頂部表面延伸至該半導體層的該頂部表面；接觸，與該半導體層的該頂部表面連接；以及氣隙間隙壁，水平位於該接觸與該閘極電極的該垂直側壁之間， 其中，該氣隙間隙壁垂直延伸至該半導體層的該頂部表面。
  16. 如申請專利範圍第15項所述之結構，更包括：第二介電間隙壁，位於該半導體層與該第一介電間隙壁之間，其中，該第二介電間隙壁位於該半導體本體的該頂部表面上，且該第二介電間隙壁垂直位於該半導體層的該頂部表面下方。
  17. 如申請專利範圍第16項所述之結構，其中，該第一介電間隙壁水平位於該第二介電間隙壁與該閘極電極的該垂直側壁之間，該第一介電間隙壁由二氧化矽組成，且該第二介電間隙壁由氮化矽組成。
  18. 如申請專利範圍第16項所述之結構，其中，該第一介電間隙壁位於該第二介電間隙壁與該閘極電極的該垂直側壁之間，該第一介電間隙壁具有厚度，且該氣隙間隙壁具有大於該第一介電間隙壁的該厚度的厚度。
  19. 如申請專利範圍第16項所述之結構，其中，該第一介電間隙壁位於該第二介電間隙壁與該閘極電極的該垂直側壁之間，該第一介電間隙壁由二氧化矽組成，且該第二介電間隙壁由氮化矽組成。
  20. 如申請專利範圍第15項所述之結構，其中，該半導體本體為鰭片，且該半導體層為該鰭片的源/汲區的部分。
TW106135332A 2016-12-13 2017-10-16 場效應電晶體的氣隙間隙壁 TWI657538B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/376,831 2016-12-13
US15/376,831 US10319627B2 (en) 2016-12-13 2016-12-13 Air-gap spacers for field-effect transistors

Publications (2)

Publication Number Publication Date
TW201834145A true TW201834145A (zh) 2018-09-16
TWI657538B TWI657538B (zh) 2019-04-21

Family

ID=62489581

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106135332A TWI657538B (zh) 2016-12-13 2017-10-16 場效應電晶體的氣隙間隙壁

Country Status (3)

Country Link
US (2) US10319627B2 (zh)
CN (1) CN108231764B (zh)
TW (1) TWI657538B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111261703A (zh) * 2018-11-30 2020-06-09 台湾积体电路制造股份有限公司 半导体器件及制造方法
TWI717970B (zh) * 2020-01-14 2021-02-01 華邦電子股份有限公司 半導體結構以及其形成方法
TWI721690B (zh) * 2019-12-06 2021-03-11 華邦電子股份有限公司 記憶體結構及其製造方法
US11101177B1 (en) 2020-02-19 2021-08-24 Winbond Electronics Corp. Semiconductor structure and method for forming the same
US11355616B2 (en) 2019-10-31 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Air spacers around contact plugs and method forming same

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522642B2 (en) * 2016-12-14 2019-12-31 Taiwan Semiconductor Manufacturing Co. Ltd. Semiconductor device with air-spacer
US10290549B2 (en) * 2017-09-05 2019-05-14 Globalfoundries Inc. Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same
US10170582B1 (en) * 2017-09-13 2019-01-01 International Business Machines Corporation Uniform bottom spacer for vertical field effect transistor
KR102399071B1 (ko) 2017-11-17 2022-05-17 삼성전자주식회사 반도체 장치
US10211092B1 (en) * 2018-01-28 2019-02-19 International Business Machines Corporation Transistor with robust air spacer
US10431500B1 (en) * 2018-03-27 2019-10-01 Globalfoundries Inc. Multi-step insulator formation in trenches to avoid seams in insulators
CN110581101B (zh) 2018-06-07 2022-01-11 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US10608096B2 (en) * 2018-06-11 2020-03-31 International Business Machines Corporation Formation of air gap spacers for reducing parasitic capacitance
US10854503B2 (en) 2018-07-16 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with air gap and method sealing the air gap
US10714342B2 (en) * 2018-07-31 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN110858578B (zh) * 2018-08-23 2021-07-13 联华电子股份有限公司 管芯封环及其制造方法
US10985076B2 (en) * 2018-08-24 2021-04-20 International Business Machines Corporation Single metallization scheme for gate, source, and drain contact integration
WO2020052630A1 (en) * 2018-09-14 2020-03-19 Changxin Memory Technologies, Inc. Semiconductor device and methods for manufacturing thereof
US11508827B2 (en) * 2018-09-26 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Air spacer for a gate structure of a transistor
US10825721B2 (en) * 2018-10-23 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating cap on contact structure and method for forming the same
US10910273B2 (en) 2019-02-25 2021-02-02 International Business Machines Corporation Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
US11145540B2 (en) * 2019-08-08 2021-10-12 Nanya Technology Corporation Semiconductor structure having air gap dielectric and the method of preparing the same
KR20210038762A (ko) * 2019-09-30 2021-04-08 삼성전자주식회사 반도체 장치
US11901220B2 (en) 2019-12-20 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Bilayer seal material for air gaps in semiconductor devices
CN113013100A (zh) * 2019-12-20 2021-06-22 台湾积体电路制造股份有限公司 用于形成半导体器件的方法
TWI786548B (zh) * 2020-02-27 2022-12-11 台灣積體電路製造股份有限公司 半導體裝置及其形成方法
US11289585B2 (en) 2020-02-27 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of formation
US11164795B2 (en) * 2020-03-24 2021-11-02 Globalfoundries U.S. Inc. Transistors with source/drain regions having sections of epitaxial semiconductor material
US11349014B2 (en) * 2020-06-30 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Air spacer and method of forming same
US11557510B2 (en) 2020-07-30 2023-01-17 Taiwan Semiconductor Manufacturing Co., Ltd. Spacers for semiconductor devices including backside power rails
US11374093B2 (en) * 2020-11-25 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and methods of forming the same
CN113192828B (zh) * 2021-04-29 2023-04-11 长鑫存储技术有限公司 半导体结构的制备方法和半导体结构

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859089A (en) 1997-07-01 1999-01-12 The Kerr Corporation Dental restorative compositions
US6180988B1 (en) * 1997-12-04 2001-01-30 Texas Instruments-Acer Incorporated Self-aligned silicided MOSFETS with a graded S/D junction and gate-side air-gap structure
US5869374A (en) 1998-04-22 1999-02-09 Texas Instruments-Acer Incorporated Method to form mosfet with an inverse T-shaped air-gap gate structure
US6127251A (en) 1998-09-08 2000-10-03 Advanced Micro Devices, Inc. Semiconductor device with a reduced width gate dielectric and method of making same
KR20010011638A (ko) * 1999-07-29 2001-02-15 김영환 반도체장치의 구조 및 그 제조방법
TW462122B (en) 2000-12-18 2001-11-01 United Microelectronics Corp Air gap semiconductor structure and the manufacturing method thereof
TW476135B (en) 2001-01-09 2002-02-11 United Microelectronics Corp Manufacture of semiconductor with air gap
US7442609B2 (en) * 2004-09-10 2008-10-28 Infineon Technologies Ag Method of manufacturing a transistor and a method of forming a memory device with isolation trenches
US7741663B2 (en) 2008-10-24 2010-06-22 Globalfoundries Inc. Air gap spacer formation
JP5531812B2 (ja) * 2010-06-23 2014-06-25 富士通セミコンダクター株式会社 Ｍｏｓトランジスタおよびその製造方法、半導体集積回路装置
US8637930B2 (en) * 2011-10-13 2014-01-28 International Business Machines Company FinFET parasitic capacitance reduction using air gap
KR101917815B1 (ko) * 2012-05-31 2018-11-13 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US8946791B2 (en) * 2012-08-31 2015-02-03 International Business Machines Corporation Finfet with reduced parasitic capacitance
US9275911B2 (en) * 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US9064948B2 (en) * 2012-10-22 2015-06-23 Globalfoundries Inc. Methods of forming a semiconductor device with low-k spacers and the resulting device
US8847401B2 (en) * 2012-10-31 2014-09-30 International Business Machines Corporation Semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure
US8841711B1 (en) 2013-03-12 2014-09-23 Globalfoundries Inc. Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
US9871121B2 (en) * 2014-03-10 2018-01-16 Qualcomm Incorporated Semiconductor device having a gap defined therein
JP6249888B2 (ja) * 2014-06-19 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置
US9443956B2 (en) * 2014-12-08 2016-09-13 Globalfoundries Inc. Method for forming air gap structure using carbon-containing spacer
US9412659B1 (en) * 2015-01-29 2016-08-09 Globalfoundries Inc. Semiconductor structure having source/drain gouging immunity
US9484250B2 (en) * 2015-03-10 2016-11-01 International Business Machines Corporation Air gap contact formation for reducing parasitic capacitance
KR102452593B1 (ko) * 2015-04-15 2022-10-11 삼성전자주식회사 반도체 장치의 제조 방법
EP3926688A1 (en) * 2015-07-17 2021-12-22 Intel Corporation Transistor with airgap spacer
US9362355B1 (en) * 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer
US9786737B2 (en) * 2015-12-03 2017-10-10 International Business Machines Corporation FinFET with reduced parasitic capacitance
US9716154B2 (en) * 2015-12-17 2017-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having a gas-filled gap
US10164029B2 (en) * 2015-12-18 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9627514B1 (en) * 2015-12-28 2017-04-18 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10573749B2 (en) * 2016-02-25 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
US9716158B1 (en) * 2016-03-21 2017-07-25 International Business Machines Corporation Air gap spacer between contact and gate region
US9735246B1 (en) * 2016-05-11 2017-08-15 International Business Machines Corporation Air-gap top spacer and self-aligned metal gate for vertical fets
US9608065B1 (en) * 2016-06-03 2017-03-28 International Business Machines Corporation Air gap spacer for metal gates
US9892961B1 (en) * 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111261703A (zh) * 2018-11-30 2020-06-09 台湾积体电路制造股份有限公司 半导体器件及制造方法
US10861746B2 (en) 2018-11-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device
TWI728542B (zh) * 2018-11-30 2021-05-21 台灣積體電路製造股份有限公司 半導體裝置的製造方法
CN111261703B (zh) * 2018-11-30 2023-04-25 台湾积体电路制造股份有限公司 半导体器件及制造方法
US11355616B2 (en) 2019-10-31 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Air spacers around contact plugs and method forming same
TWI721690B (zh) * 2019-12-06 2021-03-11 華邦電子股份有限公司 記憶體結構及其製造方法
TWI717970B (zh) * 2020-01-14 2021-02-01 華邦電子股份有限公司 半導體結構以及其形成方法
US11101177B1 (en) 2020-02-19 2021-08-24 Winbond Electronics Corp. Semiconductor structure and method for forming the same

Also Published As

Publication number Publication date
US20190198381A1 (en) 2019-06-27
TWI657538B (zh) 2019-04-21
US10923389B2 (en) 2021-02-16
US10319627B2 (en) 2019-06-11
CN108231764B (zh) 2021-11-26
US20180166319A1 (en) 2018-06-14
CN108231764A (zh) 2018-06-29

Similar Documents

Publication Publication Date Title
TWI657538B (zh) 場效應電晶體的氣隙間隙壁
US8445340B2 (en) Sacrificial offset protection film for a FinFET device
US10868179B2 (en) Fin-type field effect transistor structure and manufacturing method thereof
US10685889B2 (en) Semiconductor structures and fabrication methods thereof
US10872965B2 (en) Method of forming semiconductor structure
US8962430B2 (en) Method for the formation of a protective dual liner for a shallow trench isolation structure
CN103474397A (zh) 制造finfet器件的方法
US8722501B2 (en) Method for manufacturing multi-gate transistor device
US10361310B2 (en) Method of fabricating semiconductor devices
CN105280641B (zh) 用于集成电路的结构和方法
US20150200275A1 (en) Finfet and method for manufacturing the same
US9793174B1 (en) FinFET device on silicon-on-insulator and method of forming the same
WO2014023047A1 (zh) FinFET及其制造方法
TW201703140A (zh) 半導體裝置及其製作方法
US10734381B2 (en) Fin-FET devices
WO2013166733A1 (zh) FinFET及其制造方法
US10008582B2 (en) Spacers for tight gate pitches in field effect transistors
TWI728688B (zh) 具有擴散阻擋間隔件區段之場效電晶體
TWI697121B (zh) 三閘極場效電晶體
CN116825637A (zh) 半导体结构及其形成方法
CN112951725A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees