CN113451308A - 源极/漏极区具有外延半导体材料区段的晶体管 - Google Patents
源极/漏极区具有外延半导体材料区段的晶体管 Download PDFInfo
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Abstract
本发明涉及源极/漏极区具有外延半导体材料区段的晶体管,揭示场效应晶体管的结构以及形成场效应晶体管的结构的方法。第一及第二栅极结构延伸于半导体本体上方。源极/漏极区横向位于该第一栅极结构与该第二栅极结构之间。该源极/漏极区包括具有第一区段、第二区段以及第三区段的半导体层。该半导体本体的第一部分位于该半导体层的该第一区段与该半导体层的该第二区段之间。该半导体本体的第二部分位于该半导体层的该第二区段与该半导体层的该第三区段之间。
Description
技术领域
本发明涉及半导体装置制造及集成电路,尤其涉及用于场效应晶体管的结构以及形成用于场效应晶体管的结构的方法。
背景技术
可使用互补金属氧化物半导体(complementary-metal-oxide-semiconductor;CMOS)制程来建立p型与n型场效应晶体管的组合,将该p型与n型场效应晶体管用作装置,以构建例如逻辑单元(logic cell)。场效应晶体管通常包括源极、漏极、位于该源极与漏极之间的沟道区、以及与该沟道区叠置的栅极电极。当向该栅极电极施加超过特征阈值电压的控制电压时,在该源极与漏极之间的该沟道区中发生载流子流,从而产生装置输出电流。场效应晶体管可包括与多个沟道区叠置的多个栅极。
一种形成场效应晶体管的源极及漏极的方法是向半导体本体的区域中注入含有p型掺杂物或n型掺杂物的离子,以提供源极及漏极。另一种方法是从该半导体本体的区域外延生长半导体材料区段,以提供源极及漏极。可用p型掺杂物或n型掺杂物在外延生长期间原位掺杂该半导体材料。
与多栅极场效应晶体管中的宽栅极间距相关的问题是为提供源极及漏极而在腔体中外延生长的半导体材料的填充不足(underfilling)。该填充不足可能降低装置性能,例如降低射频性能指标,如功率增益。该填充不足还可能降低其它性能指标。例如,可能减少晶体管偏置于饱和区时的漏极电流(Idsat)。可能增加源极及漏极的接触电阻,且该填充不足还可能引起接触断开(contact open)问题。
需要改进的用于场效应晶体管的结构以及形成用于场效应晶体管的结构的方法。
发明内容
在本发明的一个实施例中,提供一种用于场效应晶体管的结构。该结构包括延伸于半导体本体上方的第一及第二栅极结构,以及横向位于该第一栅极结构与该第二栅极结构之间的源极/漏极区。该源极/漏极区包括具有第一区段、第二区段以及第三区段的半导体层。该半导体本体的第一部分位于该半导体层的该第一区段与该半导体层的该第二区段之间。该半导体本体的第二部分位于该半导体层的该第二区段与该半导体层的该第三区段之间。
在本发明的一个实施例中,提供一种形成用于场效应晶体管的结构的方法。该方法包括形成延伸于半导体本体上方的第一及第二栅极结构,以及形成横向位于该第一栅极结构与该第二栅极结构之间的半导体层的第一区段、第二区段以及第三区段。该半导体本体的部分位于该半导体层的该第一区段与该半导体层的该第二区段之间。该半导体本体的第二部分位于该半导体层的该第二区段与该半导体层的该第三区段之间。该半导体层的该第一区段、该第二区段以及该第三区段是该场效应晶体管的源极/漏极区的组成部分。
附图说明
包含于并构成本说明书的一部分的附图示例说明本发明的各种实施例,并与上面所作的有关本发明的概括说明以及下面所作的有关这些实施例的详细说明一起用以解释本发明的这些实施例。在这些附图中,类似的附图标记表示不同视图中类似的特征。
图1-4显示依据本发明的实施例处于处理方法的连续制造阶段的场效应晶体管的结构的剖视图。
图5显示处于图4之后的该处理方法的制造阶段的该结构的剖视图。
图5A、5B、5C显示沿大体平行于栅极结构的纵轴所作的图5的结构的不同部分的剖视图。
图6显示处于图5之后的该处理方法的制造阶段的该结构的剖视图。
图7显示依据本发明的替代实施例的结构的剖视图。
具体实施方式
请参照图1并依据本发明的实施例,场效应晶体管的结构10包括设于衬底14上方并从该衬底向上突出的鳍片12。鳍片12及衬底14可由单晶半导体材料组成,例如单晶硅。鳍片12可通过利用光刻及蚀刻制程图案化衬底14形成,或者通过自对准多重图案化制程形成。浅沟槽隔离16(图5A、5B、5C)可围绕鳍片12的下方区段60。在浅沟槽隔离16的顶部表面之上显露鳍片12的上方区段62。鳍片12定义可用以形成场效应晶体管的半导体本体。鳍片12的上方区段62包括顶部表面11及侧表面13。
栅极结构18在鳍片12上方并横越鳍片12以及在浅沟槽隔离16上沿着各自的纵轴而横向延伸。各栅极结构18横向于鳍片12对准,叠置并包覆鳍片12的上方区段62的顶部表面11及侧表面13。各栅极结构18可包括由导体(例如多晶硅)组成的伪栅极20,以及由介电材料(例如二氧化硅)组成的介电层22。在各栅极结构18上方可设置栅极覆盖体21。
邻近各栅极结构18的侧表面或侧壁19设置侧间隙壁24。侧间隙壁24可通过沉积由介电材料(例如低k介电材料)组成的共形层并利用非等向性蚀刻制程(例如反应离子蚀刻)蚀刻所沉积的共形层形成。
掺杂区26、28可形成于鳍片12中并横向设置于相邻对的栅极结构18上的侧间隙壁24之间。掺杂区26、28含有一定浓度的n型或p型掺杂物。掺杂区26、28可通过引入能量离子的离子注入制程形成,如单箭头示意标示,离子轨迹停止于鳍片12中的一定深度范围内。可从合适的源气体生成该离子,并利用离子注入工具以给定的注入条件注入鳍片12中。可选择注入条件(例如,离子种类、剂量、动能、倾斜角度)以调节掺杂区26、28的特性(例如,深度分布)。在用以形成其它类型的场效应晶体管的衬底14的区域(未显示)上方可临时形成注入掩膜。掺杂区26、28相对于鳍片12的顶部表面11延伸至深度d。
在一个实施例中,可通过注入提供p型导电性的p型掺杂物的离子(例如,硼)在鳍片12中同时形成掺杂区26、28。在一个替代实施例中,可通过注入提供n型导电性的n型掺杂物的离子(例如,磷及/或砷)在鳍片12中同时形成掺杂区26、28。在一个实施例中,掺杂区26、28的掺杂物浓度可相等或基本上相等。栅极结构18及侧间隙壁24可用以自对准在鳍片12中形成掺杂区26、28的该离子注入制程。
在一个替代实施例中,可从该装置构造省略掺杂区26、28,从而不改变鳍片12的初始掺杂(若有的话)。
请参照图2,其中,类似的附图标记表示图1中类似的特征,且在下一制造阶段,共形层30沉积在栅极结构18上的栅极覆盖体21、侧间隙壁24、以及掺杂区26、28上方的鳍片12的顶部表面11上方作为衬里。共形层30可由金属(例如钽、氮化钽、钛或氮化钛)组成,并可通过例如原子层沉积来沉积。共形层30的材料可经选择以不同于栅极覆盖体21及侧间隙壁24的材料,以便于促进后续的蚀刻制程。可以共形厚度t(其与位置无关)沉积共形层30。
通过在栅极结构18上的栅极覆盖体21、侧间隙壁24、以及掺杂区26、28上的共形层30上方沉积共形层,并通过非等向性蚀刻制程蚀刻来形成间隙壁32。间隙壁32可由例如非晶碳、二氧化硅、氮化硅或金属氧化物组成,并可通过例如原子层沉积来沉积。该蚀刻制程可为反应离子蚀刻制程,其相对于组成共形层30的材料而选择性蚀刻组成间隙壁32的材料。在提到材料移除制程(例如,蚀刻)时,本文中所使用的术语“选择性”表示目标材料的材料移除速率(也就是,蚀刻速率)高于暴露于该材料移除制程的至少另一种材料的材料移除速率(也就是,蚀刻速率)。间隙壁32具有由被蚀刻的共形层的厚度所建立的宽度。
请参照图3,其中,类似的附图标记表示图2中类似的特征,且在下一制造阶段,利用非等向性蚀刻制程蚀刻共形层30(图2)。该蚀刻制程可为反应离子蚀刻制程,其相对于鳍片12、栅极覆盖体21、侧间隙壁24以及间隙壁32的材料选择性蚀刻构成共形层30的材料。间隙壁32(其为临时结构组件并可通过该蚀刻制程缩短)掩蔽共形层30的下方部分。除了共形层30的被掩蔽部分以外,通过该蚀刻制程移除共形层30。共形层30的未移除部分可具有与间隙壁32的宽度相等或基本上相等的宽度w1。
在间隙壁32与侧间隙壁24之间定义开口34。开口34沿垂直方向延伸至各掺杂区26、28上方的鳍片12的顶部表面11。由于通过该蚀刻制程完全移除共形层30的上覆部分,因此在开口34的底部暴露出鳍片12的顶部表面11。
请参照图4,其中,类似的附图标记表示图3中类似的特征,且在下一制造阶段,在各相邻对的栅极结构18之间的鳍片12中形成腔体36、38、40。腔体36、38、40可延伸给定深度d2至鳍片12中。可通过相对于栅极覆盖体21、侧间隙壁24以及间隙壁32的材料具有选择性的蚀刻制程形成腔体36、38、40。间隙壁32在该蚀刻制程期间充当保护覆盖体,以掩蔽并维持鳍片12的部分41、43。鳍片12的部分41横向位于腔体36与腔体38之间,且鳍片12的部分43横向位于腔体38与腔体40之间。在该蚀刻制程期间可能部分消耗并由此缩短间隙壁32。鳍片12的部分41、43可具有相等或基本上相等的宽度w2。共形层30的部分位于鳍片12的各部分41、43上方的鳍片12的顶部表面11上,且部分41、43的宽度w2可等于或基本上等于共形层30的上覆部分的宽度w1。
腔体36、38、40的形成移除与鳍片12的部分41、43相邻的掺杂区26、28的部分。掺杂区26的部分在一对栅极结构18之间的鳍片12的各自的部分41、43内保持完好,且掺杂区28的部分在另一对栅极结构18之间的鳍片12的各自的部分41、43内保持完好。掺杂区26、28的部分可具有与深度d1(图1)基本上相等的厚度。在一个实施例中,腔体38、40的深度d2可大于掺杂区26、28的厚度。
请参照图5、5A、5B、5C,其中,类似的附图标记表示图4中类似的特征,且在下一制造阶段,利用相对于鳍片12、栅极覆盖体21、侧间隙壁24以及共形层30的材料具有选择性的蚀刻制程移除间隙壁32。该选择性蚀刻制程可为反应蚀刻制程。通过移除间隙壁32而暴露出的共形层30的部分未被移除,而是保留于鳍片12的部分41、43上方的顶部表面11上。
从与腔体36、38、40接壤的鳍片12的表面,尤其从腔体38、40之间的鳍片12的部分41、43的侧表面13,以各自的区段形式生长含有外延半导体材料的层42。外延半导体层42的区段独立生长于各腔体36、38、40内部,从而共同为外延生长提供与单个大腔体相比显著较大的表面积。外延半导体层42可从栅极结构18之间的空间横向延伸。外延半导体层42的各区段部分地位于腔体36、38、40的其中之一中,并部分地延伸于鳍片12的顶部表面11之上。外延半导体层42的不同区段在鳍片12的部分41、43以及位于鳍片12的部分41、43上方的共形层30的部分上方合并。共形层30的部分可被封入外延半导体层42的内部。
该外延生长制程可为选择性的,因为该半导体材料不从介电表面(例如浅沟槽隔离16、栅极覆盖体21以及侧间隙壁24的表面)生长。可用一定浓度的掺杂物在外延生长期间原位掺杂外延半导体层42。在一个实施例中,外延半导体层42可具有与掺杂区26、28相同的导电类型。在一个实施例中,可用提供n型导电性的n型掺杂物(例如磷及/或砷)在外延生长期间原位掺杂外延半导体层42。在一个替代实施例中,可用提供p型导电性的p型掺杂物(例如硼)在外延生长期间原位掺杂外延半导体层42。外延半导体层42可具有含有锗及硅的组成,且在一个实施例中,外延半导体层42可由硅-锗组成。在一个实施例中,外延半导体层42可由硅-锗组成,且可含有p型掺杂物(例如,硼)。在一个替代实施例中,外延半导体层42可由硅组成,并可含有n型掺杂物(例如,磷)。
在各组腔体36、38、40中的外延半导体层42的区段接触在腔体36与腔体38之间的鳍片12的部分41,以及在腔体38与腔体40之间的鳍片12的部分43。在各腔体36中的外延半导体层42的区段可与鳍片12的部分41的一个侧表面13直接接触,在各腔体38中的外延半导体层42的区段可与鳍片12的部分41的一个侧表面13以及鳍片12的部分43的一个侧表面13直接接触,且在各腔体40中的外延半导体层42的区段可与鳍片12的部分43的一个侧表面13直接接触。掺杂区26的部分或掺杂区28的部分被包括于共形层30的部分下方的鳍片12的部分41、43中。鳍片12的部分41定义腔体36中的外延半导体层42的区段与腔体38中的外延半导体层42的区段之间的分隔。鳍片12的部分43定义腔体38中的外延半导体42的区段与腔体40中的外延半导体层42的区段之间的分隔。
请参照图6,其中,类似的附图标记表示图5中类似的特征,且在下一制造阶段,执行替代栅极制程,以用栅极结构46、47、48替代栅极结构18,并完成该场效应晶体管的结构10。栅极结构46、47、48可包括由一种或多种金属栅极材料(例如功函数金属)组成的电极层64,以及由介电材料(例如高k介电材料,如氧化铪)组成的栅极介电层66。栅极结构46、47、48具有相对的侧表面49,且侧间隙壁24与侧表面49相邻。
结构10包括由外延半导体层42的区段、鳍片12的部分41、43、以及位于鳍片12的部分41、43中的掺杂区26所提供的源极/漏极区50。结构10包括由外延半导体层42的区段、鳍片12的部分41、43、以及位于鳍片12的部分41、43中的掺杂区28所提供的源极/漏极区52。本文中所使用的术语“源极/漏极区”是指可充当场效应晶体管的源极或漏极的半导体材料掺杂区。在一个实施例中,源极/漏极区50可提供结构10中的源极,且源极/漏极区52可提供结构10中的漏极。在一个替代实施例中,源极/漏极区50可提供结构10中的漏极,且源极/漏极区52可提供结构10中的源极。源极/漏极区50、52经掺杂以具有相同极性的导电类型。
源极/漏极区50位于栅极结构46的侧表面49与栅极结构47的侧表面49之间,且源极/漏极区52位于栅极结构47的侧表面49与栅极结构48的侧表面49之间。鳍片12提供用以形成源极/漏极区50、52的半导体本体。沟道区55设于源极/漏极区50与源极/漏极区52之间以及上覆栅极结构47下方的鳍片12的部分中。
接着执行中间工艺制程及后端工艺制程,包括形成接触、过孔、以及与该场效应晶体管耦接的互连结构的线路。位于该互连结构的层间介电层58中的接触56与源极/漏极区50、52耦接。
源极/漏极区50、52可通过外延半导体层42的外延半导体材料在填充方面呈现改进。依赖一组较小的腔体36、38、40而不是单个较大的腔体通过外延生长的半导体材料提供较小的填充体积,并可补偿较大的栅极间距,以减轻填充不足。由于分段形成及填充不足的减轻,源极/漏极区50、52可包括较大的总体体积的外延半导体材料。结构10可包括具有较宽栅极间距的额外栅极结构,且可针对成对的栅极结构重复源极/漏极区50、52,以形成用于射频集成电路的多栅极场效应晶体管。向源极/漏极区50、52添加由金属组成的共形层30的部分可用以降低源极/漏极区50、52的接触电阻。
请参照图7,其中,类似的附图标记表示图6中类似的特征,并依据替代实施例,间隙壁32的宽度及/或共形层30的厚度可用以调节各组腔体36、38、40中的外延半导体层42的各区段的宽度以及鳍片12的部分41、43的宽度。例如并如图7中所示的源极/漏极区50,可增加间隙壁32的宽度,并且还可增加共形层30的厚度,以适应较宽的栅极间距。尽管未显示,但可以与源极/漏极区50类似的方式修改源极/漏极区52。可调节间隙壁32的宽度以及共形层30的厚度,以源极/漏极针对栅极结构46、47、48的不同栅极间距调整源极/漏极区50、52的形成。
上述方法用于集成电路芯片的制造。制造者可以原始晶圆形式(例如,作为具有多个未封装芯片的单个晶圆)、作为裸芯片、或者以封装形式分配所得的集成电路芯片。在后一种情况中,该芯片安装于单芯片封装件中(例如塑料承载件,其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如陶瓷承载件,其具有单面或双面互连或嵌埋互连)。在任何情况下,可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成,作为中间产品或最终产品的部分。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框架,并非限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面,而不论其实际的三维空间取向。术语“垂直”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指在该水平平面内的方向。
本文中引用的由近似语言例如“大约”、“大致”及“基本上”所修饰的术语不限于所指定的精确值。该近似语言可对应于用以测量该值的仪器的精度,且除非另外依赖于该仪器的精度,否则可表示所述值的+/-10%。
与另一个特征“连接”或“耦接”的特征可与该另一个特征直接连接或耦接,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可与另一个特征“直接连接”或“直接耦接”。如存在至少一个中间特征,则特征可与另一个特征“非直接连接”或“非直接耦接”。在另一个特征“上”或与其“接触”的特征可直接在该另一个特征上或与其直接接触,或者可存在一个或多个中间特征。如果不存在中间特征,则特征可直接在另一个特征“上”或与其“直接接触”。如存在至少一个中间特征,则特征可“不直接”在另一个特征“上”或与其“不直接接触”。
对本发明的各种实施例所作的说明是出于示例说明的目的,而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见,而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进,或者使本领域的普通技术人员能够理解本文中所揭示的实施例。
Claims (20)
1.一种用于场效应晶体管的结构,该结构包括:
半导体本体;
第一栅极结构,延伸于该半导体本体上方;
第二栅极结构,延伸于该半导体本体上方;以及
第一源极/漏极区,横向位于该第一栅极结构与该第二栅极结构之间,该第一源极/漏极区包括具有第一区段、第二区段以及第三区段的第一半导体层,
其中,该半导体本体包括第一部分及第二部分,该半导体本体的该第一部分位于该第一半导体层的该第一区段与该第一半导体层的该第二区段之间,且该半导体本体的该第二部分位于该第一半导体层的该第二区段与该第一半导体层的该第三区段之间。
2.如权利要求1所述的结构,其中,该半导体本体包括第一腔体、第二腔体、以及第三腔体,该第一半导体层的该第一区段位于该第一腔体中,该第一半导体层的该第二区段位于该第二腔体中,以及该第一半导体层的该第三区段位于该第三腔体中。
3.如权利要求2所述的结构,其中,位于该第二腔体中的该第一半导体层的该第二区段与该半导体本体的该第二部分直接接触,并与该半导体本体的该第一部分直接接触。
4.如权利要求3所述的结构,其中,位于该第一腔体中的该第一半导体层的该第一区段与该半导体本体的该第一部分直接接触,且位于该第三腔体中的该第一半导体层的该第三区段与该半导体本体的该第二部分直接接触。
5.如权利要求2所述的结构,其中,该半导体本体为半导体鳍片。
6.如权利要求2所述的结构,其中,该半导体本体具有顶部表面,且该第一半导体层的该第一区段、该第二区段、以及该第三区段包括在该半导体本体的该顶部表面上方合并的各自的部分。
7.如权利要求1所述的结构,其中,该半导体本体的该第一部分包括含有第一掺杂物的第一掺杂区,该半导体本体的该第二部分包括含有该第一掺杂物的第二掺杂区,且该第一掺杂区与该第二掺杂区具有基本上相同的厚度。
8.如权利要求1所述的结构,其中,该半导体本体具有顶部表面,且还包括:
第二层,具有位于该半导体本体的该第一部分上方的该半导体本体的该顶部表面上的第一部分以及位于该半导体本体的该第二部分上方的该半导体本体的该顶部表面上的第二部分。
9.如权利要求8所述的结构,其中,该第一半导体层的该第一区段、该第二区段、以及该第三区段包括在该半导体本体的该顶部表面、该第二层的该第一部分、以及该第二层的该第二部分上方合并的各自的部分。
10.如权利要求8所述的结构,其中,该第二层由金属组成。
11.如权利要求8所述的结构,其中,该第二层的该第一部分及该第二部分直接位于该半导体本体的该顶部表面上。
12.如权利要求1所述的结构,还包括:
半导体衬底,
其中,该半导体本体是从该半导体衬底突出的半导体鳍片。
13.如权利要求1所述的结构,还包括:
接触,与该第一源极/漏极区连接。
14.如权利要求1所述的结构,还包括:
第二源极/漏极区,包括具有第一区段、第二区段以及第三区段的第二半导体层,
其中,该半导体本体包括第三部分及第四部分,该半导体本体的该第三部分位于该第二半导体层的该第一区段与该第二半导体层的该第二区段之间,该半导体本体的该第四部分位于该第二半导体层的该第二区段与该第二半导体层的该第三区段之间,且该第一栅极结构横向位于该第一源极/漏极区与该第二源极/漏极区之间。
15.一种形成用于场效应晶体管的结构的方法,该方法包括:
形成延伸于半导体本体上方的第一栅极结构;
形成延伸于该半导体本体上方的第二栅极结构;
形成横向位于该第一栅极结构与该第二栅极结构之间的半导体层的第一区段、第二区段、以及第三区段,
其中,该半导体本体包括第一部分及第二部分,该半导体本体的该第一部分位于该半导体层的该第一区段与该半导体层的该第二区段之间,该半导体本体的该第二部分位于该半导体层的该第二区段与该半导体层的该第三区段之间,且该半导体层的该第一区段、该第二区段、以及该第三区段是该场效应晶体管的源极/漏极区的组成部分。
16.如权利要求15所述的方法,还包括:
在该半导体本体中形成第一腔体、第二腔体、以及第三腔体,
其中,在该第一腔体中外延生长该半导体层的该第一区段,在该第二腔体中外延生长该半导体层的该第二区段,以及在该第三腔体中外延生长该半导体层的该第三区段。
17.如权利要求16所述的方法,其中,形成横向位于该第一栅极结构与该第二栅极结构之间的该半导体层的该第一区段、该第二区段、以及该第三区段包括:
在横向位于该第一栅极结构与该第二栅极结构之间的各自的位置的该半导体本体上形成第一间隙壁及第二间隙壁。
18.如权利要求17所述的方法,其中,在该半导体本体中形成该第一腔体、该第二腔体、以及该第三腔体包括:
利用该半导体本体上的该第一间隙壁及该第二间隙壁蚀刻该半导体本体,以在该半导体本体中形成该第一腔体、该第二腔体、以及该第三腔体。
19.如权利要求18所述的方法,其中,该半导体本体的该第一部分位于该第一间隙壁下方,且该半导体本体的该第二部分位于该第二间隙壁下方。
20.如权利要求18所述的方法,其中,在横向位于该第一栅极结构与该第一间隙壁之间的该半导体本体中形成该第一腔体,在横向位于该第一间隙壁与该第二间隙壁之间的该半导体本体中形成该第二腔体,以及在横向位于该第二间隙壁与该第二栅极结构之间的该半导体本体中形成该第三腔体。
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