TWI751604B - 一或多個埋藏多晶層上方之鰭型場效電晶體 - Google Patents

一或多個埋藏多晶層上方之鰭型場效電晶體 Download PDF

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TWI751604B
TWI751604B TW109122894A TW109122894A TWI751604B TW I751604 B TWI751604 B TW I751604B TW 109122894 A TW109122894 A TW 109122894A TW 109122894 A TW109122894 A TW 109122894A TW I751604 B TWI751604 B TW I751604B
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semiconductor layer
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西瓦Ｐ 阿度蘇米利
朱利安 弗羅吉爾
謝瑞龍
安東尼Ｋ 史塔佩爾
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭示具有改變的結晶性的結構以及與形成此類結構相關的方法。一種半導體層具有包含多晶半導體材料、缺陷及惰性氣體種類的原子的第一區域。在該半導體層的該第一區域上方設置多個鰭片。為形成該結構，可以惰性氣體離子注入該半導體層，以改性在第一區域以及在該第一區域與該半導體層的頂部表面之間的第二區域中的該半導體層的晶體結構。使用退火製程將該半導體層的該第一區域轉換為多晶狀態，並將該半導體層的該第二區域轉換為單晶狀態。自該半導體層的該第二區域以及該半導體層的該第二區域上方磊晶生長的另一個半導體層圖案化該鰭片。

Description

一或多個埋藏多晶層上方之鰭型場效電晶體
本發明係關於半導體裝置製造及積體電路，尤其關於在半導體裝置下方具有改變的結晶性的結構以及與形成此類結構相關的方法。
與絕緣體上矽(silicon-on-insulator；SOI)基板相比，塊體矽基板的成本較低。一般來說，SOI基板包括由矽構成的薄裝置層、操作基板，以及將該裝置層與該操作基板物理隔開並電性隔離的薄埋藏氧化物(buried oxide；BOX)層。利用SOI技術製造的裝置與利用塊體矽基板構建的類似裝置相比可呈現一定程度的性能提升。例如，SOI基板的BOX層提供底部介電隔離，其可抑制亞通道洩漏(sub-channel leakage)。由塊體矽基板提供的不良裝置隔離可能會導致在射頻(RF)操作模式下的裝置之間的串擾(cross-talk)。
需要改進的結構來提供SOI基板沒有成本的優點，以及形成此類結構的方法。
在本發明的一個實施例中，一種結構包括：半導體層，具有包 含多晶半導體材料、複數個缺陷、以及惰性氣體種類的原子的區域。該結構還包括位於該半導體層的該區域上方的複數個鰭片。
在本發明的一個實施例中，一種方法包括：以惰性氣體種類的離子在深度範圍注入第一半導體層，以改性在第一區域以及在該第一區域與該第一半導體層的頂部表面之間的第二區域中的該第一半導體層的半導體材料的晶體結構；以及用退火製程退火該第一半導體層，以將該第一半導體層的該第一區域內的該半導體材料轉換為多晶狀態，並將該第一半導體層的該第二區域內的該半導體材料轉換為單晶狀態。在退火該第一半導體層以後，在該第一半導體層的該第二區域上方磊晶生長第二半導體層；以及圖案化該第二半導體層以及該第一半導體層的該第二區域，以形成複數個鰭片。該第一區域包含複數個缺陷以及該惰性氣體種類的原子。
10:半導體層
12:頂部表面
14:介電層
16:區域
18:區域
20:區段
22:區段
24:阱
26:阱
28:注入遮罩
30:注入遮罩
32:介電層
34:多晶區
36:硬遮罩
38:半導體層
40:鰭片
42:鰭片
44:側壁
46:側壁
48:上區段
50:下區段
52:上區段
54:下區段
56:介電層
60:閘極結構
62:閘極結構
64:多晶區
66:區域
包含於並構成本說明書的一部分的附圖示例說明本發明的各種實施例，並與上面所作的有關本發明的概括說明以及下面所作的有關所述實施例的詳細說明一起用以解釋本發明的所述實施例。在所述附圖中，類似的元件符號表示不同視圖中的類似特徵。
圖1-7是依據本發明的實施例處於製程方法的連續製造階段的結構的剖視圖。
圖8及圖9是依據本發明的替代實施例的結構的剖視圖。
請參照圖1並依據本發明的實施例，提供半導體層10，其由單晶半導體材料(例如單晶矽)組成。例如，半導體層10可為由單晶半導體材料組成的塊體晶圓。在一個替代實施例中，半導體層10可為絕緣體上矽(SOI)晶圓的裝置層。在半導體層10的頂部表面12上可形成介電層14。介電層14可由藉由化學氣相沉積沉積或藉由熱氧化生長的介電材料(例如二氧化矽)組成。
含有改性(modified)半導體材料的層或區域16、18藉由離子注入形成於半導體層10中，並共同具有延伸於半導體層10內的給定深度範圍的深度剖面。區域16可位於半導體層10的頂部表面12下方的給定深度的深度剖面內，且區域18可位於區域16與半導體層10的頂部表面12之間的深度剖面內。半導體層10可為未損傷，且在超出區域16的深度剖面的深度為單晶。在一個實施例中，可執行單次注入來提供區域16、18。
區域16包含藉由該注入的離子引入的惰性氣體種類的濃度，並且還包含由該注入引起的對半導體層10的該單晶半導體材料的損傷。在區域16中的該注入惰性氣體種類的分佈可具有發生於該離子的投射範圍(projected range)附近的峰值濃度，且在區域16中的損傷分佈也可在該投射範圍附近呈現峰值。在區域18內的深度剖面包括注入損傷的分佈以及該惰性氣體種類的濃度，該濃度顯著小於區域16中的該惰性氣體種類的濃度以及/或者該濃度可忽略不計。對區域18中的該半導體材料的損傷是由該惰性氣體種類的該注入引起。
為形成區域16、18而執行的該離子注入引入高能離子(如單向箭頭示意所示)，離子軌跡穿過介電層14並進入半導體層10中。該高能離子 在它們進入半導體層10中時通過與半導體層10中的該半導體材料的原子及電子的散射事件而損失能量。核碰撞中的能量損失(在能量損失以後的低動能下占主導地位)使半導體層10的目標原子偏離它們的原始晶格位置，從而損傷半導體層10的晶格結構並在兩個區域16、18中生成點缺陷。在該動能藉由該能量損失被完全消散以後，該離子停止於半導體層10中，並主要停止於半導體層10的區域16中。
可自合適的源氣體生成該離子，並利用離子注入工具以一個或多個注入條件將其注入半導體層10中。該注入的該條件(例如，離子種類、劑量、動能)可經選擇以調節區域16、18的特性(例如，深度剖面、損傷量、惰性氣體含量)。在區域16、18中的半導體層10的晶格結構相對其初始單晶狀態可被該注入離子損傷。在一個實施例中，可自氬或另一種類型的貴原子氣體或惰性氣體生成該注入離子。該離子劑量經選擇成小於閾值劑量，超過該閾值劑量，藉由後續退火重結晶位於區域16、18中的該損傷半導體材料是不可能的。在一個實施例中，該離子劑量可小於或等於1.3x1015cm-2。在一個實施例中，該離子劑量可大於1x1014cm-2。在一個實施例中，該離子劑量可在從1x1013cm-2延伸至1x1015cm-2的範圍內。在一個實施例中，可採用不同動能及劑量的多次注入來形成區域16、18。
在一個實施例中，在形成區域16、18的該注入期間，可掩蔽半導體層10的一個區域(未顯示)。此區域可用以形成例如邏輯裝置的CMOS場效電晶體。
請參照圖2，其中類似的元件符號表示圖1中類似的特徵，且在該製程方法的下一製造階段，藉由例如離子注入可摻雜半導體層10的區段20 中的區域18，以形成阱(well)24。為此，可剝離介電層14，並可在半導體層10的區段22上方藉由微影形成注入遮罩28。注入遮罩28可包括例如有機光阻層，其藉由以下步驟鋪設：旋塗製程、預烘烤、暴露於經由光遮罩投射的光、曝光後烘烤，以及用化學顯影劑顯影。
在形成注入遮罩28以後，用提供n型電性導電性的n型摻雜物(例如，磷及/或砷)藉由離子注入在半導體層10的區段20內的區域18中可形成阱24。離子注入引入高能離子(如單向箭頭示意所示)，離子軌跡停止於半導體層10的區段20中的區域18的該半導體材料內。可自合適的源氣體生成該離子，並利用離子注入工具以一個或多個注入條件將其注入半導體層10的區段20內的區域18中。該注入條件(例如，離子種類、劑量、動能)可經選擇以調節阱24的特性(例如，深度剖面、損傷量)。尤其，該注入可在半導體層10的區段20內的區域18中引入額外損傷，其附加於在該注入之前的損傷。在一個實施例中，可採用不同動能及劑量的多次注入來形成阱24。例如，可採用跨越區域18的厚度具有不同動能及劑量的三次注入系列來形成阱24。
注入遮罩28的厚度經選擇以使該離子停止於注入遮罩28中，而不是進入半導體層10的區段22中的下方半導體層10中。在注入之後，可藉由例如注入之後接著進行灰化來移除注入遮罩28。
請參照圖3，其中類似的元件符號表示圖2中類似的特徵，且在該製程方法的下一製造階段，藉由例如離子注入可摻雜半導體層10的區段22內的區域18，以形成具有與阱24的導電類型的極性類型相反的導電類型的阱26。為此，可在半導體層10的區段20上方藉由微影形成注入遮罩30。注入遮罩30可包括例如有機光阻層，其藉由下列步驟鋪設：旋塗製程、預烘烤、暴 露於經由光遮罩投射的光、曝光後烘烤，以及用化學顯影劑顯影。
在形成注入遮罩30以後，用提供p型電性導電性的p型摻雜物(例如，硼)藉由離子注入在半導體層10的區段22內的區域18中可形成阱26。離子注入引入高能離子(如單向箭頭示意所示)，離子軌跡停止於半導體層10的區段20中的區域18的該半導體材料內。可自合適的源氣體生成該離子，並利用離子注入工具以一個或多個注入條件將其注入半導體層10的區段22中的區域18中。該注入條件(例如，離子種類、劑量、動能)可經選擇以調節阱26的特性(例如，深度剖面、損傷量)。尤其，該注入可在半導體層10的區段22中的區域18中引入額外損傷，其附加於在該注入之前的損傷。在一個實施例中，可採用不同動能及劑量的多次注入來形成阱26。例如，可採用跨越區域18的厚度具有不同動能及劑量的三次注入系列來形成阱26。
注入遮罩30的厚度經選擇以使注入的該離子停止於注入遮罩30中，而不是進入半導體層10的區段20中的下方半導體層10中。在注入之後，可藉由例如注入之後接著進行灰化來移除注入遮罩30。
請參照圖4，其中類似的元件符號表示圖3中類似的特徵，且在該製程方法的下一製造階段，介電層32形成於半導體層10的頂部表面12上並設置於阱24、26上方。介電層32可由藉由化學氣相沉積沉積或藉由熱氧化生長的介電材料(例如二氧化矽)組成。在一個替代實施例中，可在介電層14覆蓋半導體層10的區段20、22的情況下形成阱24、26，且在形成阱24、26之後可保留介電層14。
使半導體層10(尤其半導體層10的區域16、18)經歷熱處理(也就是，退火製程)。在一個實施例中，可執行尖峰退火作為用以熱處理區 域16、18的該熱處理。在一個實施例中，該尖峰退火可為快速熱退火(rapid thermal anneal；RTA)，該快速熱退火藉由使用例如一排閃光燈執行，以將半導體層10加熱至在860℃至1125℃的範圍內的峰值溫度並在該峰值溫度具有34毫秒至60秒的停留時間，且在一個特定實施例中，該峰值溫度可為1000℃，停留時間為5秒。
該熱處理將區域16的該注入及損傷的半導體材料重結晶為包含多晶半導體材料(例如，多晶矽)的多晶區34。除了該多晶半導體材料的晶粒以外，多晶區34還包含作為殘餘損傷的缺陷。該缺陷可包含經注入以形成區域16的該貴氣體或惰性氣體種類的原子(例如，氬)。設置於區域16下方的半導體層10的該單晶半導體材料提供結晶模板，以用於重結晶。可將多晶區34設置於區域16的該半導體材料中的峰值離子劑量及/或峰值損傷的先前位置處或附近。
該熱處理還將半導體層10的區域18中的阱24、26的該損傷半導體材料重結晶為單晶半導體材料(例如，單晶矽)。阱24、26的該單晶半導體材料位於多晶區34與半導體層10的頂部表面12之間。介電層32的存在可影響重結晶期間該單晶半導體材料自區域18中的阱24、26的該損傷半導體材料的形成。該熱處理還可穩定及/或活化被引入區域18中以形成阱24、26的該摻雜物。區域18缺乏多晶區34中所包含的惰性氣體原子及缺陷，且與多晶區34的多晶狀態相比，可具有處於單晶狀態的晶體結構。
請參照圖5，其中類似的元件符號表示圖4中類似的特徵，且在該製程方法的下一製造階段，剝離介電層32，並可清洗半導體層10的頂部表面12，以為後續磊晶生長製程做準備。在半導體層10的頂部表面12上形成半 導體層38。利用半導體層10作為晶體結構模板藉由磊晶生長製程可生長半導體層38。半導體層38可由單晶半導體材料組成，例如單晶矽。半導體層38的厚度經選擇成足夠用於鰭片的後續形成，且半導體層38可為未摻雜。
請參照圖6，其中類似的元件符號表示圖5中類似的特徵，且在該製程方法的下一製造階段，自半導體層38及區域18中的阱24形成鰭片40，並自半導體層38及區域18中的阱26形成鰭片42。可利用多重圖案化技術，例如自對準雙重圖案化(self-aligned double patterning；SADP)或自對準四重圖案化(self-aligned quadruple patterning；SAQP)，自該半導體材料圖案化鰭片40、42。在一個實施例中，鰭片40、42被同時圖案化，且各鰭片40、42可被圖案化期間所採用的硬遮罩36的部分覆蓋。多晶區34在所有鰭片40、42下方作為連續層橫向延伸。
各鰭片40具有側表面或側壁44以及被硬遮罩36的所述區段的其中之一覆蓋的頂部表面，且各鰭片42具有側表面或側壁46以及被硬遮罩36的所述區段的其中之一覆蓋的頂部表面。在一個實施例中，阱24、26被完全圖案化，且鰭片40的側壁44及鰭片42的側壁46可延伸至多晶區34。各鰭片40包括由半導體層38的該半導體材料組成的上區段48以及由阱24的該摻雜半導體材料組成的下區段50。各鰭片42包括由半導體層38的該半導體材料組成的上區段52以及由阱26的該摻雜半導體材料組成的下區段54。因此，鰭片40的下區段50及鰭片42的下區段54以具有相反極性的不同導電類型為特徵。鰭片40、42的相應下區段50、54可提供穿通停止(punch-through stopper；PTS)層或結構，用以抑制裝置操作期間的亞通道漏電流。
請參照圖7，其中類似的元件符號表示圖6中類似的特徵，且在 該製程方法的下一製造階段，設置介電層56，以圍繞並埋藏鰭片40、42的相應下部。鰭片40的相應上區段48及鰭片42的上區段52可設置於介電層56的頂部表面上方。在一個實施例中，介電層56的該頂部表面可與鰭片40的上區段與下區段48、50之間的界面共面，並且還與鰭片42的上區段與下區段52、54之間的界面共面。介電層56可由藉由化學氣相沉積沉積的介電材料(例如二氧化矽)組成。在沉積以後，可藉由化學機械拋光拋光並藉由蝕刻製程凹入介電層56，以顯露鰭片40的上區段48及鰭片42的上區段52。在凹入介電層56以後，可移除位於鰭片40的頂部表面上方及鰭片42的頂部表面上方的硬遮罩36的所述部分。
形成場效電晶體的閘極結構60，其橫向延伸越過鰭片40，以及形成不同場效電晶體的閘極結構62，其橫向延伸越過鰭片42。閘極結構60、62與鰭片40、42具有疊置關係，尤其，與鰭片40、42的上區段48、52中的相應通道區具有疊置關係。閘極結構60、62可包括藉由沉積層堆疊並藉由微影及蝕刻圖案化該層堆疊而形成的閘極電極及閘極介電質。該閘極電極可由導體組成，例如摻雜多晶矽或功函數金屬，且該閘極介電質可由電性絕緣體組成，例如二氧化矽或氧化鉿。
多晶區34可藉由充當在該主動裝置(例如，該鰭型場效電晶體)與位於多晶區34下方的半導體層10的該塊體基板部分之間的隔離層來提升射頻操作模式中的裝置性能。利用鰭片40、42形成的該鰭型場效電晶體可被用於例如開關或低噪聲放大器(low-noise amplifier)中，該電晶體具有得益於由多晶區34提供的電性隔離的性能。此外，在該鰭型場效電晶體下方的多晶區34有效增加基板電阻，並因此減少至半導體層10的該塊體基板部分的亞 通道洩漏。
請參照圖8，其中類似的元件符號表示圖7中類似的特徵，且依據替代實施例，可在深度上重新設置阱24、26，並可修改鰭片40、42的該圖案化，以使阱24的完好區段設置於鰭片40的下區段50與多晶區34之間，且使阱26的完好區段設置於鰭片42的下區段54與多晶區34之間。
請參照圖9，其中類似的元件符號表示圖7中類似的特徵，且依據本發明的替代實施例，藉由在位於區域16下方的位置的半導體層10中的離子注入可形成與區域16類似的額外區域。可將此包含損傷及惰性氣體原子的附加區域轉換為與多晶區34類似的額外多晶區64，以使多個多晶區34、64出現於所有鰭片40、42下方的各分立層中。多晶區64可由多晶半導體材料(例如，多晶矽)組成，除了該多晶半導體材料的晶粒以外，它還包含作為殘餘損傷的缺陷，以及與該缺陷相關的惰性氣體原子。在多晶區34與多晶區64之間可設置單晶半導體材料的區域66，其類似於在所述熱處理之後的區域18中的單晶半導體材料。
一般來說，在半導體層10中可形成多個多晶層或區，且相鄰的多晶層或區可由單晶半導體材料的中間層或區隔開。多晶區的數量可由注入的數量及/或該注入的能量及離子劑量控制，其至少部分確定在退火期間該注入損傷半導體材料重結晶為多晶半導體材料的能力。例如，可使用多次獨立的注入來形成該多個多晶區。又例如，依據能量及離子劑量，單次注入也可導致形成多個多晶層。重結晶可從位於各損傷區下方的半導體層10的部分向上以及從位於各損傷區上方的半導體層10的部分向下同時進行。
如上所述的方法用於積體電路晶片的製造中。製造者可以原始 晶圓形式(例如作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，該晶片設於單晶片封裝件中(例如塑料承載件，其具有附著至母板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，接著將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水平”被定義為與半導體基板的傳統平面平行的平面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的方向。
本文中引用的由近似語言例如“大約”、“大致”及“基本上”所修飾的術語不限於所指定的精確值。該近似語言可對應於用以測量該值的儀器的精度，且除非另外依賴於該儀器的精度，否則可表示所述值的+/- 10%。
與另一個特徵“連接”或“耦接”的特徵可與該另一個特徵直接連接或耦接，或者可存在一個或多個中間特徵。如果不存在中間特徵，則特徵可與另一個特徵“直接連接”或“直接耦接”。如存在至少一個中間特徵，則特徵可與另一個特徵“非直接連接”或“非直接耦接”。在另一個特徵“上”或與其“接觸”的特徵可直接在該另一個特徵上或與其直接接觸，或者可存在一個或多個中間特徵。如果不存在中間特徵，則特徵可直接在另一個特徵“上”或與其“直接接觸”。如存在至少一個中間特徵，則特徵可“不直 接”在另一個特徵“上”或與其“不直接接觸”。
對本發明的各種實施例所作的說明是出於示例目的，而非意圖詳盡無遺或限於所揭示的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭示的實施例。
10:半導體層
34:多晶區
40:鰭片
42:鰭片
44:側壁
46:側壁
48:上區段
50:下區段
52:上區段
54:下區段
56:介電層
60:閘極結構
62:閘極結構

Claims (18)

  1. 一種半導體結構，包括：半導體層，包含第一多晶層及第二多晶層，該第一多晶層及該第二多晶層含有多晶半導體材料；以及包含複數個第一鰭片的第一鰭型場效電晶體，該複數個第一鰭片位於該第一多晶層上方，各該複數個第一鰭片由單結晶半導體材料組成，其中，該第一多晶層係位於該第二多晶層及該複數個第一鰭片之間。
  2. 如請求項1所述的半導體結構，其中，該複數個第一鰭片具有完全延伸至該第一多晶層的相應側壁。
  3. 如請求項1所述的半導體結構，進一步包括：阱，位於該第一多晶層與該複數個第一鰭片之間。
  4. 如請求項3所述的半導體結構，其中，各該複數個第一鰭片具有直接位於該阱上方的區段，且各該複數個第一鰭片的該區段與該阱分別含有摻雜物。
  5. 如請求項1所述的半導體結構，其中，各該複數個第一鰭片具有第一區段以及位於該第一區段與該第一多晶層之間的第二區段，且各該複數個第一鰭片的該第二區段含有具有第一導電類型的第一摻雜物。
  6. 如請求項5所述的半導體結構，其中，各該複數個第一鰭片的該第一區段未經摻雜。
  7. 如請求項5所述的半導體結構，進一步包括：包含複數個第二鰭片的第二鰭型場效電晶體，該複數個第二鰭片位於該第一多晶層上方， 其中，各該複數個第二鰭片具有第一區段以及位於該第一區段與該第一多晶層之間的第二區段，且各該複數個第二鰭片的該第二區段含有具有與該第一導電類型相反的極性的第二導電類型的第二摻雜物。
  8. 如請求項7所述的半導體結構，進一步包括：第一阱，位於該第一多晶層與該複數個第一鰭片之間的該半導體層中，該第一阱含有該第一摻雜物；以及第二阱，位於該第一多晶層與該複數個第二鰭片之間的該半導體層中，該第二阱含有該第二摻雜物。
  9. 如請求項8所述的半導體結構，其中，該半導體層在該第一阱及該第二阱內含有單晶半導體材料。
  10. 如請求項1所述的半導體結構，其中，該半導體層包含在該第一多晶層與該第二多晶層之間的單晶半導體材料。
  11. 如請求項1所述的半導體結構，其中，該第一鰭型場效電晶體進一步包含閘極結構，該閘極結構與該複數個第一鰭片具有疊置關係。
  12. 一種製造半導體結構的方法，包括：以惰性氣體種類的離子在深度範圍注入第一半導體層，以改性在第一區域以及在該第一區域與該第一半導體層的頂部表面之間的第二區域中的該第一半導體層的半導體材料的晶體結構；用退火製程退火該第一半導體層，以將該第一半導體層的該第一區域內的該半導體材料轉換為多晶層，並將該第一半導體層的該第二區域內的該半導體材料轉換為單晶狀態；在退火該第一半導體層以後，在該第一半導體層的該第二區域上方磊晶生長第二半導體層；以及 圖案化該第二半導體層以及該第一半導體層的該第二區域，以形成複數個第一鰭片，其中，該第一區域含有複數個缺陷以及該惰性氣體種類的原子。
  13. 如請求項12所述的方法，其中，該複數個第一鰭片具有完全延伸至該多晶層的側壁。
  14. 如請求項12所述的方法，進一步包括：在用該退火製程退火該第一半導體層之前，以摻雜物離子注入該第一半導體層的該第二區域。
  15. 如請求項14所述的方法，其中，在該第一半導體層的該第二區域中形成包含該摻雜物的阱，且在形成該複數個第一鰭片以後，該阱的部分位於該複數個第一鰭片與該多晶層之間。
  16. 如請求項12所述的方法，其中，各該複數個第一鰭片具有第一區段以及位於該第一區段與該多晶層之間的第二區段，且各該複數個第一鰭片的該第二區段含有具有第一導電類型的第一摻雜物。
  17. 如請求項16所述的方法，其中，圖案化該第二半導體層以及該第一半導體層的該第二區域，以在該多晶層上方形成複數個第二鰭片，各該複數個第二鰭片具有第一區段以及位於該第一區段與該多晶層之間的第二區段，且各該複數個第二鰭片的該第二區段含有具有與該第一導電類型相反的極性的第二導電類型的第二摻雜物。
  18. 如請求項17所述的方法，其中，在該第一半導體層中形成含有該第一摻雜物的第一阱以及含有該第二摻雜物的第二阱，該第一半導體層在該第一阱及該第二阱內處於該單晶狀態，在形成該複數個第一鰭片以後，該第一阱的部分位於該複數個第一鰭片與該多晶層之間，以及在形成該複數個第二鰭片以後，該第二阱的部分位於該複數個第二鰭片與該多晶層之間。
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