CN109411352A - 纳米片场效应晶体管中的内间隙壁形成 - Google Patents

纳米片场效应晶体管中的内间隙壁形成 Download PDF

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CN109411352A
CN109411352A CN201810946683.8A CN201810946683A CN109411352A CN 109411352 A CN109411352 A CN 109411352A CN 201810946683 A CN201810946683 A CN 201810946683A CN 109411352 A CN109411352 A CN 109411352A
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section
channel layer
nanometer sheet
sheet channel
layer
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CN109411352B (zh
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朱利安·弗罗吉尔
谢瑞龙
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GlobalFoundries US Inc
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GlobalFoundries Inc
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Abstract

本发明涉及纳米片场效应晶体管中的内间隙壁形成，揭示纳米片场效应晶体管的结构以及用于形成纳米片场效应晶体管的结构的方法。形成本体特征，该本体特征包括垂直设于第一与第二纳米片沟道层之间的牺牲层。在该本体特征的侧壁处横向凹入该牺牲层，以暴露该第一及第二纳米片沟道层的相应部分。在该本体特征的该侧壁处通过氧化该牺牲层的部分而形成牺牲间隙壁。在该第一及第二纳米片沟道层的该暴露部分上外延生长由半导体材料构成的区段，以收窄垂直隔开该第一与第二纳米片沟道层的间隔。移除该牺牲间隙壁，以在由该半导体材料构成的该区段与该牺牲层之间形成腔体。在该腔体中共形沉积介电间隙壁。

Description

纳米片场效应晶体管中的内间隙壁形成
技术领域
本发明涉及半导体装置制造及集成电路，尤其涉及纳米片场效应晶体管的结构以及形成纳米片场效应晶体管的方法。
背景技术
场效应晶体管的装置结构通常包括本体区、定义于该本体区中的源极及漏极、以及经配置成切换在该本体区中所形成的沟道中的载流子流的栅极电极。当向该栅极电极施加大于指定阈值电压的控制电压时，在该源极与漏极之间的该沟道中的反型或耗尽层中会发生载流子流，从而产生装置输出电流。平面场效应晶体管的本体区及沟道位于支持栅极电极的衬底的顶部表面下方。
鳍式场效应晶体管(fin-type field-effect transistor；FinFET)是非平面装置结构，与平面场效应晶体管相比，鳍式场效应晶体管可被更密集地封装于集成电路中。FinFET可包括由半导体材料的实心单体组成的鳍片、形成于该本体的区段中的重掺杂源/漏区、以及包覆位于该源/漏区之间的鳍片本体中的沟道的栅极电极。与平面晶体管相比，在该栅极结构与鳍片本体之间的该设置提升对沟道的控制并降低当该FinFET处于其“关”状态时的漏电流。相应地，与平面晶体管相比，这支持使用较低的阈值电压，从而提升性能以及降低功耗。
纳米片场效应晶体管已被开发为一种先进类型的FinFET，其可额外增加封装密度。纳米片场效应晶体管的本体包括以三维阵列堆叠的多个纳米片沟道层。栅极堆叠的区段可呈环绕栅极布置而围绕各纳米片沟道层的所有侧。该纳米片沟道层初始被设置为层堆叠，其具有由相对于构成该纳米片沟道层的材料(例如，硅)可被选择性蚀刻的材料(例如，硅-锗)所组成的牺牲层。通过使用例如盐酸蒸气蚀刻并移除该牺牲层，以释放该纳米片沟道层，并提供栅区以形成该栅极堆叠。
在释放该纳米片沟道层之前，自该半导体纳米片层的侧表面外延生长源漏区。内间隙壁位于该牺牲层的侧表面与构成该源/漏区的该外延半导体材料之间。该内间隙壁(由介电材料形成)在结构上的用意是在释放该纳米片层的该蚀刻制程期间将该源/漏区与该栅区隔离。不过，传统内间隙壁可能具有相关的弯曲度并可能在邻近该纳米片层的区域中更薄。该弯曲度可能产生于锗自该牺牲层向该纳米片沟道层中的扩散以及所导致的在蚀刻腔体(后续在其中形成介电间隙壁)时蚀刻速率的局部变化。结果是传统的弯曲内间隙壁容易破裂并泄漏，从而使在纳米片释放期间所使用的蚀刻剂抵达并蚀刻该源/漏区。
发明内容
在本发明的实施例中，提供一种用于形成场效应晶体管的方法。该方法包括形成本体特征，该本体特征具有第一纳米片沟道层、第二纳米片沟道层，以及垂直设于该第一纳米片沟道层与该第二纳米片沟道层之间的牺牲层。在该本体特征的侧壁处相对该第一纳米片沟道层及该第二纳米片沟道层横向凹入该牺牲层，以暴露该第一纳米片沟道层的部分及该第二纳米片沟道层的部分。在该本体特征的该侧壁处通过氧化该牺牲层的部分形成牺牲间隙壁。分别在该第一纳米片沟道层的该暴露部分及该第二纳米片沟道层的该暴露部分上外延生长由半导体材料构成的第一区段及第二区段，以收窄垂直隔开该第一纳米片沟道层与该第二纳米片沟道层的间隔。移除该牺牲间隙壁，以在由该半导体材料构成的该第一区段及该第二区段与该牺牲层之间形成腔体。在该腔体中共形沉积介电间隙壁。
在本发明的实施例中，针对场效应晶体管提供一种结构。该结构包括：本体特征，具有第一纳米片沟道层及第二纳米片沟道层；功能栅极结构，具有栅极电极，该栅极电极具有设于该第一纳米片沟道层与该第二纳米片沟道层之间的区段；由半导体材料构成的第一区段，位于该第一纳米片沟道层的部分上；以及由该半导体材料构成的第二区段，位于该第二纳米片沟道层的部分上。介电间隙壁设于由该半导体材料构成的该第一区段及该第二区段与该栅极电极的该区段之间的腔体中。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例，并与上面所作的有关本发明的概括说明以及下面所作的有关实施例的详细说明一起用以解释本发明的实施例。
图1至9显示依据本发明的实施例处于制程方法的连续制造阶段的装置结构的剖视图。
图7A显示图7中的介电间隙壁的其中之一的放大视图。
图10至13显示依据本发明的实施例处于制程方法的连续制造阶段的装置结构的剖视图。
具体实施方式
请参照图1并依据本发明的实施例，以交替序列形成半导体层11及半导体层13，以在衬底14上定义层堆叠。衬底14由半导体材料组成，例如单晶硅。半导体层11、13可通过外延生长制程依序形成，通过反应物的选择在生长期间交替变化组分。半导体层11由半导体材料组成，而半导体层13可由经选择成相对于半导体层11的半导体材料而被选择性移除的半导体材料组成。在一个实施例中，半导体层11可由硅(Si)组成，且半导体层13可由锗浓度为百分之二十(20％)至百分之六十(60％)的硅锗(SiGe)组成，与硅相比，其以较高的速率蚀刻。本文中所使用的关于材料移除制程(例如，蚀刻)的术语“选择性”表示通过合适的蚀刻剂选择，目标材料的材料移除速率(也就是，蚀刻速率)大于暴露于该材料移除制程的至少另一种材料的移除速率。半导体层11及半导体层13的数目可不同于所示的代表性数目。
在形成半导体层11、13以后，形成介电层16，其将半导体层11、13与衬底14电性隔离。介电层16可通过在半导体层11、13下方蚀刻并用介电材料(例如二氧化硅(SiO2))或各种材料(例如氮化硅、SiBCN、碳掺杂氮化硅(SiNC)、SiN、SiCO、SiNOC等)填充形成。
在该层堆叠的最顶部半导体层13的顶部表面上形成牺牲栅极结构20。牺牲栅极结构20可由半导体材料(例如非晶硅)组成，通过CVD(化学气相沉积)沉积该半导体材料并利用硬掩膜通过反应离子蚀刻(reactive ion etching；RIE)对其图案化。牺牲栅极结构20由位于其顶部表面上的介电覆盖层22覆盖。
在邻近牺牲栅极结构20的垂直侧壁的位置处的该层堆叠的最顶部半导体层13的顶部表面上形成介电间隙壁24。介电间隙壁24具有相应的侧壁21，该侧壁可为平坦的。介电间隙壁24可由低k介电材料组成，例如硅-硼-碳-氮化物(SiBCN)或硅-氧-碳-氮化物(SiOCN)。介电间隙壁24沿垂直于牺牲栅极结构20的侧壁的横向方向具有给定厚度t0。
请参照图2，其中相同的附图标记表示图1中类似的特征且在该制程方法的下一制造阶段，通过依赖牺牲栅极结构20及相关介电间隙壁24作为蚀刻掩膜的蚀刻制程，自该层堆叠的半导体层11、13形成鳍片或本体特征26。该自对准蚀刻制程(可为反应离子蚀刻(RIE)制程)依赖一种或多种蚀刻化学以蚀刻穿过半导体层11、13并停止于介电层16上。介电层16将本体特征26与衬底14电性隔离。
本体特征26包括自半导体层11图案化的纳米片沟道层10以及自半导体层13图案化的牺牲层12。纳米片沟道层10经设置成沿垂直方向与牺牲层12交替，并沿本体特征26的侧壁25对齐。牺牲层12的其中之一邻近并直接接触介电层16。由于介电间隙壁24的减小厚度，本体特征26中的纳米片沟道层10及牺牲层12的宽度会小于形成此类本体特征的传统制程中的宽度。
请参照图3，其中相同的附图标记表示图2中类似的特征且在该制程方法的下一制造阶段，通过相对于构成纳米片沟道层10及介电层16的材料选择性蚀刻构成牺牲层12的材料的干式或湿式等向性蚀刻制程，相对于纳米片沟道层10而横向凹入牺牲层12。本体特征26的侧壁25被腔体30凹入，在该腔体处凹入牺牲层12的表面。牺牲层12的表面沿垂直方向位于介电间隙壁24下方。蚀刻牺牲层12的该制程经控制成使该横向凹入表面不延伸于牺牲栅极结构20下方。纳米片沟道层10的周边部分通过牺牲层12的该横向凹入而于本体特征26的侧壁25处暴露。牺牲层12的该横向凹入使它们于侧壁25处的相应表面相对于介电间隙壁24的侧壁21而向内，但仍垂直位于介电间隙壁24下方。纳米片沟道层10的暴露端部通过尺寸为d1的垂直间隔隔开，该尺寸等于各牺牲层12的厚度。
请参照图4，其中相同的附图标记表示图3中类似的特征且在该制程方法的下一制造阶段，通过相对于纳米片沟道层10选择性氧化各凹入牺牲层12的暴露表面，在腔体30(图3)内部形成牺牲间隙壁32。该选择性氧化制程是依照在牺牲层12与纳米片沟道层10之间所存在的组分而定。在一个实施例中，该选择性氧化制程可执行于高压及低温下，以相对于纳米片沟道层10中的硅促进牺牲层12中的硅-锗的选择性氧化。通过该选择性氧化制程消耗位于牺牲层12的侧边的半导体材料，从而收窄牺牲层12的宽度并且还可收窄腔体30。由纳米片沟道层10的侧边定义的相应表面突伸超出位于本体特征26的侧壁25处的牺牲间隙壁32。在该选择性氧化步骤之后，接着可将位于与牺牲间隙壁32的相应垂直交界处的牺牲层12的边缘与牺牲栅极结构20的侧壁垂直对齐。
各纳米片沟道层10的该相应暴露部分可经掺杂以提供表面层34，该表面层可分布于该暴露部分的外表面下方某一浅深度上。在形成n型纳米片场效应晶体管的一个实施例中，可使用来自周期表的第V族(例如，磷(P)及/或砷(As))的n型掺杂物通过例如等离子体掺杂技术掺杂表面层34，该n型掺杂物使组成的半导体材料具有n型导电性。在形成p型纳米片场效应晶体管的一个实施例中，可使用来自周期表的第III族(例如，硼(B)、铝(Al)、镓(Ga)及/或铟(In))的p型掺杂物通过例如等离子体掺杂技术掺杂表面层34，该p型掺杂物使组成的半导体材料具有p型导电性。在一个替代实施例中，表面层34及其形成可为视需要的并可自该结构及制程方法省略。
请参照图5，其中相同的附图标记表示图4中类似的特征且在该制程方法的下一制造阶段，在本体特征26的侧壁25处的纳米片沟道层10的暴露表面上形成由半导体材料构成的区段36。区段36可通过外延生长制程形成，其中，从纳米片沟道层10的暴露表面所提供的生长晶种生长该半导体材料。在一个实施例中，区段36可通过选择性外延生长(selectiveepitaxial growth；SEG)制程形成，其中，半导体材料成核以外延生长于单晶表面(例如，纳米片沟道层10)上，但不会成核以自绝缘体表面(例如，牺牲间隙壁32及介电层16)外延生长。在后一种情况下，牺牲间隙壁32覆盖牺牲层12并防止自牺牲层12产生不需要的外延生长。
构成区段36的该半导体材料可经重掺杂以依据纳米片场效应晶体管的类型而具有p型导电性或n型导电性。在形成n型纳米片场效应晶体管的一个实施例中，可使用来自周期表的第V族(例如，磷(P)及/或砷(As))的n型掺杂物通过例如等离子体掺杂技术掺杂区段36，该n型掺杂物使组成的半导体材料具有n型导电性。在形成p型纳米片场效应晶体管的一个实施例中，可使用来自周期表的第III族(例如，硼(B、铝(Al)、镓(Ga)及/或铟(In))的p型掺杂物通过例如等离子体掺杂技术掺杂区段36，该p型掺杂物使组成的半导体材料具有p型导电性。
区段36的该外延生长经控制以使各区段36不会彼此合并，且通过尺寸为d2的垂直间隔隔开。隔开区段36的该垂直间隔小于隔开纳米片沟道层10的尺寸为d1的垂直间隔。该受控制的外延生长会导致区段36具有横向突伸超出介电间隙壁24的外侧壁21的垂直平面的厚度t1，该厚度可等于介电间隙壁24的厚度t0。向各纳米片沟道层10添加区段36可补偿介电间隙壁24薄于传统介电间隙壁的方面并有效增加纳米片沟道层10的宽度，该些纳米片沟道层在它们的相应侧表面处向外延伸超过介电间隙壁24的侧壁21的平面。区段36包覆各纳米片沟道层10的被覆盖部分中的相应表面层34。
请参照图6，其中相同的附图标记表示图5中类似的特征且在该制程方法的下一制造阶段，相对于纳米片沟道层10、牺牲层12及外延半导体区段36而非等向性移除牺牲间隙壁32。在一个实施例中，利用缓冲氢氟酸(buffered hydrofluoric acid；bHF)作为蚀刻剂通过湿化学蚀刻制程可移除牺牲间隙壁32。牺牲间隙壁32的该移除(其重新暴露位于侧壁25处的牺牲层12的周边侧表面)生成T形腔体38。各腔体38具有位于相邻对区段36之间的具有较小高度的区段以及位于相邻对纳米片沟道层10之间的具有较大高度的区段。腔体38的该较大高度区段邻近牺牲层12并位于腔体38的该较小高度区段与牺牲层12之间。
请参照图7、7A，其中相同的附图标记表示图6中类似的特征且在该制程方法的下一制造阶段，邻近牺牲栅极结构20的垂直侧壁形成内间隙壁或介电间隙壁40，并在腔体38(图6)的两个区段内部同时共形形成内介电间隙壁42。介电间隙壁40、42可由低k介电材料组成，例如硅-硼-碳-氮化物(SiBCN)、硅-氧-碳氮化物(SiOCN)，或各种不同材料，例如氮化硅、SiNC、SiN、SiCO等，且可通过沉积该低k介电材料的共形层并执行湿式蚀刻制程及/或干式蚀刻制程来形成。当移除该共形介电层时，在本体特征26的侧壁25处暴露纳米片沟道层10上的外延半导体区段36的侧表面。
介电间隙壁24设于介电间隙壁40与牺牲栅极结构20之间。介电间隙壁40沿垂直于牺牲栅极结构20的侧壁的方向具有给定厚度t2，并包覆介电间隙壁24。
介电间隙壁42的形状可符合腔体38的T形并同样采用具有不同尺寸的多个区段的T形。如图7A中最佳所示，各介电间隙壁42包括邻近牺牲层12的其中之一设置的具有尺寸或高度h1的区段41，以及设于相邻对外延半导体区段36之间的具有尺寸或高度h2的区段43。区段41的高度大于区段43的高度，其中，各高度沿垂直方向测量。各区段41设于外延半导体区段36与牺牲层12之间。
在填充腔体38时，通过该共形介电层的夹止可形成介电间隙壁42。介电间隙壁42的区段41、43可由实心介电材料构成，或区段41、43的其中一者或两者可包括在夹止期间被包覆的气隙(未显示)。区段41具有矩形形状，该矩形形状反映腔体38(在其中形成该区段)的相应矩形形状。区段41包括表面41a、41b，该些表面可为平坦的并可在直角边及拐角处相交。表面41a、41b不具有在形成纳米片场效应晶体管的传统制程期间与包覆牺牲栅极结构的介电间隙壁相关的弯曲度及相关的不均匀高度及厚度。
请参照图8，其中相同的附图标记表示图7中类似的特征且在该制程方法的下一制造阶段，邻近本体特征26的侧壁25形成源/漏区44。本文中所使用的术语“源/漏区”是指可充当纳米片场效应晶体管的源极或漏极的半导体材料掺杂区。源/漏区44通过外延半导体区段36与纳米片沟道层10连接并通过介电间隙壁42而与牺牲层12物理隔离。源/漏区44通过介电层16与衬底14电性隔离。
源/漏区44通过外延生长制程形成，其中，自附着于纳米片沟道层10的外延半导体区段36所提供的生长晶种而横向生长该半导体材料。构成源/漏区44的该半导体材料可经重掺杂以依据纳米片场效应晶体管的类型具有p型导电性或n型导电性。在一个实施例中，源/漏区44可通过选择性外延生长(SEG)制程形成，其中，半导体材料成核以外延生长于单晶表面(例如，位于纳米片沟道层10上的外延半导体区段36)上，但不会成核以自绝缘体表面(例如，介电层16)外延生长。与纳米片沟道层10的侧表面的剖面面积相比，位于纳米片沟道层10上的外延半导体区段36的该暴露表面提供较大的剖面面积以供源/漏区44生长，从而可改进构成源/漏区44的该外延半导体材料的成核及生长。
请参照图9，其中相同的附图标记表示图8中类似的特征且在该制程方法的下一制造阶段，来自外延半导体区段36的掺杂物以及来自视需要的表面层34的掺杂物可通过扩散被向内驱动至介电间隙壁42下方以及纳米片沟道层10的边缘中，从而提供位于纳米片沟道层10与外延半导体区段36及源/漏区44之间的延伸区45。该掺杂物驱入可通过例如快速加热制程或激光退火提供。在活化以后，该掺杂物有效减小延伸区45的半导体材料的电阻，并与外延半导体区段36一起，延伸区45在源/漏区44与纳米片沟道层10之间提供低电阻路径。
可沉积并平坦化由介电材料(例如二氧化硅(SiO2))组成的介电层46，以移除介电覆盖层22并暴露牺牲栅极结构20。可通过相对于纳米片沟道层10具有选择性的一个或多个蚀刻制程而依序移除牺牲栅极结构20及牺牲层12。利用例如热氨及/或盐酸蒸气可蚀刻并移除牺牲栅极结构20并接着移除牺牲层12。
在围绕各纳米片沟道层10的开放空间中共形形成场效应晶体管50的功能栅极结构48，作为替代栅极制程的部分。功能栅极结构48可包括位于纳米片沟道层10的表面上的薄氧化物层、由介电材料(例如高k介电质)组成的栅极介电层、以及金属栅极电极。该栅极介电层设于该金属栅极电极与纳米片沟道层10的外表面上的该薄氧化物层之间。该金属栅极电极包括一个或多个共形阻挡金属层及/或功函数金属层，例如由碳化铝钛(TiAlC)及/或氮化钛(TiN)组成的层，以及由导体例如钨(W)组成的金属栅极填充层。本文中所使用的术语“牺牲栅极结构”是指后续将形成的功能栅极结构的占位体结构。本文中所使用的术语“功能栅极结构”是指用以控制场效应晶体管的输出电流(例如，沟道中的载流子流)的永久栅极结构。
介电间隙壁42用以自移除牺牲层12以释放纳米片沟道层10的蚀刻制程掩蔽并气密密封源/漏区44。形成介电间隙壁42的制程仅部分依赖于牺牲层12的该横向凹入所导致的凹口(也就是，腔体30)。与传统内间隙壁形成制程相比，容置介电间隙壁42的空间的部分通过形成并移除牺牲间隙壁32来提供。结果是当通过沉积填充腔体38的共形介电层来形成时，介电间隙壁42采用移除牺牲间隙壁32后的空间的几何形状(也就是，盒状或矩形状)，因此并不具有曲面。
场效应晶体管50的纳米片沟道层10以垂直堆叠设置。功能栅极结构48的区段位于先前被所移除的牺牲层12占据的空间中并呈环绕栅极布置的方式围绕纳米片沟道层10的外表面，其中，功能栅极结构48的区段包覆各纳米片沟道层10。纳米片沟道层10充当在场效应晶体管50的操作期间所形成的载流子流的沟道。介电间隙壁42设于功能栅极结构48的区段与由外延半导体材料构成的区段36之间。
接着执行中间工艺(middle-of-line；MOL)及后端工艺(back-end-of-line；BEOL)制程，其包括形成位于该装置结构上方的局部互连结构的接触及线路，以及形成通过互连线路与场效应晶体管50的功能栅极结构48及源/漏区44耦接的互连结构的介电层、过孔塞以及线路。
请参照图10，其中相同的附图标记表示图4中类似的特征且在该制程方法的下一制造阶段，介电间隙壁42可用于自半导体层11、13形成多个本体特征26的情形。牺牲层12’的其中一个或多个可具有与其它牺牲层12相比较大的厚度。牺牲层12’的增加厚度可用以形成高悬置(tall suspension)，其可用于形成特定类型的纳米片场效应晶体管。在该代表性实施例中，牺牲层12’位于该层堆叠中央。形成于纳米片沟道层10的暴露部分的表面上由外延半导体材料构成的区段36会在本体特征26之间的空间中合并在一起。相邻对的区段36通过间隙保持垂直隔开。
请参照图11，其中相同的附图标记表示图10中类似的特征且在该制程方法的下一制造阶段，用非等向性蚀刻制程(例如反应离子蚀刻(RIE))蚀刻外延半导体区段36，以形成开口或沟槽37，从而分隔由半导体材料构成的区段36并消除它们在本体特征26之间的空间中的合并状态。牺牲栅极结构20及介电间隙壁24自对准通过该蚀刻制程所形成的沟槽，以消除外延半导体区段36的合并状态。由于该蚀刻制程的该自对准，各外延半导体区段36具有沿本体特征26的侧壁25与纳米片沟道层10的其中之一的侧边缘的表面共面的表面。
请参照图12，其中相同的附图标记表示图11中类似的特征且在该制程方法的下一制造阶段，相对于纳米片沟道层10、牺牲层12及外延半导体区段36而选择性非等向性移除牺牲间隙壁32，如图6的上下文中所述，以产生腔体38。
请参照图13，其中相同的附图标记表示图12中类似的特征且在该制程方法的下一制造阶段，如结合图7至9所述继续制程，以形成包括多个本体特征26的纳米片场效应晶体管51。场效应晶体管51包括外延生长于本体特征26之间的空间中的源/漏区44，以及当移除牺牲层12、12’时如上所述增强源/漏区44的保护的介电间隙壁42。该制程方法可促进多个本体特征26的接触栅极(多晶)间距(contacted gate(poly)pitch；CPP)的微缩，同时支持在该微缩CPP的高悬置。在传统内间隙壁制程中，在微缩CPP的高悬置(如本文中的牺牲层12’所实现的那样)由于可能导致短路的栅极至栅极夹止(gate-to-gate pinch-off)而不可行。具体地说，由于外延半导体区段36有效收窄各腔体38的入口，所以介电间隙壁42可通过在与较高牺牲层12’相关的腔体38中的共形沉积期间的夹止来形成。
如上所述的方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如，作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。在后一种情况中，该芯片设于单芯片封装件中(例如，塑料承载件，其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装件中(例如，陶瓷承载件，其具有单面或双面互连或嵌埋互连)。在任何情况下，可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。
本文中引用术语例如“垂直”、“水平”、“横向”等作为示例来建立参考框架，并非限制。术语例如“水平”及“横向”是指与半导体衬底的顶部平面平行的平面中的方向，而不论其实际的三维空间取向。术语例如“垂直”及“正交”是指垂直于该“水平”及“横向”方向的方向。术语例如“上方”及“下方”表示元件或结构相对彼此及/或相对该半导体衬底的该顶部表面的定位，而不是相对标高。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接，或者可存在一个或多个中间元件。如果不存在中间元件，则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件，则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭示的实施例。

Claims (20)

1.一种形成场效应晶体管的方法，该方法包括：
形成第一本体特征，该第一本体特征包括第一纳米片沟道层、第二纳米片沟道层、以及垂直设于该第一纳米片沟道层与该第二纳米片沟道层之间的牺牲层；
在该第一本体特征的侧壁处相对于该第一纳米片沟道层及该第二纳米片沟道层而横向凹入该牺牲层，以暴露该第一纳米片沟道层的部分及该第二纳米片沟道层的部分；
在该第一本体特征的该侧壁处通过氧化该牺牲层的部分形成牺牲间隙壁；
分别在该第一纳米片沟道层的该暴露部分及该第二纳米片沟道层的该暴露部分上外延生长由半导体材料构成的第一区段及第二区段，以收窄垂直隔开该第一纳米片沟道层与该第二纳米片沟道层的间隔；
移除该牺牲间隙壁以在由该半导体材料构成的该第一区段及该第二区段与该牺牲层之间形成腔体；以及
在该腔体中共形沉积介电间隙壁。
2.如权利要求1所述的方法，其中，在横向凹入该牺牲层以后，形成该牺牲间隙壁。
3.如权利要求1所述的方法，其中，在外延生长由该半导体材料构成的该第一区段及该第二区段以后，移除该牺牲间隙壁。
4.如权利要求1所述的方法，其中，在移除该牺牲间隙壁以后，在该腔体中共形形成该介电间隙壁。
5.如权利要求1所述的方法，还包括：
利用由该半导体材料构成的该第一区段及该第二区段作为相应的生长晶种来外延生长源/漏区。
6.如权利要求5所述的方法，还包括：
在外延生长该源/漏区以后，相对于由该半导体材料构成的该第一区段及该第二区段而选择性移除该牺牲层，
其中，当移除该牺牲层时，该介电间隙壁保护该源/漏区。
7.如权利要求1所述的方法，还包括：
在外延生长由该半导体材料构成的该第一区段及该第二区段之前，等离子体掺杂该第一纳米片沟道层及该第二纳米片沟道层的该相应部分，使表面层包括掺杂物浓度。
8.如权利要求1所述的方法，其中，由该半导体材料构成的该第一区段及该第二区段分别含有掺杂物浓度，且还包括：
退火以使该掺杂物扩散至该第一纳米片沟道层及该第二纳米片沟道层的该相应暴露部分中，从而形成相应的延伸区。
9.如权利要求1所述的方法，其中，相对于该第一纳米片沟道层及该第二纳米片沟道层而选择性氧化该牺牲层的该部分。
10.如权利要求1所述的方法，其中，该牺牲间隙壁垂直设于该第一纳米片沟道层与该第二纳米片沟道层之间。
11.如权利要求1所述的方法，其中，该介电间隙壁包括在直角拐角处相交的多个平坦侧壁，且该介电间隙壁的该多个平坦侧壁的其中之一邻近该牺牲层设置。
12.如权利要求1所述的方法，其中，邻近该第一本体特征设置第二本体特征，由该半导体材料构成的该第一区段自该第一本体特征的该第一纳米片沟道层延伸至该第二本体特征的第一纳米片沟道层，由该半导体材料构成的该第二区段自该第一本体特征的该第二纳米片沟道层延伸至该第二本体特征的第二纳米片沟道层，且还包括：
蚀刻开口，该开口延伸穿过由该半导体材料构成的该第一区段及该第二区段，以分隔由该半导体材料构成的该第一区段及该第二区段。
13.如权利要求12所述的方法，还包括：
利用由该半导体材料构成的该第一区段及该第二区段作为相应的生长晶种而在该第一本体特征与该第二本体特征之间外延生长源/漏区。
14.如权利要求1所述的方法，其中，栅极结构与该第一本体特征堆叠并包括第一侧间隙壁，且还包括：
在移除该牺牲间隙壁以后，在该第一侧间隙壁上形成第二侧间隙壁。
15.如权利要求14所述的方法，其中，当在该腔体中共形形成该介电间隙壁时，形成该第二侧间隙壁。
16.一种场效应晶体管结构，包括：
本体特征，包括第一纳米片沟道层及第二纳米片沟道层；
功能栅极结构，包括栅极电极，该栅极电极具有设于该第一纳米片沟道层与该第二纳米片沟道层之间的区段；
第一区段，由半导体材料构成，位于该第一纳米片沟道层的部分上；
第二区段，由该半导体材料构成，位于该第二纳米片沟道层的部分上；以及
介电间隙壁，设置于由该半导体材料构成的该第一区段及该第二区段与该栅极电极的该区段之间的腔体中。
17.如权利要求16所述的场效应晶体管结构，其中，该介电间隙壁包括在直角拐角处相交的多个平坦侧壁，且该介电间隙壁的该多个平坦侧壁的其中之一邻近该栅极电极的该区段设置。
18.如权利要求16所述的场效应晶体管结构，其中，该介电间隙壁垂直设置于该第一纳米片沟道层与该第二纳米片沟道层之间。
19.如权利要求16所述的场效应晶体管结构，还包括：
源/漏区，与由该半导体材料构成的该第一区段及该第二区段直接接触。
20.如权利要求17所述的场效应晶体管结构，其中，该第一纳米片沟道层以第一间隔与该第二纳米片沟道层垂直隔开，且由该半导体材料构成的该第一区段以小于该第一间隔的第二间隔与由该半导体材料构成的该第二区段垂直隔开。
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