CN112750908A - 在芯轴上具有包括二维材料的沟道区的场效应晶体管 - Google Patents

在芯轴上具有包括二维材料的沟道区的场效应晶体管 Download PDF

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CN112750908A
CN112750908A CN202011060512.9A CN202011060512A CN112750908A CN 112750908 A CN112750908 A CN 112750908A CN 202011060512 A CN202011060512 A CN 202011060512A CN 112750908 A CN112750908 A CN 112750908A
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channel layer
mandrel
channel
layer
region
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CN112750908B (zh
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朱利安·弗罗吉尔
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Abstract

本发明涉及在芯轴上具有包括二维材料的沟道区的场效应晶体管，其揭示场效应晶体管的结构以及形成场效应晶体管的结构的方法。栅极电极具有包覆由介电材料组成的芯轴的第一侧表面及第二侧表面的部分。沟道层具有部分位于该芯轴的该第一侧表面与该栅极电极的该部分之间的沟道区。该沟道层由二维材料组成。

Description

在芯轴上具有包括二维材料的沟道区的场效应晶体管
技术领域
本发明涉及半导体装置制造及集成电路，尤其涉及场效应晶体管 的结构以及形成场效应晶体管的结构的方法。
背景技术
可使用互补金属氧化物半导体 (complementary-metal-oxide-semiconductor；CMOS)制程来建立p型 与n型场效应晶体管的组合，该p型与n型场效应晶体管用以构建例如逻辑单元。场效应晶体管通常包括位于半导体本体中的沟道区、源 极、漏极、以及位于该本体上方的栅极电极。当向该栅极电极施加超 过特征阈值电压的控制电压时，在该源极与漏极之间的该沟道区中发 生载流子流(carrier flow)，从而产生装置输出电流。
纳米片场效应晶体管代表一种非平面场效应晶体管，其可在集成 电路中以增加的封装密度制造。纳米片场效应晶体管包括在衬底的顶 部表面上方的图案化层堆叠中设置的多个纳米片沟道层，以及与该纳 米片沟道层的横向端部连接的源/漏区。初始将该纳米片沟道层与包含 材料(例如，硅-锗)的牺牲层一起设置于该图案化层堆叠中，该牺牲 层与该纳米片沟道层交替并可相对构成该纳米片沟道层的材料(例如， 硅)被选择性蚀刻。可通过自该纳米片沟道层的该横向端部外延生长 半导体材料来形成该源/漏区。蚀刻并移除该牺牲层，以释放该纳米片 沟道层并为形成栅极电极提供空间。该栅极电极的部分可以环绕栅极 (gate-all-around)布置围绕各纳米片沟道层的所有侧面。在向该栅极 电极施加控制电压的操作期间，在该纳米片沟道层中的水平载流子流 产生装置输出电流。
纳米片场效应晶体管可能遇到微缩困难，因为减小纳米片厚度最 终会达到量子约束显著降低性能的程度。此外，短沟道效应可能限制 继续缩小栅极长度的能力。因此，纳米片场效应晶体管的静电控制限 制可能限制微缩。
需要改进的场效应晶体管的结构以及形成场效应晶体管的结构的 方法。
发明内容
在本发明的实施例中，提供一种场效应晶体管的结构。该结构包 括由介电材料组成的芯轴(mandrel)，以及具有包覆该芯轴的第一侧表 面及第二侧表面的部分(section)的栅极电极。该结构还包括具有部分 (in part)位于该芯轴的该第一侧表面与该栅极电极的该部分之间的沟 道区的沟道层。该沟道层由二维材料组成。
在本发明的实施例中，提供一种形成场效应晶体管的方法。该方 法包括：形成包括沟道区的沟道层，形成包括第一侧表面及第二侧表 面的介电芯轴，以及形成具有包覆该介电芯轴的该第一侧表面及该第 二侧表面的部分的栅极电极。该沟道层由二维材料组成。该沟道层的 该沟道区部分位于该介电芯轴的该第一侧表面与该栅极电极的该部分 之间。
附图说明
包含于并构成本说明书的一部分的附图示例说明本发明的各种实 施例，并与上面所作的有关本发明的概括说明以及下面所作的有关所 述实施例的详细说明一起用以解释本发明的所述实施例。在所述附图 中，类似的附图标记表示不同视图中类似的特征。
图1显示依据本发明的实施例处于制程方法的初始制造阶段的装 置结构的顶视图。
图2显示大体沿图1中的线2-2所作的剖视图。
图3显示处于图1之后的制造阶段的该装置结构的顶视图。
图4显示大体沿图3中的线4-4所作的剖视图。
图4A显示大体沿图3中的线4A-4A所作的剖视图。
图4B显示大体沿图3中的线4B-4B所作的剖视图。
图5-10、5A-10A及5B-10B显示处于图4、4A、4B之后的该制 程方法的连续制造阶段的该装置结构的相应剖视图。
图11-16、11A-16A及11B-16B显示依据替代实施例处于制程方 法的连续制造阶段的该装置结构的剖视图。
具体实施方式
请参照图1、2并依据本发明的实施例，在位于衬底11上的层堆 叠15中设置一个或多个纳米片沟道层10、一个或多个牺牲层12、以 及牺牲层14。牺牲层14沿垂直方向设置于衬底11与最下方牺牲层12 之间。衬底11可由单晶半导体材料例如单晶硅组成。纳米片沟道层10、 牺牲层12、以及牺牲层14可通过外延生长制程形成于衬底11上，在 该外延生长制程期间，通过改变提供给沉积工具的反应物来交替层组 分。层堆叠15中的纳米片沟道层10及牺牲层12的数目可不同于该代 表性实施例中的数目。尤其，通过向层堆叠15添加成对的纳米片沟道 层10及牺牲层12，层堆叠15中的纳米片沟道层10及牺牲层12的数 目可大于该代表性实施例中的数目。
纳米片沟道层10由单晶半导体材料组成，且牺牲层12由组分经 选择以相对纳米片沟道层10的该单晶半导体材料被选择性移除的单晶 半导体材料组成。牺牲层14由组分经选择以相对纳米片沟道层10及 牺牲层12两者的该单晶半导体材料被选择性移除的单晶半导体材料组 成。在提到材料移除制程(例如，蚀刻)时本文中所使用的术语“选 择性”表示通过合适的蚀刻剂选择，目标材料的材料移除速率(也就 是，蚀刻速率)大于暴露于该材料移除制程的至少另一种材料的移除 速率。
在一个实施例中，构成纳米片沟道层10的半导体材料可为单晶硅， 构成牺牲层12的半导体材料可为单晶硅锗，由于其锗含量，因此以高 于硅的速率蚀刻，以及构成牺牲层14的半导体材料可为硅锗，由于其 与牺牲层12相比包含更高的锗含量，因此以高于牺牲层12的速率蚀 刻。在一个实施例中，纳米片沟道层10不含锗，牺牲层12的锗含量 可在从十五原子百分比(15at.％)至三十五原子百分比(35at.％)的 范围内变化，且牺牲层14的锗含量可在从五十原子百分比(50at.％) 至七十五原子百分比(75at.％)的范围内变化。
在层堆叠15上方沉积硬掩膜16，并接着通过光刻及蚀刻制程图案 化该硬掩膜。硬掩膜16的部分覆盖层堆叠15的部分。硬掩膜16可由 通过化学气相沉积(chemical vapordeposition；CVD)沉积的介电材料 例如氮化硅组成。
请参照图3、4、4A、4B，其中类似的附图标记表示图1、2中类 似的特征，且在下一制造阶段。利用蚀刻制程(例如非等向性蚀刻制 程，如反应离子蚀刻)图案化纳米片沟道层10、牺牲层12、以及牺牲 层14，以定义鳍片18。先前图案化硬掩膜16的该部分建立鳍片18的图案。
可通过该蚀刻制程蚀刻衬底11，尤其，可在鳍片18的相邻侧壁 19之间的衬底11中定义自对准沟槽。随后，通过在该沟槽中沉积由介 电材料例如二氧化硅组成的层并利用蚀刻制程凹入该沉积的层，在鳍 片18的相邻侧壁19之间的该沟槽中形成浅沟槽隔离区20。
形成牺牲栅极结构22，其与叠置并包覆各鳍片18的部分。本文中 所使用的术语“牺牲栅极结构”是指后续将形成的栅极结构的占位体 (placeholder)结构。牺牲栅极结构22沿鳍片18的长度具有间隔布置， 并垂直于鳍片18的纵轴排列。牺牲栅极结构22可包括涂布鳍片18的 外表面的薄氧化物层以及包含牺牲材料例如非晶硅的较厚层。利用硬 掩膜，通过反应离子蚀刻(reactive ion etching；RIE)自这些构成层藉 由光刻及蚀刻制程可图案化牺牲栅极结构22。牺牲栅极结构22分别由 硬掩膜覆盖层(hardmask cap)24覆盖。硬掩膜覆盖层24(包含介电 材料，例如氮化硅)可为用以图案化牺牲栅极结构22的该光刻及蚀刻 制程的硬掩膜的残余物。
可通过选择性蚀刻制程自各鳍片18移除牺牲层14，以在鳍片18 下方形成空隙。在提到材料移除制程(例如，蚀刻)时本文中所使用 的术语“选择性”表示通过合适的蚀刻剂选择，目标材料的材料移除 速率(也就是，蚀刻速率)大于暴露于该材料移除制程的至少另一种 材料的移除速率。接着，邻近牺牲栅极结构22的侧壁可形成侧间隙壁 26。通过沉积由介电材料例如低k介电材料(例如，SiBCN、SiOC、 或SiOCN)组成的共形层，并利用非等向性(anisotropic)蚀刻制程例 如反应离子蚀刻蚀刻所沉积的共形层，可形成侧间隙壁26。所沉积的 共形层的部分填充通过所述移除牺牲层14的该图案化部分而形成的该 空隙，以定义位于鳍片18下方的底部介电隔离层28。
通过蚀刻制程可在鳍片18中形成凹槽25，该蚀刻制程通过侧间隙 壁26及牺牲栅极结构22自对准。该蚀刻制程可停止于底部介电隔离 层28上。各鳍片18包括邻近该凹槽的侧壁19，且鳍片18的相邻侧壁 19由尺寸为S的间隙隔开。
请参照图5、5A、5B，其中，类似的附图标记表示图4、4A、4B 中类似的特征，且在下一制造阶段，利用蚀刻制程凹入牺牲层12，以 相对纳米片沟道层10的材料选择性移除牺牲层12的材料。通过沉积 介电材料(例如氮化硅)的共形层形成内间隙壁30，该共形层填充与凹入牺牲层12的相对端部相邻的凹槽，接着执行非等向性蚀刻制程， 以自该凹槽的外部移除该共形层。
请参照图6、6A、6B，其中，类似的附图标记表示图5、5A、5B 中类似的特征，且在下一制造阶段，利用蚀刻制程完全移除纳米片沟 道层10，以形成延伸于牺牲层12及侧间隙壁26的整个宽度上的空隙 32。例如，该蚀刻制程可为远程等离子体辅助干式蚀刻制程(例如，Frontier蚀刻)，其将纳米片沟道层10暴露于由三氟化氮(NF3)与氢 气(H2)的气体混合物生成的自由基(例如，不带电或中性种类)。在 传统制程中，纳米片沟道层10不是牺牲的，且将在最终装置结构中找 到。
请参照图7、7A、7B，其中，类似的附图标记表示图6、6A、6B 中类似的特征，且在下一制造阶段，共形沉积二维(2D)材料，其用 替代沟道层34部分地填充各空隙32，并形成包覆侧间隙壁26及硬掩 膜覆盖层24的层36。该二维材料还沉积于底部介电隔离层28上。替代沟道层34仅用该二维材料部分地填充各空隙32。替代沟道层34及 层36定义由该二维材料组成的连续薄膜。
形成替代沟道层34及层36的该二维材料可为薄的共形涂层，其 通过例如原子层沉积或化学气相沉积来沉积。由于该沉积发生于形成 替代牺牲栅极结构22的金属栅极结构之前的流程中，因此减少对沉积 温度的限制。在一个实施例中，该二维材料可具有载流子迁移率大于 硅的载流子迁移率的特征。在一个实施例中，该二维材料可由包括过 渡金属(例如钼(Mo)或钨(W))及硫族原子(硫(S)、硒(Se)、 或碲(Te))的过渡金属二硫族化合物(transition metal dichalcogenide) 组成。示例的过渡金属二硫族化合物包括但不限于二硫化钼(MoS2)、 二硫化铪(HfS2)、二硫化锆(ZrS2)、二硫化钨(WS2)、硫化锡(SnS)、 以及二硒化钨(WSe2)。在一个替代实施例中，该二维材料可由石墨烯 (C)组成。在一个实施例中，该二维材料(尤其被包含于各替代沟道 层34中的该二维材料)可包括以薄片设置的单个原子单层。在一个替 代实施例中，各替代沟道层34可包含该二维材料的一个单层或两个单 层。在一个替代实施例中，各替代沟道层34可包含该二维材料的两个 或更多单层。
请参照图8、8A、8B，其中，类似的附图标记表示图7、7A、7B 中类似的特征，且在下一制造阶段，形成芯轴38，其填充未被替代沟 道层34占据的各空隙32的剩余部分。芯轴38可由介电材料组成，例 如低k介电材料(例如，SiBCN、SiOC、或SiOCN)，通过原子层沉积 沉积为层并利用等向性(isotropic)蚀刻制程蚀刻，以移除位于空隙32 外部的该层的部分。该沉积的层可夹止于空隙32内，以形成芯轴38。 芯轴38在形成替代沟道层34及层36以后形成。芯轴38具有由空隙 32及替代沟道层34建立的堆叠布置。
各芯轴38包括相对彼此沿横向隔开的相对端部表面37，以及位于 相对端部表面37之间的侧表面39。侧表面39围绕各芯轴38的周边设 置。各芯轴38的侧表面39的其中之一是离衬底11最远(也就是，远 离)的上侧表面，且各芯轴38的侧表面39的其中另一个是离衬底11 最近(也就是，接近)的下侧表面。各芯轴38的上下侧表面39可被 包含于平行或基本平行的平面中。在一个实施例中，各芯轴38可具有 平行于其纵轴的矩形剖面。在各替代沟道层34中的该二维材料包覆(也 就是，围绕或在其周围充分延伸)芯轴38的其中之一的所有侧表面39， 并因此位于上下侧表面39以及所有其它侧表面39上。在一个实施例 中，在各替代沟道层34中的该二维材料与芯轴38的其中之一的侧表 面39直接接触。各芯轴38的相对端部表面37未被该二维材料覆盖。
如图8中用附图标记35标记的单向箭头示意表示，可掺杂层36 中的该二维材料，以增加其导电性。在一个实施例中，层36中的该二 维材料可在其沉积之后且形成芯轴38以后掺杂。在一个实施例中，层36中的该二维材料可通过非损伤掺杂制程(例如通过等离子体掺杂制 程)掺杂。在一个实施例中，层36中的该二维材料可用提供p型导电 性的p型掺杂物掺杂。在一个替代实施例中，层36中的该二维材料可 用提供n型导电性的n型掺杂物掺杂。替代沟道层34被掩蔽，且不通 过掺杂层36的该制程来掺杂。
请参照图9、9A、9B，其中，类似的附图标记表示图8、8A、8B 中类似的特征，且在下一制造阶段，在凹槽25中形成源极/漏极接触 (source/drain contact)40。源极/漏极接触40通过层36与替代沟道层 34的该二维材料耦接。源极/漏极接触40可由经沉积并利用回蚀刻制 程凹入的金属例如钨或氮化钛组成。层36中的该二维材料(可经掺杂) 包覆各源极/漏极接触40。此关系最大限度地增加接触面积，从而可减 小接触电阻。
各鳍片18中的替代沟道层34横向设置于不同的源极/漏极接触40 之间，并与这些不同的源极/漏极接触40耦接。芯轴38从源极/漏极接 触40的其中一个至源极/漏极接触40的其中另一个在各鳍片18上沿横 向充分延伸，且各芯轴38的相对端部表面37终止于并直接接触源极/ 漏极接触40的其中之一。各芯轴38的端部表面37不具有该二维材料， 以促进该直接接触以及各鳍片18中的不同替代沟道层34的电性隔离。
利用等向性蚀刻制程，在形成源极/漏极接触40以后可斜切层36， 以使不同的源极/漏极接触40彼此断开。源极/漏极接触40的高度可决 定层36的斜切的程度。
沉积并平坦化层间介电层41，以填充位于源极/漏极接触40上方 的空隙。层间介电层41可由通过化学气相沉积沉积的介电材料例如二 氧化硅组成，并可通过化学机械抛光平坦化。该平坦化可移除硬掩膜 覆盖层24，从而开放牺牲栅极结构22，以供后续移除。
请参照图10、10A、10B，其中，类似的附图标记表示图9、9A、 9B中类似的特征，且在下一制造阶段，利用一个或多个蚀刻制程移除 牺牲栅极结构22。随后，利用蚀刻制程移除牺牲层12，该蚀刻制程相 对替代沟道层34及内间隙壁30的材料选择性移除牺牲层12的材料。
在通过所述移除牺牲栅极结构22及牺牲层12而开放的空隙中形 成栅极结构42，以在替代栅极制程中完成场效应晶体管的形成。栅极 结构42可包括由介电材料(例如高k介电质如氧化铪)组成的栅极介 电层，以及包括一个或多个阻挡金属层及/或功函数金属层(例如碳化 铝钛或氮化钛)的栅极电极。该栅极介电层设置于该栅极电极与替代 沟道层34之间。
替代沟道层34设置于垂直堆叠中，各替代沟道层34包覆芯轴38 的其中之一的侧表面39。各栅极结构42的栅极电极的部分43位于先 前被所移除的牺牲层12占据的空隙中。各栅极电极部分43可以环绕 栅极布置包覆替代沟道层34的其中之一的沟道区70以及相关芯轴38。
各替代沟道层34还包括位于沟道区70的相对横向端部的延伸区 72。因此，沟道区70横向位于延伸区72之间。延伸区72将各替代沟 道层34的沟道区70的相对端部与源极/漏极接触40的其中之一耦接。 各替代沟道层34的沟道区70及延伸区72包覆(也就是，围绕或在其 周围充分延伸)芯轴38的其中之一的所有侧表面39。延伸区72以及 芯轴38的相应横向部分(延伸区72位于其上)延伸穿过相邻内间隙 壁30之间的间隙。内间隙壁30的其中之一沿垂直方向设置于相邻沟 道层34的延伸区72之间。
在侧间隙壁26之间的各栅极结构42上方的空隙中形成由介电材 料例如氮化硅组成的自对准接触覆盖层44。可移除层间介电层41，以 开放源极/漏极接触40上方的空间，并可在这些开放空间中形成延伸接 触源极/漏极接触40的沟槽硅化物接触(未显示)。
随后使用中间工艺(middle-of-line；MOL)及后端工艺 (back-end-of-line；BEOL)制程来形成具有与该场效应晶体管耦接的 接触的互连结构。
在替代沟道层34中引入该二维材料能够形成具有改进的有效宽度 以及改进的制程灵活性的特征的堆叠二维场效应晶体管。制程灵活性 的改进至少部分因为在形成源极/漏极接触40之前以及在形成栅极结 构42之前形成该二维材料。因此，可用更激进的热预算来沉积该二维 材料，因为金属互扩散的风险降低以及栅极结构42的损伤风险降低。 由该二维材料实现的替代沟道层34的改进静电控制可允许该栅极长度 向下微缩。
层36及源极/漏极接触40的设置提供可减小接触电阻的包覆式接 触(wrap-around-contact；WAC)。由于源极/漏极接触40不像在传统场 效应晶体管中那样包含外延半导体材料，故包括由二维材料构成的该 替代沟道层的该场效应晶体管是无结的(junction-less)。通过调节层36 中的该二维材料的掺杂以及用以形成源极/漏极接触40的金属可形成n 型或p型场效应晶体管。
请参照图11、11A、11B，其中，类似的附图标记表示图4、4A、 4B中类似的特征，且依据替代实施例，可以减小的厚度在该层堆叠中 形成纳米片沟道层10。可邻近鳍片18的侧壁形成间隙壁50。间隙壁 50可通过沉积由介电材料例如氧化钛组成的共形层并利用非等向性蚀 刻制程例如反应离子蚀刻蚀刻所沉积的共形层来形成。沉积并平坦化 层间介电层52，以填充鳍片18与牺牲栅极结构22之间的空隙。层间 介电层52可由通过化学气相沉积沉积的介电材料例如二氧化硅组成， 并可通过化学机械抛光平坦化。该平坦化可移除硬掩膜覆盖层24，以 开放牺牲栅极结构22。
请参照图12、12A、12B，其中，类似的附图标记表示图11、11A、 11B中类似的特征，且在下一制造阶段，利用一个或多个蚀刻制程移 除牺牲栅极结构22，以定义空隙54。随后，利用蚀刻制程移除牺牲层 12，该蚀刻制程相对替代沟道层34及内间隙壁30的材料选择性移除 牺牲层12的材料。
形成芯轴56，其填充由被移除的牺牲层12腾出的空隙。芯轴56 可由低k介电材料例如SiBCN、SiOC或SiOCN组成，通过原子层沉 积共形沉积为层并利用等向性蚀刻制程蚀刻，以移除位于该空隙外部 的该层的部分。该沉积的层可夹止于该空隙内，以形成芯轴56。层间 介电层52阻止在牺牲栅极结构22之间沉积该层。各芯轴56包括相对 彼此沿横向隔开的相对端部表面57，以及位于该相对端部表面之间的 侧表面59。端部表面57及侧表面59与如前所述的芯轴38的端部表面 37及侧表面39类似。
请参照图13、13A、13B，其中，类似的附图标记表示图12、12A、 12B中类似的特征，且在下一制造阶段，利用蚀刻制程，如前所述完 全移除纳米片沟道层10，以形成延伸于鳍片18及侧间隙壁26的整个 宽度上的空隙32。接着，利用等向性蚀刻制程薄化芯轴56，该蚀刻制 程还移除间隙壁50，以定义与空隙32连通的空隙51。
请参照图14、14A、14B，其中，类似的附图标记表示图13、13A、 13B中类似的特征，且在下一制造阶段，如前所述形成由二维材料组 成的替代沟道层34及层36。在该替代实施例中，芯轴56在形成替代 沟道层34及层36之前形成，且替代沟道层34形成于芯轴56及内间隙壁30的外表面上。替代沟道层34与芯轴56的侧表面59之间的关 系类似于如前所述的替代沟道层34与芯轴38的侧表面39之间的关系。 不过，替代沟道层34的延伸区72没有围绕芯轴56。相反，替代沟道 层34的延伸区72为短段，其完全填充通过移除纳米片沟道层10而形成于内间隙壁30之间的空隙32及空隙51。各芯轴56的相对端部表面 57终止于并直接接触内间隙壁30的其中之一。
请参照图15、15A、15B，其中，类似的附图标记表示图14、14A、 14B中类似的特征，且在下一制造阶段，复合塞45形成于芯轴56之 间的空隙32中并可与替代沟道层34直接接触。复合塞45可包括栅极 结构42的共形沉积栅极介电层，由例如氮化钛组成的覆盖层，以及由 例如p型多晶硅组成的中央核心。在复合塞42存在的情况下，可执行 退火，以改进该栅极介电层的物理属性及可靠性。
层36的该二维材料的部分暴露于最顶部芯轴56上方的空间中， 并利用蚀刻制程移除。所述移除层36的该二维材料的这些暴露部分定 义位于各最顶部内间隙壁30上方的凹槽57。复合塞42在形成凹槽57 期间保护替代沟道层34。
请参照图16、16A、16B，其中，类似的附图标记表示图15、15A、 15B中类似的特征，且在下一制造阶段，用介电材料填充位于最顶部 内间隙壁30上方的凹槽57，该介电材料可为构成内间隙壁30的相同 介电材料(例如，氮化硅)。随后，利用蚀刻制程移除复合塞45的该 覆盖层及中央核心，保留栅极结构42的该栅极介电层。如前所述形成 栅极结构42的栅极电极。各栅极结构42的栅极电极部分43位于芯轴 56之间的空隙中并包覆替代沟道层34的沟道区70及相关芯轴56。接 着，形成栅极结构42的栅极电极以及自对准接触覆盖层44。
移除层间介电层52，以暴露层36。然后，可掺杂层36中的该二 维材料，如前所述，以增加其导电性。接着，在凹槽25中形成通过层36与替代沟道层34的延伸区耦接的源极/漏极接触40。
上述方法用于集成电路芯片的制造。制造者可以原始晶圆形式(例 如，作为具有多个未封装芯片的单个晶圆)、作为裸芯片、或者以封装 形式分配所得的集成电路芯片。可将该芯片与其它芯片、分立电路元 件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。该 最终产品可为包括集成电路芯片的任意产品，例如具有中央处理器的 电脑产品或智能手机。
本文中引用的由近似语言例如“大约”、“大致”及“基本上”所 修饰的术语不限于所指定的精确值。该近似语言可对应于用以测量该 值的仪器的精度，且除非另外依赖于该仪器的精度，否则可表示所述 值的+/-10％。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框 架，并非限制。本文中所使用的术语“水平”被定义为与半导体衬底 的传统平面平行的平面，而不论其实际的三维空间取向。术语“垂直” 及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向” 是指在该水平平面内的方向。
与另一个特征“连接”或“耦接”的特征可与该另一个特征直接 连接或耦接，或者可存在一个或多个中间特征。如果不存在中间特征， 则特征可与另一个特征“直接连接”或“直接耦接”。如存在至少一个 中间特征，则特征可与另一个特征“非直接连接”或“非直接耦接”。 在另一个特征“上”或与其“接触”的特征可直接在该另一个特征上 或与其直接接触，或者可存在一个或多个中间特征。如果不存在中间 特征，则特征可直接在另一个特征“上”或与其“直接接触”。如存在 至少一个中间特征，则特征可“不直接”在另一个特征“上”或与其 “不直接接触”。
对本发明的各种实施例所作的说明是出于示例说明的目的，而非 意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的 普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文 中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场 已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文 中所揭示的实施例。

Claims (20)

1.一种场效应晶体管的结构，该结构包括：
第一芯轴，由介电材料组成，该第一芯轴包括第一侧表面及第二侧表面；
栅极电极，具有包覆该第一芯轴的该第一侧表面及该第二侧表面的部分；以及
第一沟道层，包括沟道区，该第一沟道层的该沟道区部分位于该第一芯轴的该第一侧表面与该栅极电极的该部分之间，
其中，该第一沟道层由二维材料组成。
2.如权利要求1所述的结构，其中，该第一沟道层的该沟道区部分位于该第一芯轴的该第二侧表面与该栅极电极的该部分之间。
3.如权利要求2所述的结构，其中，该第一芯轴的该第一侧表面与该第二侧表面被包含于基本平行的相应平面中。
4.如权利要求1所述的结构，其中，该第一侧表面与该第二侧表面被包括于该第一沟道层的多个侧表面中，且该第一沟道层的该沟道区围绕该第一芯轴的所有该侧表面延伸。
5.如权利要求1所述的结构，还包括：
第二芯轴，由该介电材料组成，该第二芯轴包括侧表面，且该第二芯轴设置于该第一芯轴上方；以及
第二沟道层，包括部分位于该第二芯轴的该侧表面与该栅极电极的该部分之间的沟道区，
其中，该第二沟道层由该二维材料组成。
6.如权利要求5所述的结构，其中，该第一沟道层包括延伸区，该第二沟道层包括延伸区，且还包括：
源极/漏极接触，通过该第一沟道层的该延伸区与该第一沟道层的该沟道区连接并通过该第二沟道层的该延伸区与该第二沟道层的该沟道区连接。
7.如权利要求6所述的结构，其中，该第一芯轴及该第二芯轴分别终止于该源极/漏极接触，与该源极/漏极接触直接接触，该第一沟道层的该延伸区围绕该第一芯轴充分延伸，且该第二沟道层的该延伸区围绕该第二芯轴充分延伸。
8.如权利要求7所述的结构，还包括：
内间隙壁，沿第一方向位于该栅极电极的该部分与该源极/漏极接触之间，
其中，该内间隙壁沿第二方向位于该第一沟道层的该延伸区与该第二沟道层的该延伸区之间。
9.如权利要求1所述的结构，其中，该第一沟道层包括第一延伸区，且还包括：
第一源极/漏极接触，通过该第一沟道层的该第一延伸区与该第一沟道层的该沟道区连接。
10.如权利要求9所述的结构，其中，该第一沟道层包括第二延伸区，该第一沟道层的该沟道区位于该第一沟道层的该第一延伸区与该第二延伸区之间，且还包括：
第二源极/漏极接触，通过该第一沟道层的该第二延伸区与该第一沟道层的该沟道区连接。
11.如权利要求10所述的结构，其中，该第一侧表面及该第二侧表面被包括于多个侧表面中，且该第一沟道层的该沟道区、该第一延伸区、以及该第二延伸区围绕该第一芯轴的所有该侧表面延伸。
12.如权利要求9所述的结构，还包括：
该二维材料的层，将该第一沟道层的该第一延伸区与该第一源极/漏极接触耦接。
13.如权利要求12所述的结构，其中，该二维材料的该层包含掺杂物，其有效增加该二维材料的导电性。
14.如权利要求9所述的结构，还包括：
第一内间隙壁及第二内间隙壁，沿第一方向位于该栅极电极的该部分与该第一源极/漏极接触之间，
其中，该第一延伸区沿第二方向位于该第一内间隙壁与该第二内间隙壁之间，且该第一芯轴终止于该第一内间隙壁及该第二内间隙壁。
15.如权利要求1所述的结构，其中，该二维材料为过渡金属二硫族化合物。
16.如权利要求1所述的结构，其中，该二维材料为二硫化钼、二硫化铪、二硫化锆、二硫化钨、硫化锡、或二硒化钨。
17.一种形成场效应晶体管的方法，该方法包括：
形成包括沟道区的沟道层；
形成介电芯轴，其包括第一侧表面及第二侧表面；以及
形成栅极电极，其具有包覆该介电芯轴的该第一侧表面及该第二侧表面的部分，
其中，该沟道层的该沟道区部分位于该介电芯轴的该第一侧表面与该栅极电极的该部分之间，且该沟道层由二维材料组成。
18.如权利要求17所述的方法，其中，在形成该介电芯轴之前，形成该沟道层。
19.如权利要求17所述的方法，其中，在形成该介电芯轴以后，形成该沟道层。
20.如权利要求17所述的方法，其中，该第一侧表面与该第二侧表面被包括于该沟道层的多个侧表面中，且该沟道层的该沟道区围绕该介电芯轴的所有该侧表面延伸。
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