WO2020248474A1 - 堆叠式环栅纳米片cmos器件结构及其制造方法 - Google Patents

堆叠式环栅纳米片cmos器件结构及其制造方法 Download PDF

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WO2020248474A1
WO2020248474A1 PCT/CN2019/114174 CN2019114174W WO2020248474A1 WO 2020248474 A1 WO2020248474 A1 WO 2020248474A1 CN 2019114174 W CN2019114174 W CN 2019114174W WO 2020248474 A1 WO2020248474 A1 WO 2020248474A1
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channel
layer
pmos
nmos
gate stack
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PCT/CN2019/114174
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English (en)
French (fr)
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殷华湘
叶甜春
张青竹
姚佳欣
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中国科学院微电子研究所
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Priority to US16/954,776 priority Critical patent/US11411091B2/en
Publication of WO2020248474A1 publication Critical patent/WO2020248474A1/zh

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Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a stacked ring-gate nano-chip CMOS device structure and a manufacturing method thereof.
  • FinFET Fin Field-Effect Transistor, fin field effect transistor
  • HKMG High-K & Metal Gate
  • FinFET process compatible GAA Gate-All-Around nano-sheet transistors will be the next-generation key structure to achieve size reduction. Its channel structure includes nano-wire (NW) and nano-sheet (Nano-Sheet). , NS) Two choices.
  • the new structure is to selectively form stacked nanowires or nanosheet structures (the source and drain are still Fin) in the back gate in the HKMG FinFET process, and then form a GAA device.
  • both NMOS and PMOS use the ⁇ 100> crystal orientation of the Si(100) crystal plane as the device channel.
  • NMOS it will bring empty space.
  • hole mobility and device performance, and for PMOS it will bring about a slight decrease in hole mobility and device performance, which leads to a mismatch between the performance of NMOS and PMOS, which brings about CMOS device and circuit design. Serious impact.
  • the stacked ring-gate nano-chip CMOS device structure and the manufacturing method thereof provided by the present invention can solve the problem of the performance mismatch between NMOS and PMOS caused by the low hole mobility of Si-channel PMOS in single-channel CMOS.
  • the present invention provides a method for manufacturing a stacked ring-gate nano-chip CMOS device, including:
  • a substrate is provided, one side of the substrate has a supporting part, and sacrificial layers and channel layers are alternately stacked on the supporting part along the extending direction of the supporting part.
  • the supporting part, the sacrificial layer and the channel layer constitute a fin structure, wherein NMOS is used For the channel layer of the first material, PMOS uses the channel layer of the second material, and the respective channel layers are the same sacrificial layer of the other side, and the hole mobility of the second material is greater than the hole mobility of the first material;
  • the dummy gate stack of NMOS/PMOS and the sacrificial layer covered by it are sequentially removed, so that part of the surface of the channel layer between the source/drain regions is exposed, and the channel layer with an exposed surface is formed Nanosheet array
  • a gate stack structure is formed around the outer circumference of each nanosheet in the nanosheet array.
  • the selective etching process is used to sequentially remove the dummy gate stack of NMOS/PMOS and the sacrificial layer covered by it, so that part of the surface of the channel layer located between the source/drain regions is exposed.
  • the channel layer on the surface constitutes the nanosheet array including:
  • etching masking layer to completely cover the PMOS and expose the NMOS.
  • an etching process that only etches the second material but not the first material is used to remove the second material in the channel region to realize the channel separation of the NMOS multilayer first material;
  • etching masking layer to completely cover the NMOS and expose the PMOS.
  • an etching process that only corrodes the first material but not the second material is used to remove the first material in the channel region to realize the channel separation of the multi-layer second material of the PMOS.
  • the etching process includes dry and wet etching processes.
  • the forming source/drain regions in the fin structure located on both sides of the dummy gate stack includes: forming source/drain regions in the fin structure located on both sides of the dummy gate stack through source-drain selective epitaxy and doping and rapid annealing. /Drain area.
  • the first material is Si
  • the hole mobility of the second material is greater than 100 cm 2 /V ⁇ s.
  • the second material includes GeSi, Ge, and Si 1-x Ge x .
  • the corrosion masking layer includes photoresist, polymer, amorphous carbon a-C, organic insulator, spin-on glass, low-dielectric constant low-k material, and silicon nitride.
  • the present invention provides a stacked ring-gate nanochip CMOS device structure, including:
  • the substrate includes an NMOS region and a PMOS region, where NMOS uses a channel layer of a first material, and PMOS uses a channel layer of a second material.
  • the hole mobility of the second material is greater than that of the first material.
  • a nanosheet array is located on the substrate and includes a plurality of nanosheets
  • a gate stack structure arranged around the nanosheets in the nanosheet array.
  • the source/drain regions are connected to the nanosheet array.
  • the first material is Si
  • the hole mobility of the second material is greater than 100 cm 2 /V ⁇ s.
  • the second material includes GeSi, Ge, and Si 1-x Ge x .
  • the first material is used as the device channel of NMOS
  • the second material is used as the device channel of PMOS, wherein the holes of the second material
  • the mobility is greater than the hole mobility of the first material, which can improve hole mobility and device performance for NMOS while providing higher hole mobility and device performance for PMOS.
  • the performance of NMOS and PMOS can Get matched, so that high-performance CMOS devices and circuits can be obtained.
  • Figures 1a and 1b are a top view and a cross-sectional view along the A-A' direction of forming an active region laminate structure on a substrate provided by an embodiment of the present invention
  • 2a, 2b, and 2c are top views of Fin structures and well region structures for forming NMOS/PMOS, cross-sectional views along the gate direction A-A', and along the NMOS channel direction B-B' and A cross-sectional view along the direction C-C' of the PMOS channel;
  • 3a, 3b, and 3c are a top view of forming an STI, a cross-sectional view along the gate direction AA', and along the NMOS channel direction B-B' and along the PMOS channel direction C-C' according to an embodiment of the present invention.
  • 4a, 4b, and 4c are a top view of a dummy gate stack and an outer wall forming a cross-fin structure provided by an embodiment of the present invention, a cross-sectional view along the gate direction A-A', and a cross-sectional view along the NMOS channel direction B-B' And a cross-sectional view along the PMOS channel direction C-C';
  • Figures 5a, 5b, and 5c are top views of the structure of performing ILD 0 layer deposition, planarization, and exposing the top of the NMOS/PMOS dummy gate stack, cross-sectional views along the gate direction A-A', and Cross-sectional views of the NMOS channel direction B-B' and the PMOS channel direction C-C';
  • 6a, 6b, and 6c are a top view of a structure obtained after selective etching of an NMOS dummy gate stack provided by an embodiment of the present invention, a cross-sectional view along the gate direction A-A', and a cross-sectional view along the NMOS channel direction B- B'and a cross-sectional view along the PMOS channel direction C-C';
  • 7a, 7b, and 7c are a top view of a structure obtained after releasing the NMOS channel, a cross-sectional view along the gate direction AA', and a cross-sectional view along the NMOS channel direction B-B' and along the PMOS channel according to an embodiment of the present invention.
  • 8a, 8b, and 8c are a top view of a structure obtained after selective etching of a PMOS dummy gate stack according to an embodiment of the present invention, a cross-sectional view along the gate direction AA', and a cross-sectional view along the NMOS channel direction B- B'and a cross-sectional view along the PMOS channel direction C-C';
  • 9a, 9b, and 9c are a top view of a structure obtained after releasing the PMOS channel according to an embodiment of the present invention, a cross-sectional view along the gate direction A-A', and a cross-sectional view along the NMOS channel direction B-B' and along the PMOS channel.
  • 10a, 10b, and 10c are top views of the structure obtained after the deposition of the HK layer/WFL layer of NMOS and the HK layer/WFL layer of PMOS provided by the embodiments of the present invention, along the gate direction A-A' A cross-sectional view and a cross-sectional view along the NMOS channel direction B-B' and along the PMOS channel direction C-C';
  • 11a, 11b, and 11c are a top view of a structure obtained after filling and planarizing the NMOS/PMOS gate and conductive materials, a cross-sectional view along the gate direction AA', and a cross-sectional view along the NMOS channel provided by an embodiment of the present invention A cross-sectional view in the direction B-B' and along the PMOS channel direction C-C';
  • 12a, 12b, and 12c are top views of the structure obtained after ILD 1 layer deposition and planarization, through hole etching, and through hole material filling and planarization according to an embodiment of the present invention, along the gate direction A-A 'And cross-sectional views along the NMOS channel direction B-B' and along the PMOS channel direction C-C'.
  • the embodiment of the present invention provides a method for manufacturing a stacked ring gate nano-chip CMOS device, the method including:
  • a Si/GeSi active area stack is formed on the substrate 01, where 02 is Si and 03 is GeSi, as shown in Figs. 1a and 1b.
  • NMOS/PMOS The Fin structure of NMOS/PMOS is formed by photolithography and etching. After etching, the Si/GeSi stack in NMOS is marked as 0201, 0301, and the Si/GeSi stack in PMOS is marked as 0202, 0302; And through ion implantation and annealing, the well region 0101 of NMOS and the well region 0102 of PMOS are respectively formed, as shown in FIG. 2a, FIG. 2b and FIG. 2c.
  • the dummy gate stack material includes a gate insulating layer and a dummy gate stack, which are usually silicon oxide and polysilicon, respectively, by photolithography and etching,
  • the dummy gate stack 0501 of NMOS and the dummy gate stack 0502 of PMOS are respectively formed, the outer wall material 06 is deposited, the Si/GeSi stack is wrapped, and the outer wall 0601 of NMOS and the outer wall of PMOS are formed through photolithography and etching.
  • the outer wall 0602 as shown in Figure 4a, Figure 4b and Figure 4c.
  • the side wall material is re-deposited and anisotropic corrosion is used to form the inner wall structure.
  • the source and drain regions are formed by source and drain selective epitaxy and doping and rapid annealing.
  • NMOS/PMOS ILD Interlayer Dielectric
  • CMP Chemical Mechanical Polishing
  • the corrosion masking layer 0801 may be photoresist, polymer, amorphous carbon (a-C), organic insulator, spin-on glass, low-k material, silicon nitride, or other insulating fillers.
  • the corrosion masking layer 0802 may be insulating fillers such as photoresist, polymer, a-C, organic insulator, spin-on glass, low-k, silicon nitride, etc.
  • the above-mentioned etching process includes dry or wet etching process.
  • the GeSi may also be other high hole mobility materials with hole mobility greater than silicon-based hole mobility under the same conditions.
  • the hole mobility of the high hole mobility material is greater than 100 cm 2 /V ⁇ s in a high field.
  • the high hole mobility material may be Ge, Si 1-x Ge x, or the like.
  • the manufacturing method of the stacked ring-gate nano-chip CMOS device uses Si as the device channel of the NMOS, which can improve the hole mobility and device performance for the NMOS, and uses SiGe as the device channel of the PMOS , Can provide higher hole mobility and device performance for PMOS, and the performance of NMOS and PMOS can be matched, so that high-performance CMOS devices and circuits can be obtained.
  • the embodiment of the present invention also provides a stacked ring-gate nanochip CMOS device structure.
  • the stacked ring-gate nanochip CMOS device structure includes:
  • the substrate includes an NMOS region and a PMOS region, where NMOS uses a channel layer of a first material, and PMOS uses a channel layer of a second material.
  • the hole mobility of the second material is greater than that of the first material.
  • a nanosheet array is located on the substrate and includes a plurality of nanosheets
  • a gate stack structure arranged around the nanosheets in the nanosheet array.
  • the source/drain regions are connected to the nanosheet array.
  • the first material is Si
  • the hole mobility of the second material is greater than 100 cm 2 /V ⁇ s.
  • the second material includes GeSi, Ge, and Si 1-x Ge x .
  • a first material is used as the device channel of NMOS
  • a second material is used as the device channel of PMOS, wherein the hole mobility of the second material is greater than that of the first material.
  • the hole mobility of a material can improve hole mobility and device performance for NMOS while providing higher hole mobility and device performance for PMOS.
  • the performance of NMOS and PMOS can be matched, thus Able to obtain high-performance CMOS devices and circuits.

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Abstract

本发明提供一种堆叠式环栅纳米片CMOS器件的制造方法，包括：提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；绕纳米片阵列中各纳米片的外周形成栅叠层结构。

Description

堆叠式环栅纳米片CMOS器件结构及其制造方法
本申请要求于2019年06月11日提交中国专利局、申请号为201910500728.3、发明创造名称为“堆叠式环栅纳米片CMOS器件结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种堆叠式环栅纳米片CMOS器件结构及其制造方法。
背景技术
集成电路特征尺寸持续微缩，传统三栅或双栅的FinFET(Fin Field-Effect Transistor，鳍式场效应晶体管)在5nm以下节点受到限制，与主流后高K金属栅(High-K&Metal Gate，HKMG)FinFET工艺兼容的GAA(Gate-All-Around，环栅)纳米片晶体管将是实现尺寸微缩的下一代关键结构，其沟道结构包括纳米线(Nano-Wire，NW)与纳米片(Nano-Sheet，NS)两种选择。
新的结构是在后栅HKMG FinFET工艺中，在后栅中选择性形成堆叠纳米线或者纳米片结构(源漏仍为Fin)，然后形成GAA器件。
目前，现有的基于GeSi/Si叠层的Stacking NS FET集成工艺中，NMOS和PMOS都采用Si(100)晶面的<100>晶向作为器件沟道，对于NMOS来说，会带来空穴迁移率和器件性能的提升，而对于PMOS来说，则会带来空穴迁移率和器件性能的轻微下降，由此导致NMOS与PMOS的性能不匹配，从而对CMOS器件和电路设计带来严重的影响。
发明内容
本发明提供的堆叠式环栅纳米片CMOS器件结构及其制造方法，能够解决单一沟道CMOS因Si沟道PMOS空穴迁移率低而导致的NMOS与PMOS性能不匹配的问题。
第一方面，本发明提供一种堆叠式环栅纳米片CMOS器件的制造方法，包括：
提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；
通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；
绕纳米片阵列中各纳米片的外周形成栅叠层结构。
可选地，所述通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列包括：
使用腐蚀掩蔽层将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀第一材料的腐蚀工艺，将NMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第二材料而不腐蚀第一材料的腐蚀工艺，将沟道区的第二材料去除，实现NMOS的多层第一材料沟道分离；
使用腐蚀掩蔽层将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀第二材料的腐蚀工艺，将PMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第一材料而不腐蚀第二材料的腐蚀工艺，将沟道区的第一材料去除，实现PMOS的多层第二材料沟道分离。
可选地，所述腐蚀工艺包括干法和湿法腐蚀工艺。
可选地，所述在位于假栅叠层两侧的鳍结构中形成源/漏区包括：通过源漏选择外延和掺杂及快速退火在位于假栅叠层两侧的鳍结构中形成源/漏区。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm 2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si 1-xGe x。
可选地，所述腐蚀掩蔽层包括光刻胶、聚合物、无定形碳a-C、有机绝缘体、旋涂玻璃、低介电常数low-k材料和氮化硅。
第二方面，本发明提供一种堆叠式环栅纳米片CMOS器件结构，包括：
衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
纳米片阵列，位于所述衬底上，包括多个纳米片；
栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
源/漏区，与所述纳米片阵列连接。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm 2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si 1-xGe x。
本发明实施例提供的堆叠式环栅纳米片CMOS器件结构及其制造方法，采用第一材料作为NMOS的器件沟道，采用第二材料作为PMOS的器件沟道，其中，第二材料的空穴迁移率大于第一材料的空穴迁移率，从而可以在为NMOS带来空穴迁移率和器件性能的提升的同时为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得高性能的CMOS器件和电路。
附图说明
图1a和图1b为本发明实施例提供的在衬底上形成有源区叠层结构的俯视图和沿A-A’方向的截面图；
图2a、图2b和图2c为本发明实施例提供的形成NMOS/PMOS的Fin结构以及阱区结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图3a、图3b和图3c为本发明实施例提供的形成STI的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图4a、图4b和图4c为本发明实施例提供的形成跨鳍结构的假栅叠层和外侧墙的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图5a、图5b和图5c为本发明实施例提供的进行ILD 0 layer淀积、平坦化并露出NMOS/PMOS假栅叠层顶部的结构俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图6a、图6b和图6c为本发明实施例提供的对NMOS假栅叠层进行选择性腐蚀后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图7a、图7b和图7c为本发明实施例提供的释放NMOS沟道后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图8a、图8b和图8c为本发明实施例提供的对PMOS假栅叠层进行选择性腐蚀后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图9a、图9b和图9c为本发明实施例提供的释放PMOS沟道后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图10a、图10b和图10c为本发明实施例提供的进行NMOS的HK层/WFL层淀积以及PMOS的HK层/WFL层淀积后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图11a、图11b和图11c为本发明实施例提供的进行NMOS/PMOS栅及导电材料的填充及平坦化后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图12a、图12b和图12c为本发明实施例提供的进行ILD 1 layer淀积与平坦化、通孔刻蚀及通孔材料填充与平坦化后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实 施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种堆叠式环栅纳米片CMOS器件的制造方法，所述方法包括：
S1、通过交替外延，在衬底01上形成Si/GeSi有源区叠层，其中，02为Si，03为GeSi，如图1a和图1b所示。
S2、通过光刻、刻蚀形成NMOS/PMOS的Fin结构，其中，刻蚀后，NMOS中Si/GeSi叠层分别记为0201、0301，PMOS中Si/GeSi叠层分别记为0202、0302；并通过离子注入与退火，分别形成NMOS的阱区0101和PMOS的阱区0102，如图2a、图2b和图2c所示。
S3、通过低温淀积绝缘介质，并回刻，形成STI(浅槽隔离)04，STI回刻平面与位于底层的外延Si沟道02地面平齐，如图3a、图3b和图3c所示。
S4、淀积假栅叠层材料05，包裹Si/GeSi叠层，该假栅叠层材料包括栅绝缘层和假栅叠层，通常分别为氧化硅和多晶硅，并通过光刻、刻蚀，分别形成NMOS的假栅叠层0501和PMOS的假栅叠层0502，淀积外侧墙材料06，包裹Si/GeSi叠层，并通过光刻、刻蚀，分别形成NMOS的外侧墙0601和PMOS的外侧墙0602，如图4a、图4b和图4c所示。
可选的，通过侧墙外沟道材料腐蚀，再沉积侧墙材料与各向异性腐蚀形成内侧墙结构。
可选的，通过源漏选择外延和掺杂及快速退火形成源漏区域。
S5、淀积包裹NMOS/PMOS的ILD(Interlayer Dielectric，层间电介质)0 layer 07，并通过CMP(化学机械抛光)露出NMOS/PMOS假栅叠层顶部，如图5a、图5b和图5c所示。
S6、对NMOS假栅叠层进行选择性腐蚀：使用腐蚀掩蔽层0801将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀Si的腐蚀工艺将NMOS的假栅叠层0501除去，以实现露出Si沟道表面，如图6a、图6b和图6c所示。
其中，所述腐蚀掩蔽层0801可以为光刻胶、聚合物、无定形碳(a-C)、 有机绝缘体、旋涂玻璃、低介电常数(low-k)材料、氮化硅等绝缘填充物。
S7、释放NMOS沟道：使用一种只腐蚀GeSi而不腐蚀Si的腐蚀工艺，将沟道区的GeSi去除，以实现NMOS的多层Si沟道0201分离，如图7a、图7b和图7c所示。
S8、对PMOS假栅叠层进行选择性腐蚀：使用腐蚀掩蔽层0802将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀GeSi的腐蚀工艺，将PMOS的假栅叠层0502除去，以实现露出GeSi沟道表面，如图8a、图8b和图8c所示。
其中，所述腐蚀掩蔽层0802可以为光刻胶、聚合物、a-C、有机绝缘体、旋涂玻璃、low-k、氮化硅等绝缘填充物。
S9、释放PMOS沟道：使用一种只腐蚀Si而不腐蚀GeSi的腐蚀工艺，将沟道区的Si去除，以实现PMOS的多层GeSi沟道0302分离，如图9a、图9b和图9c所示。
其中，上述腐蚀工艺包括干法或湿法腐蚀工艺。
S10、进行NMOS的HK层/WFL层淀积(记为0901)以及PMOS的HK层/WFL层淀积(记为0902)，如图10a、图10b和图10c所示。
S11、进行NMOS/PMOS栅及导电材料10的填充及平坦化(CMP露出07顶部)，如图11a、图11b和图11c所示。
S12、进行ILD 1 layer 1101淀积与平坦化、通孔刻蚀及通孔材料1102填充与平坦化，如图12a、图12b和图12c所示。
可选地，所述GeSi也可以为其它空穴迁移率大于同等条件下的硅基空穴迁移率的高空穴迁移率材料。
优选地，所述高空穴迁移率材料的空穴迁移率为高场下大于100cm 2/V·s。
可选地，所述高空穴迁移率材料可以为Ge、Si 1-xGe x等。
本发明实施例提供的堆叠式环栅纳米片CMOS器件的制造方法，采用Si作为NMOS的器件沟道，可以为NMOS带来空穴迁移率和器件性能的提升，采用SiGe作为PMOS的器件沟道，可以为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得 高性能的CMOS器件和电路。
本发明实施例还提供一种堆叠式环栅纳米片CMOS器件结构，如图12b和12c所示，所述堆叠式环栅纳米片CMOS器件结构包括：
衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
纳米片阵列，位于所述衬底上，包括多个纳米片；
栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
源/漏区，与所述纳米片阵列连接。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm 2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si 1-xGe x。
本发明实施例提供的堆叠式环栅纳米片CMOS器件结构，采用第一材料作为NMOS的器件沟道，采用第二材料作为PMOS的器件沟道，其中，第二材料的空穴迁移率大于第一材料的空穴迁移率，从而可以在为NMOS带来空穴迁移率和器件性能的提升的同时为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得高性能的CMOS器件和电路。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种堆叠式环栅纳米片CMOS器件的制造方法，其特征在于，包括：
    提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
    形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；
    通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；
    绕纳米片阵列中各纳米片的外周形成栅叠层结构。
  2. 根据权利要求1所述的方法，其特征在于，所述通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列包括：
    使用腐蚀掩蔽层将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀第一材料的腐蚀工艺，将NMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第二材料而不腐蚀第一材料的腐蚀工艺，将沟道区的第二材料去除，实现NMOS的多层第一材料沟道分离；
    使用腐蚀掩蔽层将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀第二材料的腐蚀工艺，将PMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第一材料而不腐蚀第二材料的腐蚀工艺，将沟道区的第一材料去除，实现PMOS的多层第二材料沟道分离。
  3. 根据权利要求2所述的方法，其特征在于，所述腐蚀工艺包括干法和湿法腐蚀工艺。
  4. 根据权利要求1所述的方法，其特征在于，所述在位于假栅叠层两侧的鳍结构中形成源/漏区包括：通过源漏选择外延和掺杂及快速退火在位于假栅叠层两侧的鳍结构中形成源/漏区。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm 2/V·s。
  6. 根据权利要求5所述的方法，其特征在于，所述第二材料包括GeSi、Ge和Si 1-xGe x。
  7. 根据权利要求2所述的方法，其特征在于，所述腐蚀掩蔽层包括光刻胶、聚合物、无定形碳a-C、有机绝缘体、旋涂玻璃、低介电常数low-k材料和氮化硅。
  8. 一种堆叠式环栅纳米片CMOS器件结构，其特征在于，包括：
    衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
    纳米片阵列，位于所述衬底上，包括多个纳米片；
    栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
    源/漏区，与所述纳米片阵列连接。
  9. 根据权利要求8所述的堆叠式环栅纳米片CMOS器件结构，其特征在于，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm 2/V·s。
  10. 根据权利要求8所述的堆叠式环栅纳米片CMOS器件结构，其特征在于，所述第二材料包括GeSi、Ge和Si 1-xGe x。
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