CN110246806A - 堆叠式环栅纳米片cmos器件结构及其制造方法 - Google Patents

堆叠式环栅纳米片cmos器件结构及其制造方法 Download PDF

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CN110246806A
CN110246806A CN201910500728.3A CN201910500728A CN110246806A CN 110246806 A CN110246806 A CN 110246806A CN 201910500728 A CN201910500728 A CN 201910500728A CN 110246806 A CN110246806 A CN 110246806A
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pmos
nmos
channel
layer
gate stack
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殷华湘
叶甜春
张青竹
姚佳欣
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201910500728.3A priority Critical patent/CN110246806A/zh
Publication of CN110246806A publication Critical patent/CN110246806A/zh
Priority to PCT/CN2019/114174 priority patent/WO2020248474A1/zh
Priority to US16/954,776 priority patent/US11411091B2/en
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Abstract

本发明提供一种堆叠式环栅纳米片CMOS器件的制造方法，包括：提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；绕纳米片阵列中各纳米片的外周形成栅叠层结构。

Description

堆叠式环栅纳米片CMOS器件结构及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种堆叠式环栅纳米片CMOS器件结构及其制造方法。
背景技术
集成电路特征尺寸持续微缩，传统三栅或双栅的FinFET(Fin Field-EffectTransistor，鳍式场效应晶体管)在5nm以下节点受到限制，与主流后高K金属栅(High-K&Metal Gate，HKMG)FinFET工艺兼容的GAA(Gate-All-Around，环栅)纳米片晶体管将是实现尺寸微缩的下一代关键结构，其沟道结构包括纳米线(Nano-Wire，NW)与纳米片(Nano-Sheet，NS)两种选择。
新的结构是在后栅HKMG FinFET工艺中，在后栅中选择性形成堆叠纳米线或者纳米片结构(源漏仍为Fin)，然后形成GAA器件。
目前，现有的基于GeSi/Si叠层的Stacking NS FET集成工艺中，NMOS和PMOS都采用Si(100)晶面的<100>晶向作为器件沟道，对于NMOS来说，会带来空穴迁移率和器件性能的提升，而对于PMOS来说，则会带来空穴迁移率和器件性能的轻微下降，由此导致NMOS与PMOS的性能不匹配，从而对CMOS器件和电路设计带来严重的影响。
发明内容
本发明提供的堆叠式环栅纳米片CMOS器件结构及其制造方法，能够解决单一沟道CMOS因Si沟道PMOS空穴迁移率低而导致的NMOS与PMOS性能不匹配的问题。
第一方面，本发明提供一种堆叠式环栅纳米片CMOS器件的制造方法，包括：
提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；
通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；
绕纳米片阵列中各纳米片的外周形成栅叠层结构。
可选地，所述通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列包括：
使用腐蚀掩蔽层将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀第一材料的腐蚀工艺，将NMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第二材料而不腐蚀第一材料的腐蚀工艺，将沟道区的第二材料去除，实现NMOS的多层第一材料沟道分离；
使用腐蚀掩蔽层将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀第二材料的腐蚀工艺，将PMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第一材料而不腐蚀第二材料的腐蚀工艺，将沟道区的第一材料去除，实现PMOS的多层第二材料沟道分离。
可选地，所述腐蚀工艺包括干法和湿法腐蚀工艺。
可选地，所述在位于假栅叠层两侧的鳍结构中形成源/漏区包括：通过源漏选择外延和掺杂及快速退火在位于假栅叠层两侧的鳍结构中形成源/漏区。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si1-xGex。
可选地，所述腐蚀掩蔽层包括光刻胶、聚合物、a-C、有机绝缘体、旋涂玻璃、low-k和氮化硅。
第二方面，本发明提供一种堆叠式环栅纳米片CMOS器件结构，包括：
衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
纳米片阵列，位于所述衬底上，包括多个纳米片；
栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
源/漏区，与所述纳米片阵列连接。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si1-xGex。
本发明实施例提供的堆叠式环栅纳米片CMOS器件结构及其制造方法，采用第一材料作为NMOS的器件沟道，采用第二材料作为PMOS的器件沟道，其中，第二材料的空穴迁移率大于第一材料的空穴迁移率，从而可以在为NMOS带来空穴迁移率和器件性能的提升的同时为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得高性能的CMOS器件和电路。
附图说明
图1a和图1b为本发明实施例提供的在衬底上形成有源区叠层结构的俯视图和沿A-A’方向的截面图；
图2a、图2b和图2c为本发明实施例提供的形成NMOS/PMOS的Fin结构以及阱区结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图3a、图3b和图3c为本发明实施例提供的形成STI的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图4a、图4b和图4c为本发明实施例提供的形成跨鳍结构的假栅叠层和外侧墙的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图5a、图5b和图5c为本发明实施例提供的进行ILD 0layer淀积、平坦化并露出NMOS/PMOS假栅叠层顶部的结构俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图6a、图6b和图6c为本发明实施例提供的对NMOS假栅叠层进行选择性腐蚀后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图7a、图7b和图7c为本发明实施例提供的释放NMOS沟道后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图8a、图8b和图8c为本发明实施例提供的对PMOS假栅叠层进行选择性腐蚀后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图9a、图9b和图9c为本发明实施例提供的释放PMOS沟道后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图10a、图10b和图10c为本发明实施例提供的进行NMOS的HK层/WFL层淀积以及PMOS的HK层/WFL层淀积后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图11a、图11b和图11c为本发明实施例提供的进行NMOS/PMOS栅及导电材料的填充及平坦化后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图；
图12a、图12b和图12c为本发明实施例提供的进行ILD 1layer淀积与平坦化、通孔刻蚀及通孔材料填充与平坦化后得到的结构的俯视图、沿栅方向A-A’的截面图以及沿NMOS沟道方向B-B’和沿PMOS沟道方向C-C’的截面图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种堆叠式环栅纳米片CMOS器件的制造方法，所述方法包括：
S1、通过交替外延，在衬底01上形成Si/GeSi有源区叠层，其中，02为Si，03为GeSi，如图1a和图1b所示。
S2、通过光刻、刻蚀形成NMOS/PMOS的Fin结构，其中，刻蚀后，NMOS中Si/GeSi叠层分别记为0201、0301，PMOS中Si/GeSi叠层分别记为0202、0302；并通过离子注入与退火，分别形成NMOS的阱区0101和PMOS的阱区0102，如图2a、图2b和图2c所示。
S3、通过低温淀积绝缘介质，并回刻，形成STI(浅槽隔离)04，STI回刻平面与位于底层的外延Si沟道02地面平齐，如图3a、图3b和图3c所示。
S4、淀积假栅叠层材料05，包裹Si/GeSi叠层，该假栅叠层材料包括栅绝缘层和假栅叠层，通常分别为氧化硅和多晶硅，并通过光刻、刻蚀，分别形成NMOS的假栅叠层0501和PMOS的假栅叠层0502，淀积外侧墙材料06，包裹Si/GeSi叠层，并通过光刻、刻蚀，分别形成NMOS的外侧墙0601和PMOS的外侧墙0602，如图4a、图4b和图4c所示。
可选的，通过侧墙外沟道材料腐蚀，再沉积侧墙材料与各向异性腐蚀形成内侧墙结构。
可选的，通过源漏选择外延和掺杂及快速退火形成源漏区域。
S5、淀积包裹NMOS/PMOS的ILD(Interlayer Dielectric，层间电介质)0layer07，并通过CMP(化学机械抛光)露出NMOS/PMOS假栅叠层顶部，如图5a、图5b和图5c所示。
S6、对NMOS假栅叠层进行选择性腐蚀：使用腐蚀掩蔽层0801将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀Si的腐蚀工艺将NMOS的假栅叠层0501除去，以实现露出Si沟道表面，如图6a、图6b和图6c所示。
其中，所述腐蚀掩蔽层0801可以为光刻胶、聚合物、a-C、有机绝缘体、旋涂玻璃、low-k、氮化硅等绝缘填充物。
S7、释放NMOS沟道：使用一种只腐蚀GeSi而不腐蚀Si的腐蚀工艺，将沟道区的GeSi去除，以实现NMOS的多层Si沟道0201分离，如图7a、图7b和图7c所示。
S8、对PMOS假栅叠层进行选择性腐蚀：使用腐蚀掩蔽层0802将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀GeSi的腐蚀工艺，将PMOS的假栅叠层0502除去，以实现露出GeSi沟道表面，如图8a、图8b和图8c所示。
其中，所述腐蚀掩蔽层0802可以为光刻胶、聚合物、a-C、有机绝缘体、旋涂玻璃、low-k、氮化硅等绝缘填充物。
S9、释放PMOS沟道：使用一种只腐蚀Si而不腐蚀GeSi的腐蚀工艺，将沟道区的Si去除，以实现PMOS的多层GeSi沟道0302分离，如图9a、图9b和图9c所示。
其中，上述腐蚀工艺包括干法或湿法腐蚀工艺。
S10、进行NMOS的HK层/WFL层淀积(记为0901)以及PMOS的HK层/WFL层淀积(记为0902)，如图10a、图10b和图10c所示。
S11、进行NMOS/PMOS栅及导电材料10的填充及平坦化(CMP露出07顶部)，如图11a、图11b和图11c所示。
S12、进行ILD 1layer 1101淀积与平坦化、通孔刻蚀及通孔材料1102填充与平坦化，如图12a、图12b和图12c所示。
可选地，所述GeSi也可以为其它空穴迁移率大于同等条件下的硅基空穴迁移率的高空穴迁移率材料。
优选地，所述高空穴迁移率材料的空穴迁移率为高场下大于100cm2/V·s。
可选地，所述高空穴迁移率材料可以为Ge、Si1-xGex等。
本发明实施例提供的堆叠式环栅纳米片CMOS器件的制造方法，采用Si作为NMOS的器件沟道，可以为NMOS带来空穴迁移率和器件性能的提升，采用SiGe作为PMOS的器件沟道，可以为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得高性能的CMOS器件和电路。
本发明实施例还提供一种堆叠式环栅纳米片CMOS器件结构，如图12b和12c所示，所述堆叠式环栅纳米片CMOS器件结构包括：
衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
纳米片阵列，位于所述衬底上，包括多个纳米片；
栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
源/漏区，与所述纳米片阵列连接。
可选地，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm2/V·s。
可选地，所述第二材料包括GeSi、Ge和Si1-xGex。
本发明实施例提供的堆叠式环栅纳米片CMOS器件结构，采用第一材料作为NMOS的器件沟道，采用第二材料作为PMOS的器件沟道，其中，第二材料的空穴迁移率大于第一材料的空穴迁移率，从而可以在为NMOS带来空穴迁移率和器件性能的提升的同时为PMOS提供较高的空穴迁移率和器件性能，NMOS与PMOS的性能能够得到匹配，从而能够获得高性能的CMOS器件和电路。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

1.一种堆叠式环栅纳米片CMOS器件的制造方法，其特征在于，包括：
提供衬底，衬底的一侧具有支撑部，沿支撑部的延伸方向在支撑部上交替层叠设置牺牲层与沟道层，支撑部、牺牲层与沟道层构成鳍结构，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，且各自的沟道层同为对方的牺牲层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
形成跨鳍结构的假栅叠层，在位于假栅叠层两侧的鳍结构中形成源/漏区；
通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列；
绕纳米片阵列中各纳米片的外周形成栅叠层结构。
2.根据权利要求1所述的方法，其特征在于，所述通过选择性腐蚀工艺，依次去除NMOS/PMOS的假栅叠层以及其所覆盖的牺牲层，以使沟道层中位于源/漏区之间的部分表面裸露，具有裸露表面的沟道层构成纳米片阵列包括：
使用腐蚀掩蔽层将PMOS完全覆盖，露出NMOS，使用一种只腐蚀假栅叠层而不腐蚀第一材料的腐蚀工艺，将NMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第二材料而不腐蚀第一材料的腐蚀工艺，将沟道区的第二材料去除，实现NMOS的多层第一材料沟道分离；
使用腐蚀掩蔽层将NMOS完全覆盖，露出PMOS，使用一种只腐蚀假栅叠层而不腐蚀第二材料的腐蚀工艺，将PMOS的假栅叠层除去，露出第一材料和第二材料沟道表面，并使用一种只腐蚀第一材料而不腐蚀第二材料的腐蚀工艺，将沟道区的第一材料去除，实现PMOS的多层第二材料沟道分离。
3.根据权利要求2所述的方法，其特征在于，所述腐蚀工艺包括干法和湿法腐蚀工艺。
4.根据权利要求1所述的方法，其特征在于，所述在位于假栅叠层两侧的鳍结构中形成源/漏区包括：通过源漏选择外延和掺杂及快速退火在位于假栅叠层两侧的鳍结构中形成源/漏区。
5.根据权利要求1至4中任一项所述的方法，其特征在于，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm2/V·s。
6.根据权利要求5所述的方法，其特征在于，所述第二材料包括GeSi、Ge和Si1-xGex。
7.根据权利要求2所述的方法，其特征在于，所述腐蚀掩蔽层包括光刻胶、聚合物、a-C、有机绝缘体、旋涂玻璃、low-k和氮化硅。
8.一种堆叠式环栅纳米片CMOS器件结构，其特征在于，包括：
衬底，所述衬底包括NMOS区域和PMOS区域，其中，NMOS使用第一材料的沟道层，PMOS使用第二材料的沟道层，第二材料的空穴迁移率大于第一材料的空穴迁移率；
纳米片阵列，位于所述衬底上，包括多个纳米片；
栅堆叠结构，环绕所述纳米片阵列中的纳米片设置；以及
源/漏区，与所述纳米片阵列连接。
9.根据权利要求8所述的堆叠式环栅纳米片CMOS器件结构，其特征在于，所述第一材料为Si，所述第二材料的空穴迁移率大于100cm2/V·s。
10.根据权利要求8所述的堆叠式环栅纳米片CMOS器件结构，其特征在于，所述第二材料包括GeSi、Ge和Si1-xGex。
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