CN110729233A - 具有气隙的半导体结构、其制造方法和气隙的密封方法 - Google Patents

具有气隙的半导体结构、其制造方法和气隙的密封方法 Download PDF

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CN110729233A
CN110729233A CN201910637638.9A CN201910637638A CN110729233A CN 110729233 A CN110729233 A CN 110729233A CN 201910637638 A CN201910637638 A CN 201910637638A CN 110729233 A CN110729233 A CN 110729233A
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layer
substrate
gate
ion implantation
air gap
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CN110729233B (zh
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孙宏彰
峰地辉
方子韦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明根据一些实施例提供了制造半导体结构的方法。该方法包括接收具有有源区域和隔离区域的衬底；在衬底上形成栅极堆叠件并且该栅极堆叠件从有源区域延伸至隔离区域；在栅极堆叠件的侧壁上形成内栅极间隔件和外栅极间隔件；在衬底上形成层间介电(ILD)层；去除隔离区域中的外栅极间隔件，从而在内栅极间隔件和ILD层之间产生气隙；并且对ILD层实施离子注入工艺，从而扩展ILD层以覆盖气隙。本发明的实施例还提供了具有气隙的半导体结构的制造方法和气隙的密封方法。

Description

具有气隙的半导体结构、其制造方法和气隙的密封方法
技术领域
本发明的实施例一般地涉及半导体技术领域，更具体地，涉及具有气隙的半导体结构、其制造方法和气隙的密封方法。
背景技术
半导体集成电路(IC)工业已经经历了快速增长。IC材料和设计中的技术进步已经产生了多代IC，其中，每一代都比上一代具有更小和更复杂的电路。然而，这些进步已经增加了处理和制造IC的复杂性，并且为了实现这些进步，需要IC处理和制造中的类似发展。在集成电路演化过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，使用制造工艺可产生的最小组件(或线))已经减小。IC可以包括形成在衬底上的电子组件，诸如晶体管、电容器等。然后在电子组件上方形成诸如通孔和导线的互连结构，以提供电子组件之间的连接并且提供至外部器件的连接。为了减小互连结构的寄生电容，可以在包括低k介电材料的介电层中形成互连结构。然而，即使使用低k介电材料，由于先进技术节点中的小尺寸，寄生电容仍然是不可容忍的。因此，需要一种电路结构及其制造方法来解决上述问题。
发明内容
根据本发明的一方面，提供了一种制造半导体结构的方法，包括：接收具有有源区域和隔离区域的衬底；在所述衬底上形成栅极堆叠件，并且所述栅极堆叠件从所述有源区域延伸至所述隔离区域；在所述栅极堆叠件的侧壁上形成内栅极间隔件和外栅极间隔件；在所述衬底上形成层间介电(ILD)层；去除所述隔离区域中的外栅极间隔件，从而在所述内栅极间隔件和所述层间介电层之间产生气隙；以及对所述层间介电层实施离子注入工艺，从而扩展所述层间介电层以覆盖所述气隙。
根据本发明的另一方面，提供了一种制造半导体结构的方法，包括：接收衬底，其中，所述衬底具有浅沟槽隔离(STI)部件和有源区域，位于所述衬底上的栅极堆叠件、位于所述栅极堆叠件的侧壁上的内栅极间隔件和外栅极间隔件，以及在所述衬底上形成层间介电(ILD)层，其中，所述栅极堆叠件从所述有源区域延伸至所述浅沟槽隔离部件上；去除所述外栅极间隔件的位于所述浅沟槽隔离部件上的部分，从而在所述内栅极间隔件和所述层间介电层之间产生气隙；以及对所述层间介电层实施离子注入工艺，从而扩展所述层间介电层以覆盖所述气隙。
根据本发明的又一方面，提供了一种半导体结构，包括：衬底，具有有源区域和隔离区域；栅极堆叠件，位于所述衬底上并且从所述有源区域延伸至所述隔离区域；栅极间隔件，位于所述栅极堆叠件的侧壁上；以及层间介电(ILD)层，位于所述衬底上并且限定所述层间介电层和所述栅极间隔件之间的气隙，其中，所述层间介电层包括顶部，所述顶部横向延伸至所述栅极间隔件并且覆盖所述气隙。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的各个方面的示出形成半导体结构或其部分的方法的实施例的流程图。
图2A是处于根据一些实施例构建的制造阶段的半导体结构的顶视图。
图2B、图2C和图2D是根据一些实施例构建的分别沿着图2A的虚线AA’、BB’和CC’的半导体结构的截面图。
图3是处于根据一些实施例构建的不同制造阶段的半导体结构的顶视图。
图4、图5、图6、图7、图8和图9是处于根据一些实施例构建的各个制造阶段的半导体结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明提供了在层间介电(ILD)层和栅极间隔件之间具有气隙的半导体结构。本发明也提供了形成和密封气隙的方法。具体地，该方法包括去除浅沟槽隔离(STI)部件上的牺牲栅极间隔件并且对ILD层实施离子注入，从而扩展ILD层的顶部以封闭气隙。
现在参照图1，其中示出了用于制造半导体结构的方法100的一个实施例的流程图，该半导体结构具有设置在栅极间隔件和ILD层之间并且由扩展的ILD层覆盖的气隙。图2A是顶视图；图2B是沿着虚线AA’的截面图；图2C是沿着虚线BB’的截面图；并且图2D是根据一些实施例的处于一个制造阶段的沿着半导体结构200的虚线CC’的截面图。图3是处于之后制造阶段的顶视图。图4至图8是沿着虚线BB’的处于各个制造阶段的半导体结构200的截面图，并且图9是在一些实施例中根据本发明的各个方面构建的沿着虚线AA’的处于制造阶段的半导体结构200的截面图。参照图1至图9共同描述方法100和IC结构200。
参照图2A、图2B、图2C和图2D，方法100开始于块102，其中，提供半导体衬底202。半导体衬底202包括硅。在一些其它实施例中，半导体衬底202包括锗、硅锗或其它适当的半导体材料。半导体衬底202可以可选地由以下材料制成：一些其它合适的元素半导体，诸如金刚石或锗；合适的化合物半导体，例如碳化硅、砷化铟或磷化铟；或合适的合金半导体，诸如碳化硅锗、磷砷化镓或磷化镓铟。
半导体衬底202也包括各个掺杂区域，诸如n阱和p阱。在一个实施例中，半导体衬底202包括外延(或epi)半导体层。在另一实施例中，半导体衬底202包括通过适当的技术形成的用于隔离的掩埋介电材料层，诸如称为注氧隔离(SIMOX)的技术。在一些实施例中，半导体衬底202可以是绝缘体上的半导体，诸如绝缘体上硅(SOI)。
仍参照图2A至图2D，方法100进入操作104，其中，在半导体衬底202上形成浅沟槽隔离(STI)部件204。在一些实施例中，通过包括以下过程来形成STI部件204：蚀刻工艺以形成沟槽；通过沉积用介电材料填充沟槽；并且抛光以去除过量的介电材料并且平坦化顶面。蚀刻工艺可以包括通过软掩模的开口(诸如通过光刻工艺形成的光刻胶层)或通过光刻工艺和蚀刻图案化的硬掩模而施加至半导体衬底202的一个或多个蚀刻步骤。
通过图案化掩模层的开口将蚀刻工艺施加至半导体衬底202，从而形成沟槽。蚀刻工艺可以包括任何合适的蚀刻技术，诸如干蚀刻、湿蚀刻和/或其它蚀刻方法(例如，反应离子蚀刻(RIE))。在一些实施例中，蚀刻工艺包括具有不同蚀刻化学物质的多个蚀刻步骤，设计为蚀刻衬底以形成具有特定沟槽轮廓的沟槽，以改进器件性能和图案密度。在一些实例中，可以使用基于氟的蚀刻剂通过干蚀刻工艺来蚀刻衬底的半导体材料。通过沉积将一种或多种介电材料填充在沟槽中。合适的填充介电材料包括半导体氧化物、半导体氮化物、半导体氮氧化物、氟化二氧化硅玻璃(FSG)、低K介电材料和/或它们的组合。在各个实施例中，使用HDP-CVD工艺、子大气压CVD(SACVD)工艺、高纵横比工艺(HARP)、可流动CVD(FCVD)和/或旋涂工艺来沉积介电材料。然后，施加化学机械抛光/平坦化(CMP)工艺以去除过量的介电材料并且平坦化半导体结构200的顶面。
在操作104之后，有源区域限定在半导体衬底202上并且由STI部件204围绕。在一些实施例中，通过操作106形成的有源区域是3维的，有源区域诸如鳍式有源区域206。
参照图2A至图2D，方法100通过形成鳍式有源区域206进入操作106。如图2D所示，鳍式有源区域206突出到STI部件204之上。在一些实施例中，操作106包括使STI部件204凹进。凹进工艺采用一个或多个蚀刻步骤(诸如干蚀刻、湿蚀刻或它们的组合)来选择性地回蚀刻STI部件204。例如，当STI部件204是氧化硅时，使用氢氟酸的湿蚀刻工艺可以用于蚀刻。鳍式有源区域206沿着第一方向(X方向)定向，并且沿着第二方向(Y方向)彼此间隔开。
可以将各种掺杂工艺施加至半导体衬底202以形成各种掺杂阱，诸如当前阶段处或操作106之前的n阱和p阱。可以分别通过离子注入在半导体衬底202中形成各种掺杂阱。
仍参照图2A至图2D，方法100进入操作108，其中，在半导体衬底202上形成栅极堆叠件208。每个栅极堆叠件208还包括栅电极210和栅极介电层212。在本实施例中，栅极堆叠件208具有细长形状并且在第二方向(Y方向)上定向。每个栅极堆叠件208均可以设置在多个鳍式有源区域206上方。具体地，栅极堆叠件208设置在鳍式有源区域206上并且延伸至STI部件204上。因此，每个栅极堆叠件208均包括位于鳍式有源区域206上的部分以及位于STI部件204上的部分。操作108也包括形成内栅极间隔件214、外栅极间隔件216、源极/漏极(S/D)部件218和层间介电(ILD)层220。操作108还包括多个操作。在本实施例中，操作108还包括操作110、112、114、116和118，其中，将在下面参照图1和图2A至图2D进一步描述这些操作。
方法100(或操作108)包括操作110，其中，形成伪栅极(未在图2A至图2D中示出，因为这些伪栅极将在操作118处由栅极堆叠件208进行替换并且位于栅极堆叠件208的位置处)。伪栅极可以包括介电材料层(诸如氧化硅)和多晶硅。伪栅极的形成包括沉积伪栅极材料(诸如形成氧化硅层和沉积多晶硅层)；并且通过光刻工艺和蚀刻来图案化伪栅极材料。硬掩模可以形成在伪栅极材料上，并且在伪栅极的形成期间用作蚀刻掩模。栅极硬掩模可以包括任何合适的材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅、其它合适的材料和/或它们的组合。在一个实施例中，栅极硬掩模包括多种膜，诸如氧化硅和氮化硅。在一些实施例中，用于形成伪栅极的图案化工艺包括通过光刻工艺在硬掩模上形成图案化的光刻胶层；使用图案化的光刻胶层作为蚀刻掩模来蚀刻硬掩模；以及使用图案化的硬掩模作为蚀刻掩模，蚀刻栅极材料以形成伪栅极。
方法100也包括操作112，其中，在伪栅极的侧壁上形成栅极间隔件，栅极间隔件包括内栅极间隔件214和外栅极间隔件216。栅极间隔件(内栅极间隔件214和外栅极间隔件216)可以包括任何合适的介电材料，诸如半导体氧化物、半导体氮化物、半导体碳化物、半导体氮氧化物、其它合适的介电材料和/或它们的组合。内栅极间隔件214包括第一介电材料，并且外栅极间隔件216包括组分与第一介电材料不同的第二介电材料，以实现蚀刻选择性。在一些实施例中，第一介电材料包括SiCN、SiOCN、SiOC以及它们的组合中的一种；并且第二介电材料包括低k介电材料，诸如氟化硅玻璃(FSG)、碳掺杂氧化硅、干凝胶、气凝胶、非晶氟化碳、聚酰亚胺、其它合适的低k介电材料或它们的组合。栅极间隔件的形成包括沉积第一和第二介电材料和各向异性蚀刻，诸如干蚀刻。
方法100进入操作114，其中，形成S/D部件218。S/D部件218可以包括轻掺杂漏极(LDD)部件和重掺杂源极和漏极(S/D)部件。例如，每个场效应晶体管均包括形成在相应的鳍式有源区域上并且由相应的栅极堆叠件208介于其之间的源极和漏极部件。沟道形成在鳍式有源区域中的位于栅极堆叠件下面的部分中并且跨越在对应的S/D部件218之间。
在一些实施例中，S/D部件218是通过选择性外延生长形成的凸起的S/D部件，以用于应变效应，从而具有增强的载流子迁移率和器件性能。伪栅极、内栅极间隔件214和外栅极间隔件216限制将要形成在源极和漏极区域内的S/D部件218。在一些实施例中，通过一个或多个外延或外延生长形成S/D部件218，由此，在鳍式有源区域206上以晶态生长Si部件、SiGe部件、SiC部件和/或其它合适的部件。可选地，施加蚀刻工艺以在外延生长之前使源极和漏极区域凹进。合适的外延生长包括CVD沉积技术(例如，汽相外延(VPE)和/或超高真空CVD(UHV-CVD)、分子束外延和/或其它合适的工艺)。外延生长可以使用与鳍式有源区域206的组分相互作用的气态和/或液体前体。
通过引入掺杂物质，可以在外延工艺期间原位掺杂S/D部件218，掺杂物质包括：p型掺杂剂，诸如硼或BF2；n型掺杂剂，诸如磷或砷；和/或其它合适的掺杂剂，包括它们的组合。如果未原位掺杂S/D部件218，则实施注入工艺(即，结注入工艺)以将对应的掺杂剂引入S/D部件218。在实施例中，n型场效应晶体管(nFET)中的S/D部件218包括掺杂有磷的SiC或Si，而p型场效应晶体管(pFET)中的那些S/D部件包括掺杂有硼的Ge或SiGe。在一些其它实施例中，S/D部件218包括多于一个的半导体材料层。例如，硅锗层外延生长在硅层上，并且硅层外延生长在硅锗层上。此后，可以实施一个或多个退火工艺以激活S/D部件218。合适的退火工艺包括快速热退火(RTA)、激光退火工艺、其它合适的退火技术或它们的组合。
方法100进入操作116，其中，在半导体衬底202上形成覆盖S/D部件218的ILD层220。未在图2A中示出S/D部件218和鳍式有源区域206，从而可以看到ILD层220下面的那些部件(诸如S/D部件218)。ILD层220围绕伪栅极、内栅极间隔件214和外栅极间隔件216，允许去除伪栅极，并且在产生的栅极腔中形成替换栅极。在本实施例中，选择ILD层220的组分，以通过离子注入工艺有效地实现气隙密封的扩展。ILD层220包括一种或多种合适的介电材料，诸如SiN、SiOC、SiOCN、SiCN、Si、SiGe、SiO2、TiO2、Al2O3、Ge、W、TaN、TiN、HfO2、ZrO2、La2O3或它们的组合。ILD层220的形成包括沉积(诸如CVD或高密度等离子体CVD-HDPCVD)和CMP以提供平坦化的顶面。在一些实施例中，操作116也包括形成蚀刻停止层222以提供操作期间的蚀刻停止从而形成至S/D部件218的接触件。蚀刻停止层222与ILD层220的组分不同以具有期望的蚀刻选择性。在一些实施例中，蚀刻停止层222包括SiCN、SiOCN、SiOC、SiN以及它们的组合中的一种。
方法100进入操作118以用于栅极替换。在操作118中，用具有高k介电材料和金属的栅极堆叠件208替换伪栅极。操作118包括实施蚀刻工艺以选择性地去除伪栅极，从而产生栅极腔；以及在栅极腔中沉积栅极材料(包括高k介电材料和金属)；以及实施CMP工艺以从ILD层220去除过量的栅极材料。具体地，栅极堆叠件208包括栅电极210和栅极介电层212。栅电极210包括金属、金属合金或它们的组合。栅极介电层212包括高k介电材料。由于栅极介电层212共形地沉积在栅极腔中，并且因此是如图2B和图2C中示出的U形。
栅极介电层212和栅电极210均可以包括多个子层。在一些实施例中，栅极介电层212包括高k介电材料，其为金属氧化物或金属氮化物，诸如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物(SiON)或其它合适的高k介电材料。栅极介电层212还可以包括夹置于高k介电材料层和鳍式有源区域之间的界面层。界面层可以包括氧化硅、氮化硅、氮氧化硅和/或其它合适的材料。通过诸如ALD，CVD、臭氧氧化等的合适的方法沉积界面层。通过合适的技术在界面层(如果存在界面层)上沉积高k介电层，诸如ALD、CVD、金属有机CVD(MOCVD)、PVD、热氧化、它们的组合和/或其它合适的技术。
栅电极210可以包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W或任何合适的材料。在一些实施例中，不同的金属材料用于具有相应的功函的nFET和pFET。例如，栅电极210可以包括覆盖层、功函金属层和填充金属层。在进一步的实施例中，覆盖层包括通过适当的沉积技术(诸如ALD)形成的氮化钛、氮化钽或其它合适的材料。填充金属层包括物理汽相沉积(PVD)或其它合适的沉积技术沉积的铝、铜、硅化物、合适的其它金属或金属合金。
功函金属层包括具有适当功函的金属或金属合金导电层，从而使得对应的FET的器件性能增强。功函(WF)金属层对于pFET和nFET是不同的，分别称为n型WF金属和p型WF金属。WF金属的选择取决于将要在有源区域上形成的FET。例如，n型WF金属是具有第一功函的金属，从而使得相关的nFET的阈值电压减小。例如，n型WF金属具有约4.2eV或更低的功函。p型WF金属是具有第二功函的金属，从而使得相关的pFET的阈值电压减小。例如，p型功函金属具有约5.2eV或更高的WF。在一些实施例中，n型WF金属包括钽(Ta)。在其它实施例中，n型WF金属包括钛铝(TiAl)、氮化钛铝(TiAlN)或它们的组合。在一些实施例中，p型WF金属包括氮化钛(TiN)或氮化钽(TaN)。在其它实施例中，p型WF金属包括TiN、TaN、氮化钨(WN)、钛铝(TiAl)或它们的组合。
参照图3，方法100可以包括操作120，以在半导体结构200上形成具有开口304的图案化掩模层302，以限定将要形成一个或多个气隙的多个区域。在本实施例中，气隙仅形成在STI部件204上，而不形成在鳍式有源区域206上。图3是半导体结构200的顶视图。图3中示出了透明的图案化掩模层302，以便于更好的查看。图案化掩模层302可以是软掩模，诸如通过光刻工艺形成的光刻胶；或可选地，是通过沉积、光刻工艺和蚀刻形成的硬掩模。
参照图4，方法100进入操作122，其中，去除外栅极间隔件216，在内栅极间隔件214和ILD层220之间产生气隙402。图4是在STI部件204上沿着X方向(沿着图3的虚线AA’，但是处于通过操作122形成气隙402的不同制造阶段)的半导体结构200的截面图。在一些实施例中，使用图案化掩模层302作为蚀刻掩模，通过蚀刻工艺去除外栅极间隔件216，从而仅去除外栅极间隔件216的位于STI部件204上的部分但是保留外栅极间隔件216的位于鳍式有源区域206内的部分。相邻栅极堆叠件208之间的ILD层220跨越宽度d1。气隙402具有高度h1和宽度d2。在一些实例中，比率d2/d1大于10％。在一些实例中，比率d2/d1在10％和30％之间的范围内。在又一些实例中，高度h1小于200nm；宽度d1在5nm和50nm之间的范围内；并且宽度d2小于10nm。
蚀刻工艺可以是干蚀刻、湿蚀刻或它们的组合。图案化掩模层302的多个开口304被设计为限定形成多个气隙的多个区域，但蚀刻工艺仍设计为对其它部件(诸如内栅极间隔件214、蚀刻停止层222以及甚至ILD层220)具有蚀刻选择性。此外，外栅极间隔件216的组分与那些部件的组分不同，并且蚀刻工艺选择蚀刻剂以选择性地去除外栅极间隔件216而基本不蚀刻包括诸如内栅极间隔件214和蚀刻停止层222的其它部件。
参照图5，方法100进入操作124，其中，对ILD层220实施离子注入工艺，从而扩展ILD层220以覆盖气隙402。离子注入工艺将一种或多种掺杂剂引入ILD层220的顶部502，将顶部502转换为注入部分，并且留下ILD层220的底部504作为非注入部分。离子注入工艺增加顶部502的体积，横向扩展顶部502并且密封气隙402。顶部502的扩展部分506用作盖以密封气隙402，因此也称为扩展盖506。在一些实施例中，使用图案化掩模302实施离子注入工艺，以控制仅注入至期望区域。可以在操作124之后去除图案化掩模层302。当ILD层220的顶部502扩展时，推动蚀刻停止层222的对应部分以到达内栅极间隔件214，从而覆盖气隙402。
在离子注入工艺之后，ILD层220的顶部502具有高度h2和顶部宽度d1+2*d2。气隙402限定在ILD层220和栅极堆叠件208之间。更具体地，气隙402垂直和水平地跨越在内栅极间隔件214和蚀刻停止层222之间。为了密封气隙402，ILD层220需要在每个边缘处扩展d2以到达内栅极间隔件214。换句话说，ILD层的顶面从原始宽度d1水平扩展至扩展宽度d1+2*d2。扩展的体积与d2/d1成比例。例如，如果气隙402上方的扩展部分是三角形，则顶部502的原始体积上方的最终体积等于d2/d1。ILD层220的顶部502的体积扩展与掺杂剂浓度相关，并且在一些实施例中，与掺杂剂浓度成正比例。例如，如果顶部502的相对体积扩展可以达到d2/d1，则气隙将被密封。在本实施例中，根据一些实施例，比率d2/d1大于10％，或在从10％至30％的范围内。离子注入工艺设计为使掺杂剂浓度足够高以确保通过扩展密封气隙402。在一些实施例中，通过离子束电流和离子注入工艺的注入持续时间的组合来控制掺杂剂浓度，以扩展ILD层220(诸如多于10％)，从而密封气隙402。因此，根据一些实施例，离子注入工艺具有高剂量，诸如顶部502的掺杂剂浓度在1E11至1E17atoms/cm2(个原子/平方厘米)的范围内。
在一些实施例中，通过注入倾斜角从60°改变至-60°来实施离子注入工艺，同时使半导体衬底202旋转以在各个方向上进行注入，从而控制ILD层220的顶部502的扩展盖506的形状。扩展盖506的形状也与顶部502的高度h2有关，由注入能量控制该形状。高度h2控制在一定范围内，诸如小于50nm，以使气隙402的体积最大化并且具有有效的密封效果。通过控制剂量、离子束电流、注入持续时间、注入能量和注入倾斜角的组合，使ILD层220扩展以有效地密封气隙402并且可以实现扩展盖506的各种形状，诸如如图6中示出的三角形形状；或如图7示出的正方形形状；或如图8中示出的弯曲形状。
在一些实施例中，离子注入工艺包括向ILD层220引入第一掺杂剂物质，其中，第一掺杂剂物质选自镍(Ni)、氟(F)、氟化硼(BF)、锗(Ge)、钴(Co)、氩(Ar)、砷(As)、镓(Ga)、锑(Sb)、铟(In)以及它们的组合。在一些实施例中，离子注入工艺包括引入第一掺杂剂物质并且另外引入第二掺杂剂物质，第二掺杂剂物质选自碳(C)、磷(P)、硅(Si)、氢(H)、氮(N)、氧(O)以及它们的组合。在这种情况下，根据一些实施例，顶部502中的总掺杂剂浓度可以在从1E11至1E17atoms/cm2的范围内。
在其它方法中，可以通过沉积来密封气隙。如果沉积的密封膜具有良好的均匀性，则密封膜将填充气隙并且破坏气隙。如果沉积的密封膜具有差的均匀性，则当图案密度不均匀时，由于密封膜不均匀地填充气隙而将使密封膜经受负载效应。通过所公开的方法，当通过离子注入工艺将掺杂剂引入ILD层时，通过横向扩展ILD层来密封气隙。此外，通过离子束电流、注入持续时间、注入能量和注入倾斜角的组合来设计离子注入工艺，从而使得ILD层220扩展以有效地密封气隙402并且具有最大化的气隙402体积。通过调整上述工艺参数的组合，使ILD层220的顶部502扩展以形成具有各种形状的扩展盖506，诸如如图6中示出的三角形形状；或如图7示出的正方形形状；或如图8中示出的弯曲形状，以平衡密封效果和气隙体积。例如，图6中的三角形形状具有最大的气隙体积，图7中的方形形状具有最大的密封效果，并且图8中的弯曲形状的气隙体积大于图7的气隙体积并且其密封效果比图6的密封效果更好。
方法100可以包括在上述操作之前、期间或之后的其它操作。例如，方法100包括操作126以形成如图9所示的位于S/D部件218上的接触件902。注意，图9是沿着鳍式有源区域206切割的半导体结构200的截面图，其中，ILD层220未被注入并且因此未扩展。接触件902是导电部件，将对应的S/D部件218电连接至上面的互连结构904，以形成集成电路。接触件902包括导电材料(包括金属和金属合金)的插塞，诸如钨(W)、铝(Al)、铝合金、铜(Cu)、钴(Co)、镍(Ni)、其它合适的金属/金属合金或它们的组合。注意，鳍式有源区域206内的ILD层220未被注入并且未扩展。在一些实施例中，接触件902还包括内衬接触孔的阻挡层，以增强材料集成，诸如增加粘附力并且减少相互扩散。阻挡层可包括多于一个的膜，诸如钛和氮化钛(Ti/TiN)、钽和氮化钽(Ta/TaN)、硅化铜或其它合适的材料。根据一些实施例，接触件902的形成包括图案化ILD层220以形成接触孔；沉积阻挡层以内衬接触孔，在接触孔内的阻挡层上沉积导电材料；以及实施CMP工艺以去除过量的导电材料并且平坦化顶面。
方法100也可以包括在半导体结构200上形成互连结构904的操作128。互连结构904包括各个导电部件以连接各个器件部件(诸如栅极堆叠件208和S/D部件218)以形成功能电路。具体地，互连结构904包括多个金属层(以提供水平电布线)和通孔(以提供垂直电布线)。互连结构904也包括多个ILD层906，以使各个导电部件彼此隔离。例如，多个ILD层906可以包括低k介电材料或其它合适的介电材料，诸如氧化硅。在用于说明的一些实例中，互连结构904包括第一金属层910、位于第一金属层910上方的第二金属层914以及位于第二金属层914上方的第三金属层918。每个金属层均包括多条金属线。互连结构904还包括通孔908、912和916，以在相邻金属层中的金属线之间或第一金属层910的第一金属线和器件(诸如S/D部件218的栅极堆叠件208或接触件902)之间提供垂直互连。在各个实施例中，互连结构904的导电部件(诸如金属线和通孔)包括铝、铜、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合。互连结构904可以使用通过沉积和蚀刻形成的铝互连件，或通过镶嵌工艺形成的铜互连件。在铜互连件中，导电部件包括铜，并且还可以包括阻挡层。由镶嵌工艺形成铜互连结构。镶嵌工艺包括沉积ILD层；图案化ILD层以形成沟槽；沉积各种导电材料(诸如阻挡层和铜)；并且实施CMP工艺。
在方法100中，光刻工艺和图案化的硬掩模用于不同的操作中并且在下面共同描述。图案化掩模层可以是沉积并且图案化的硬掩模。硬掩模包括介电材料，诸如半导体氧化物、半导体氮化物、半导体氮氧化物、半导体碳化物或它们的组合。可以通过热生长、原子层沉积(ALD)、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、其它合适的沉积工艺来形成硬掩模层。硬掩模的形成包括沉积，形成图案化光刻胶层，以及使用图案化光刻胶层作为蚀刻掩模来蚀刻硬掩模。图案化硬掩模层的蚀刻工艺可以包括湿蚀刻、干蚀刻或它们的组合。例如，可以通过稀释的氢氟溶液蚀刻硬掩模层中的氧化硅膜，并且可以通过磷酸溶液蚀刻硬掩模层中的氮化硅膜。
光刻胶层包括光敏材料，该光敏材料使光刻胶层在暴露于光(诸如紫外(UV)光、深UV(DUV)光或极UV(EUV)光)时经历性质变化(诸如化学变化)。该性质变化可以用于通过提及的显影工艺去除光刻胶层的曝光或未曝光部分。形成图案化光刻胶层的该过程称为光刻工艺。光刻工艺可以包括旋涂光刻胶层、软烘烤光刻胶层、掩模对准、曝光、曝光后烘烤、显影光刻胶层、清洗和干燥(例如，硬烘烤)。可选地，可以通过诸如无掩模光刻、电子束写入和离子束写入的其它方法来实现、补充或替换光刻工艺。
公开了具有气隙的半导体结构及其制造方法。该方法包括去除外栅极间隔件以形成气隙；并且实施离子注入工艺以将一种或多种掺杂剂物质引入ILD层，从而扩展ILD层以覆盖气隙。可以在本发明的各个应用中存在多种优势。没有特定的优势对所有实施例都是需要的，并且不同的实施例可以提供不同的优势。一些实施例中的一个优势是在没有沉积的情况下密封气隙，以实现优化的密封效果和增加的气隙体积。此外，通过离子束电流、注入持续时间、注入能量和注入倾斜角的组合来设计离子注入工艺，从而使得ILD层扩展以有效地密封气隙并且具有最大化的气隙402体积。通过调整上述工艺参数的组合，ILD层的扩展盖可以具有各种形状，诸如三角形；或方形；或弯曲形状以平衡密封效果和气隙体积。
因此，本发明根据一些实施例提供了制造半导体结构的方法。该方法包括接收具有有源区域和隔离区域的衬底；在衬底上形成栅极堆叠件，该栅极堆叠件从有源区域延伸至隔离区域；在栅极堆叠件的侧壁上形成内栅极间隔件和外栅极间隔件；在衬底上形成ILD层；去除隔离区域中的外栅极间隔件，从而在内栅极间隔件和ILD层之间产生气隙；并且对ILD层实施离子注入工艺，从而扩展ILD层以覆盖气隙。
在实施例中，实施离子注入工艺包括实施离子注入工艺以将以下掺杂剂物质引入所述层间介电层中，所述掺杂剂物质选自于镍(Ni)、氟(F)、氟化硼(BF)、锗(Ge)、钴(Co)、氩(Ar)、砷(As)、镓(Ga)、锑(Sb)、铟(In)以及它们的组合。
在实施例中，实施所述离子注入工艺包括实施所述离子注入工艺以将掺杂剂物质引入所述层间介电层中，所述掺杂剂物质选自于碳(C)、磷(Si)、硅(Si)、氢(H)、氮(N)、氧(O)以及它们的组合。
在实施例中，实施所述离子注入工艺包括使用掺杂剂浓度在从1E11至1E17原子/平方厘米的范围内的高剂量来实施所述离子注入工艺。
在实施例中，方法还包括，形成具有开口的图案化材料层，以在去除所述隔离区域中的外栅极间隔件之前，暴露所述层间介电层和所述隔离区域内的外栅极间隔件，其中，去除所述隔离区域中的外栅极间隔件包括实施蚀刻工艺以通过所述图案化材料层的开口选择性地去除所述外侧壁间隔件。
在实施例中，实施所述离子注入工艺包括通过所述图案化材料层的开口对所述层间介电层实施所述离子注入工艺。
在实施例中，所述内栅极间隔件和所述外栅极间隔件的形成包括：在所述衬底和所述栅极堆叠件上沉积第一介电材料层；在所述第一介电材料层上沉积第二介电材料层，所述第二介电材料层的组分与所述第一介电材料层的组分不同；以及对所述第一介电材料层和所述第二介电材料层实施各向异性蚀刻工艺。
在实施例中，形成所述层间介电层包括：在所述衬底上和所述外栅极间隔件的侧壁上形成蚀刻停止层；在所述蚀刻停止层上形成第三介电材料，所述第三介电材料的组分与所述蚀刻停止层的组分不同；以及对所述第三介电材料层实施化学机械抛光工艺。
在实施例中，所述第三介电材料层包括SiN、SiOC、SiOCN、SiCN、Si、SiGe、W、TiN、HfO2、ZrO2、La2O3以及它们的组合中的一种。本发明也根据一些实施例提供了方法。该方法包括接收衬底，该衬底具有STI部件和有源区域、位于衬底上的栅极堆叠件、位于栅极堆叠件的侧壁上内栅极间隔件和外栅极间隔件；以及在衬底上形成ILD层，其中，栅极堆叠件从有源区域延伸至STI部件。该方法还包括去除外栅极间隔件的位于STI部件上的部分，从而在内栅极间隔件和ILD层之间产生间隙；以及对ILD层实施离子注入工艺，从而扩展ILD层以覆盖气隙。
在实施例中，实施离子注入工艺包括实施离子注入工艺以将第一掺杂剂物质和第二掺杂剂物质引入所述层间介电层中，其中，所述第一掺杂剂物质选自于镍(Ni)、氟(F)、氟化硼(BF)、锗(Ge)、钴(Co)、氩(Ar)、砷(As)、镓(Ga)、锑(Sb)、铟(In)以及它们的组合；并且第二掺杂剂物质选自于碳(C)、磷(Si)、硅(Si)、氢(H)、氮(N)、氧(O)以及它们的组合。
在实施例中，实施所述离子注入工艺包括使用总掺杂剂浓度在从1E11至1E17原子/cm2的范围内的高剂量来实施所述离子注入工艺。
在实施例中，方法还包括，形成具有开口的图案化材料层，以暴露所述层间介电层的部分和所述外栅极间隔件的位于所述浅沟槽隔离部件上的部分，其中，去除所述外栅极间隔件的部分包括实施蚀刻工艺以通过所述图案化材料层的开口选择性地蚀刻所述外侧壁间隔件的部分。
在实施例中，实施所述离子注入工艺包括通过所述图案化材料层的开口对所述层间介电层的部分实施所述离子注入工艺。
在实施例中，实施所述离子注入工艺包括通过在所述衬底旋转时将注入倾斜角从60°改变至-60°来实施所述离子注入工艺。
在实施例中，实施所述离子注入工艺包括利用离子束电流和注入持续时间来实施所述离子注入工艺，以使所述层间介电层横向扩展多于10％。
本发明还根据一些实施例提供了半导体结构。半导体结构包括具有有源区域和隔离区域的衬底；位于衬底上并且从有源区域延伸至隔离区域的栅极堆叠件；位于栅极堆叠件的侧壁上的栅极间隔件；以及位于衬底上并且限定ILD层和栅极间隔件之间的气隙的ILD层，其中，ILD层包括顶部，该顶部横向延伸至栅极间隔件并且覆盖气隙。
在实施例中，所述层间介电层包括底部和所述顶部；所述层间介电层的底部包括介电材料；以及所述层间介电层的顶部包括掺杂有镍(Ni)、氟(F)、氟化硼(BF)、锗(Ge)、钴(Co)、氩(Ar)、砷(As)、镓(Ga)、锑(Sb)、铟(In)以及它们的组合中的一种的介电材料。
在实施例中，所述介电材料选自于SiN、SiOC、SiOCN、SiCN、Si、SiGe、SiO2、TiO2、Al2O3、Ge、W、TaN、TiN、HfO2、ZrO2、La2O3。
在实施例中，所述层间介电层的顶部在所述气隙上方具有弯曲形状。
虽然已经详细描述了本发明的一些实施例的优势，但是应当理解，在不脱离由所附权利要求限定的本公开的精神和范围的情况下，可以对本文进行各种改变、替换和更改。此外，本申请的范围不旨在限于说明书中描述的工艺、机械、制造和物质组分、装置、方法和步骤的特定实施例。根据本发明，本领域普通技术人员将从本发明容易理解，目前存在或之后发展的工艺、机械、制造、物质组分、装置、方法或步骤，其实施基本相同的功能或实现基本相同的结果，因为可以利用本文描述的对应的实施例。因此，所附权利要求旨在在其范围内包括这样的工艺、机械、制造、物质组分、装置、方法或步骤。

Claims (10)

1.一种制造半导体结构的方法，包括：
接收具有有源区域和隔离区域的衬底；
在所述衬底上形成栅极堆叠件，并且所述栅极堆叠件从所述有源区域延伸至所述隔离区域；
在所述栅极堆叠件的侧壁上形成内栅极间隔件和外栅极间隔件；
在所述衬底上形成层间介电(ILD)层；
去除所述隔离区域中的外栅极间隔件，从而在所述内栅极间隔件和所述层间介电层之间产生气隙；以及
对所述层间介电层实施离子注入工艺，从而扩展所述层间介电层以覆盖所述气隙。
2.根据权利要求1所述的方法，其中，实施离子注入工艺包括实施离子注入工艺以将以下掺杂剂物质引入所述层间介电层中，所述掺杂剂物质选自于镍(Ni)、氟(F)、氟化硼(BF)、锗(Ge)、钴(Co)、氩(Ar)、砷(As)、镓(Ga)、锑(Sb)、铟(In)以及它们的组合。
3.根据权利要求1所述的方法，其中，实施所述离子注入工艺包括实施所述离子注入工艺以将掺杂剂物质引入所述层间介电层中，所述掺杂剂物质选自于碳(C)、磷(Si)、硅(Si)、氢(H)、氮(N)、氧(O)以及它们的组合。
4.根据权利要求1所述的方法，其中，实施所述离子注入工艺包括使用掺杂剂浓度在从1E11至1E17原子/平方厘米的范围内的高剂量来实施所述离子注入工艺。
5.根据权利要求1所述的方法，还包括，形成具有开口的图案化材料层，以在去除所述隔离区域中的外栅极间隔件之前，暴露所述层间介电层和所述隔离区域内的外栅极间隔件，其中，去除所述隔离区域中的外栅极间隔件包括实施蚀刻工艺以通过所述图案化材料层的开口选择性地去除所述外侧壁间隔件。
6.根据权利要求5所述的方法，其中，实施所述离子注入工艺包括通过所述图案化材料层的开口对所述层间介电层实施所述离子注入工艺。
7.根据权利要求1所述的方法，其中，所述内栅极间隔件和所述外栅极间隔件的形成包括：
在所述衬底和所述栅极堆叠件上沉积第一介电材料层；
在所述第一介电材料层上沉积第二介电材料层，所述第二介电材料层的组分与所述第一介电材料层的组分不同；以及
对所述第一介电材料层和所述第二介电材料层实施各向异性蚀刻工艺。
8.根据权利要求7所述的方法，其中，形成所述层间介电层包括：
在所述衬底上和所述外栅极间隔件的侧壁上形成蚀刻停止层；
在所述蚀刻停止层上形成第三介电材料，所述第三介电材料的组分与所述蚀刻停止层的组分不同；以及
对所述第三介电材料层实施化学机械抛光工艺。
9.一种制造半导体结构的方法，包括：
接收衬底，其中，所述衬底具有浅沟槽隔离(STI)部件和有源区域，位于所述衬底上的栅极堆叠件、位于所述栅极堆叠件的侧壁上的内栅极间隔件和外栅极间隔件，以及在所述衬底上形成层间介电(ILD)层，其中，所述栅极堆叠件从所述有源区域延伸至所述浅沟槽隔离部件上；
去除所述外栅极间隔件的位于所述浅沟槽隔离部件上的部分，从而在所述内栅极间隔件和所述层间介电层之间产生气隙；以及
对所述层间介电层实施离子注入工艺，从而扩展所述层间介电层以覆盖所述气隙。
10.一种半导体结构，包括：
衬底，具有有源区域和隔离区域；
栅极堆叠件，位于所述衬底上并且从所述有源区域延伸至所述隔离区域；
栅极间隔件，位于所述栅极堆叠件的侧壁上；以及
层间介电(ILD)层，位于所述衬底上并且限定所述层间介电层和所述栅极间隔件之间的气隙，其中，所述层间介电层包括顶部，所述顶部横向延伸至所述栅极间隔件并且覆盖所述气隙。
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