CN107818946A - 具有阈值电压不同的晶体管的cmos电路及其制造方法 - Google Patents

具有阈值电压不同的晶体管的cmos电路及其制造方法 Download PDF

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CN107818946A
CN107818946A CN201710816705.4A CN201710816705A CN107818946A CN 107818946 A CN107818946 A CN 107818946A CN 201710816705 A CN201710816705 A CN 201710816705A CN 107818946 A CN107818946 A CN 107818946A
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effect transistor
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王维
王维一
洪俊九
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Samsung Electronics Co Ltd
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Abstract

提供了一种互补金属氧化物半导体(CMOS)电路及其制造方法。所述CMOS电路包括基底和位于基底上的多个场效应晶体管。每个场效应晶体管包括：多个接触件；源极，连接到所述多个接触件中的一个接触件；漏极，连接到所述多个接触件中的另一接触件；栅极；间隔件，位于栅极与接触件之间。所述多个场效应晶体管中的一个的间隔件具有比所述多个场效应晶体管中的另一个的间隔件的气隙大的气隙。

Description

具有阈值电压不同的晶体管的CMOS电路及其制造方法
本发明专利申请要求在2016年9月12日提交的题为“METHOD OF FORMING MULTI-Vt FOR CMOS USING AIRGAP SPACERS(使用气隙间隔件形成多Vt CMOS的方法)”的序列号为62/393,620的美国临时专利申请以及在2016年11月10号提交的题为“COMPLIMENTARYMETAL-OXIDE-SEMICONDUCTOR CIRCUIT HAVING TRANSISTORS WITH DIFFERENT THRESHOLDVOLTAGES AND METHOD OF MANUFACTURING THE SAME(具有阈值电压不同的晶体管的互补金属氧化物半导体电路及其制造方法)”的序列号为15/348,916号美国非临时专利申请的优先权和权益，所述专利申请的全部内容通过引用包含于此。
技术领域
本发明的示例实施例的方面涉及一种包括具有不同阈值电压(Vt)的多个晶体管的互补金属氧化物半导体(CMOS)电路以及一种制造该互补金属氧化物半导体电路的方法。
背景技术
随着集成电路装置的尺寸减小，正进行尝试来提高晶体管(例如，场效应晶体管或FET)在基底上的密度。另外，已经进行尝试提供诸如互补金属氧化物半导体(CMOS)电路的电路装置，所述CMOS电路包括具有修改的阈值电压(Vt)的FET使得CMOS电路的各种FET具有彼此不同的阈值电压。这样的电路装置可以称作多Vt(multi-Vt)电路装置或mVt电路装置。
制造多Vt电路装置的传统方法包括改变晶体管的栅极中的功函数金属(WFM)堆叠件的厚度。用于n型FET(nFET)的WFM可以包括反应性WFM，诸如，铝、铪、钛等)，用于p型FET(pFET)的WFM可以包括中间带隙(midgap)WFM，诸如，具有或不具有反应性金属的氮化钽(TaN)、氮化钛(TiN)等。
已经证明的是，改变晶体管中的WFM堆叠件的厚度(例如，增加WFM堆叠件中的某些材料或层的厚度)调节了WFM堆叠件的有效功函数(eWF)，从而调节了晶体管的Vt。例如，增加中间带隙WFM的厚度已经被证明使eWF增加，且增加反应性WFM的厚度已经被证明使eWF减小。然而，当节点尺寸继续减小时(例如，7nm和更小的节点)，可用于晶体管中WFM堆叠件的空间进一步减小。这样，随着节点尺寸减小，增加WFM层的厚度来调节Vt变得(或者会是)不切实际。另外，用于形成WFM堆叠件的层的当前制造工艺不能为这种调节Vt方法变得经济提供必要的精度和可重复性。
鉴于与改变晶体管中WFM堆叠件的厚度相关的缺点，已经研究了调节晶体管的Vt的其它方法。这样的其它方法包括将锗(Ge)添加到晶体管的硅(Si)沟道(这已经被证明在不改变WFM堆叠件的情况下调节晶体管的Vt)，以及在形成替代金属栅极(replacementmetal gate)的步骤期间晶体管的高温退火(例如，直接O2退火)。然而，这些方法均具有各种缺点，诸如增加了界面缺陷状态(前者)和不期望地增大了电阻(后者)，从而使这些方法不那么可取。
发明内容
本公开针对包括具有彼此不同的阈值电压(Vt)的多个晶体管的互补金属氧化物半导体(CMOS)电路及其制造方法的各种实施例。
根据本发明的实施例，一种互补金属氧化物半导体(CMOS)电路包括基底和位于基底上的多个场效应晶体管。每个场效应晶体管包括：多个接触件；源极，连接到所述多个接触件中的一个接触件；漏极，连接到所述多个接触件中的另一接触件；栅极；间隔件，位于栅极与接触件之间。所述多个场效应晶体管中的一个的间隔件具有比所述多个场效应晶体管中的另一个的间隔件的气隙大的气隙。
所述多个场效应晶体管中的所述一个的间隔件可以具有比所述多个场效应晶体管中的所述另一个的间隔件的整体密度小的整体密度。
每个场效应晶体管的栅极可以包括金属栅极以及形成在金属栅极的底部处和外围周围的高k介电材料，每个金属栅极可以包括相同的材料。所述多个场效应晶体管中的所述一个的金属栅极的有效功函数可以与所述多个场效应晶体管中的所述另一个的金属栅极的有效功函数不同。
所述多个场效应晶体管中的所述另一个的间隔件可以不具有气隙。
每个场效应晶体管的栅极可以包括相同的功函数金属。
根据本发明的另一实施例，一种制造互补金属氧化物半导体(CMOS)电路的方法包括以下步骤：在基底上形成多个场效应晶体管；选择性地蚀刻所述多个场效应晶体管中的一个场效应晶体管的间隔件；在所述多个场效应晶体管中的所述一个场效应晶体管中形成另一间隔件，所述另一间隔件包括气隙。
该方法还可以包括在所有的场效应晶体管上形成一个连续的密封剂层。
形成场效应晶体管的步骤可以包括替代金属栅极工艺。
形成所述另一间隔件的步骤可以包括化学气相沉积工艺、等离子体增强化学气相沉积工艺、低压化学气相沉积工艺、减压化学气相沉积工艺或原子层沉积工艺。
形成所述另一间隔件的步骤还可以包括在氧、臭氧和/或氧化环境下沉积原硅酸四乙酯。
形成所述另一间隔件的步骤还可以包括在氢或还原环境下沉积氮化硅、碳氮氧化硅或碳氮化硅硼。
根据本发明的另一实施例，一种制造互补金属氧化物半导体(CMOS)电路的方法包括以下步骤：在基底上形成多个场效应晶体管，每个场效应晶体管包括多个接触件、连接到所述多个接触件中的一个接触件的源极、连接到所述多个接触件中的另一接触件的漏极、栅极以及位于栅极与接触件之间的间隔件；蚀刻来自多个场效应晶体管中的仅仅一些场效应晶体管的间隔件；在间隔件被蚀刻的场效应晶体管中形成另一间隔件，所述另一间隔件包括气隙。
在蚀刻间隔件的步骤之后并且在形成另一间隔件的步骤之前，场效应晶体管中的第一组可以包括间隔件，场效应晶体管中的第二组可以具有位于栅极和接触件之间的未被占有的空隙。
在形成所述另一间隔件的步骤之后，场效应晶体管中的第二组可以具有与场效应晶体管中的第一组的阈值电压不同的阈值电压。
形成多个场效应晶体管的步骤可以包括使栅极平坦化。
蚀刻间隔件的步骤可以直接发生在使栅极平坦化的步骤之后。
形成所述另一间隔件的步骤可以包括化学气相沉积工艺、等离子体增强化学气相沉积工艺、低压化学气相沉积工艺、减压化学气相沉积工艺或原子层沉积工艺。
形成所述另一间隔件的步骤还可以包括在氧、臭氧和/或氧化环境下沉积原硅酸四乙酯。
形成所述另一间隔件的步骤还可以包括在氢或还原环境下沉积氮化硅、碳氮氧化硅(SiOCN)或碳氮化硅硼(SiBCN)。
形成场效应晶体管的步骤可以包括替代金属栅极工艺。
基底可以具有(100)或(110)的晶体学取向。
基底可以是体基底或绝缘体上硅基底。
提供本发明内容以介绍对下面在具体实施方式中进一步描述的本发明的示例实施例的特征和构思的选择。本发明内容不意图确定所要求保护主题的关键特征或必要特征，也不意图用于限制所要求保护主题的范围。根据一个或更多个示例实施例的一个或更多个所描述的特征可以与根据一个或更多个示例实施例的一个或更多个其它所描述的特征相结合，以提供可工作的装置。
附图说明
图1示出了传统的场效应晶体管(FET)；
图2示出了根据本发明的示例实施例的FET；以及
图3至图6示出了根据本发明的示例实施例的制造互补金属氧化物半导体(CMOS)电路的方法。
具体实施方式
本发明针对包括具有彼此不同的阈值电压(Vt)的多个晶体管的互补金属氧化物半导体(CMOS)电路以及制造该互补金属氧化物半导体电路的方法的各种示例实施例。在一个示例实施例中，CMOS电路包括基底和处于基底上的多个场效应晶体管。每个场效应晶体管可以包括：多个接触件；源极，连接到多个接触件中的一个；漏极，连接到多个接触件中的另一个；栅极；间隔件，位于栅极与接触件之间，场效应晶体管中的一个的间隔件可以具有比场效应晶体管中的另一个的间隔件大的气隙(air gap)。因此，提供了包括具有彼此不同的Vt的晶体管的CMOS电路(例如，多Vt CMOS电路)。在其它实施例中，提供了制造包括具有彼此不同的Vt的晶体管的CMOS电路。根据本发明的实施例的CMOS电路可以用在例如微处理器、存储芯片或电路等中。
将在下文中参照附图更详细地描述本发明的示例实施例。然而，本发明可以以各种不同的形式来实施并且不应解释为受限于仅在这里示出的实施例。相反，提供这些实施例作为示例，从而本公开将是彻底的和完整的，并且将向本领域的技术人员充分地传达本发明的方面和特征。因此，可以不描述对本领域普通技术人员而言完全理解本发明的方面和特征所不必要的工艺、元件和技术。除非另外注明，否则贯穿附图和书面描述，同样的附图标记表示同样的元件，因此，可以不重复对其的描述。
在附图中，为了清楚，可以夸大和/或简化元件和区域的相对尺寸。为了容易说明，在这里可以使用诸如“在……之下”、“在……下方”、“下面的”、“在……下面”、“在……上方”、“上面的”等的空间相对术语来描述如图中所示的一个元件或特征与另外的元件或特征的关系。将理解的是，空间相对术语意图包含除了在图中描绘的方位之外的装置在使用或操作中的不同方位。例如，如果附图中的装置被翻转，则被描述为“在”其它元件或特征“下方”或“之下”或者“下面”的元件随后将定位于所述其它元件或特征“上方”。因此，示例术语“在……下方”和“在……下面”可包含上方和下方两种方位。所述装置可被另外定位(例如，旋转90度或者在其它方位)，并且应当相应地解释这里使用的空间相对描述符。
将理解的是，尽管这里可以使用术语“第一”、“第二”、“第三”等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语限制。这些术语用来将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开。因此，在不脱离本发明的精神和范围的情况下，下面讨论的第一元件、组件、区域、层或部分可被称作第二元件、组件、区域、层或部分。
将理解的是，当元件被称作为“在”另一元件“上”、“连接到”或“结合到”另一元件时，该元件可直接在所述另一元件上、直接连接到或直接结合到所述另一元件，或者可以存在一个或更多个中间元件。另外，还将理解的是，当元件被称作“在(位于)”两个元件“之间”时，该元件可以是位于所述两个元件之间唯一的元件，或者也可以存在一个或更多个中间元件。
这里使用的术语是出于描述具体实施例的目的，而并不意图限制本发明。如这里使用的，除非上下文另外明确指出，否则单数形式“一个(种、者)”和“所述(该)”也意图包括复数形式。还将理解的是，术语“包含”和“包括”及其变型用在本说明书中时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。即，在这里描述的工艺、方法和算法不限制于所指明的操作，而是可以包括附加的操作或者可以省略一些操作，所述操作的顺序可以根据一些实施例而改变。如在这里所使用的，术语“和/或”包括一个或更多个相关所列项的任何和所有组合。诸如“……中的至少一个(种)”位于一列元件之后时，修饰整列的元件，而不是修饰该列的个别元件。
如在这里使用的，术语“基本上”、“大约”和类似术语被用作近似的术语而不是程度的术语，并意图解释将由本领域普通技术人员所认识到的测量或计算值中的固有偏差。此外，当描述本发明的实施例时使用“可以”表示“本发明的一个或更多个实施例”。如这里使用的，可以认为术语“使用”及其变型分别与术语“利用”及其变型同义。另外，术语“示例”意图表示例子或例示。
除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的意思相同的意思。还将理解的是，除非这里明确这样定义，否则术语(诸如在通用的字典中定义的术语)应该被解释为具有与相关领域的环境中和/或本说明书的上下文中它们的意思一致的意思，而不应以理想化的或过于形式化的含义来解释。
图1示出了示出了传统的场效应晶体管(FET)10。FET 10包括连接到漏极(例如，漏区)16的第一接触件(或通孔)11和连接到源极(例如，源区)17的第二接触件(或通孔)12。漏极16和源极17可以是另外未掺杂的半导体沟道18的掺杂区。未掺杂的半导体沟道18可以包括例如硅(Si)、硅-锗(SiGe)或任何合适的III-V族半导体。第一接触件11和第二接触件12可以包括金属，并且可以延伸穿过介电材料以分别接触漏极16和源极17。第一接触件11和第二接触件12可以被称作或者可以分别电连接到第一电极16和第二电极17(例如，漏电极和源电极)。FET 10还包括间隔件13，间隔件13在栅极(即，栅极区)周围并且在第一接触件11和第二接触件12与栅极之间延伸。间隔件13用作电绝缘件以使栅极与漏极16和源极17绝缘以及与第一接触件11和第二接触件12绝缘，并且还用作用于栅极的氧扩散阻挡件。间隔件13可以包括氧化物或氮化物，诸如氮化硅(例如，Si3N4)、氧化硅(例如，SiO2)、碳氮氧化硅(SiOCN)或碳氮化硅硼(SiBCN)。栅极包括功函数金属栅极14(例如，替代金属栅极)和在金属栅极14的外围和下方周围延伸的高k介电材料15(例如，替代高k介电材料)。
CMOS电路可以包括多个这样的FET 10。然而，因为单个CMOS电路的FET 10通常在相同或基本相同的工艺条件下在同一时间或基本同一时间(例如，同时地)制造以提高制造效率，所以每个FET 10典型地具有相同或基本相同的阈值电压(Vt)，并且FET 10的金属栅极14中的每个典型地具有相同或基本相同的有效功函数(eWF)。
当期望多Vt CMOS电路时，如上讨论的，可以根据每个FET的期望的Vt通过使用不同的工艺(诸如，不同的材料、不同的工艺条件等)来单独地制造FET中不同的FET。这样的制造方法基本上会增加制造成本并且降低效率，较早形成的FET会在形成较晚形成的FET期间受到它们所暴露的处理条件的负面影响。
图2示出了根据本发明的示例实施例的场效应晶体管(FET)21。FET 21包括连接到漏极(例如，漏区)160的第一接触件(或通孔)110和连接到源极(例如，源区)170的第二接触件(或通孔)120。第一接触件110和第二接触件120可以包括金属，并且可以延伸穿过介电材料以分别连接到漏极160和源极170。第一接触件110和第二接触件120可以被称作或者可以分别电连接到第一电极160和第二电极170(例如，漏电极和源电极)。FET 21还包括间隔件130，间隔件130在栅极(即，栅极区)周围并且在第一接触件110和第二接触件120与栅极之间延伸。栅极包括金属栅极140(例如，替代金属栅极)和在金属栅极140的周围和下方延伸的高k介电材料150(例如，替代高k介电材料)。
FET 21的间隔件130包括气隙135。例如，FET 21的间隔件130可以具有比FET 10的不具有气隙的间隔件13的密度低的密度(例如，较低的总体密度)。如将在下面进一步描述的，包括气隙135的间隔件130用作气隙Vt变换器(airgap Vt shifter)或AGVS。气隙135由形成间隔件130的诸如氧化物或氮化物(例如，SiO2、Si3N4、SiOCN、SiBCN等)的介电材料的薄层围绕。气隙135减小了间隔件130的寄生电容。
包括气隙135的间隔件130可以通过化学气相沉积(CVD)、等离子体增强化学气相沉积(PE-CVD)、低压化学气相沉积(LP-CVD)、减压化学气相沉积(RP-CVD)或者原子层沉积(ALD)方法或工艺来形成。
虽然形成间隔件130的工艺可以具有例如在μPa至mPa的范围内的中度真空作为工艺条件，但在气隙135内部产生的真空可以比或基本比在形成间隔件130期间的真空条件大。由于纳米尺寸的气隙135，使得气隙135中的真空比或基本比在形成间隔件130期间的整体工艺条件的真空大。因此，即使当间隔件13和130包括诸如Si3N4的相同的材料(或者由所述相同的材料形成)时，包括气隙135的间隔件130的整体介电强度也大于(图1的)不包括气隙135的间隔件13的介电强度。
另外，形成间隔件130的工艺(例如，CVD、PE-CVD、LP-CVD、RP-CVD或ALD工艺)在有或没有等离子体辅助的情况下使用诸如硅烷(SiH4)、一氧化二氮(N2O)、氢气(H2)等各种合适的气体。当金属栅极140暴露于这些气体时，金属栅极140(例如，金属栅极140的WFM堆叠件)的有效功函数(eWF)被调节。例如，用来形成间隔件130的整体工艺步骤调节了在金属栅极140的WFM堆叠件中的氧和氧衍生物，诸如在WFM堆叠件的界面处的氧空位和偶极子。
当在形成间隔件130的工艺期间存在氧化环境时(例如，当在具有氧或臭氧的情况下在近似300℃到近似500℃的范围内的温度下沉积原硅酸四乙酯(TEOS)以形成间隔件130时)，金属栅极140的eWF增大；当在形成间隔件130的工艺期间存在还原环境时(例如，当在具有过度富裕氢的情况下在近似300℃到近似800℃的范围内的温度下沉积氮化硅以形成间隔件130时)，金属栅极140的eWF减小。因此，金属栅极140的eWF可以根据形成包括气隙135的间隔件130的工艺条件而选择性地增大或减小。
图3至图6示出了根据本发明的实施例的制造包括多个场效应晶体管的CMOS电路的方法。
图3是包括两个FET 10和20的CMOS电路1000的简化图，这两个FET 10和20中的每个与以上参照图1描述的FET 10相似。虽然CMOS电路1000被示出为具有两个FET 10和20，但是本发明不限于此。在其它实施例中，CMOS电路1000可以具有形成在基底上的任何合适数量的FET。这里，基底可以具有(100)或(110)的晶体学取向，并且可以是体基底或绝缘体上硅基底。另外，如将在下面讨论的，当多于两个的FET存在于CMOS电路中时，FET可以具有多于两个的不同的电压阈值。此外，FET 10和20可以根据对于本领域技术人员已知的任何合适的方法来制造。例如，FET 10和20可以通过利用替代金属栅极工艺来制造。此外，FET 10和20可以在彼此相同或基本相同的时间制造(例如，可以同时形成或制造)。
参照图4，FET 20中的一个可以被选择为具有修改的Vt，而FET 10中的另一个可以被选择为具有未修改的Vt。然后，对被选择为具有修改的Vt的FET 20进行处理以使间隔件13被蚀刻掉，而不对FET 10中的所述另一个不进行处理。例如，在沉积金属栅极14以形成栅极之后(例如，在金属栅极14被平坦化之后)但在FET 10和20之上沉积密封剂层(例如，见图6中的190)之前，被选择为具有修改的Vt的FET 20的间隔件13可以被选择性地蚀刻掉。
参照图5，于在FET 20中初始地存在间隔件13之处形成包括气隙135的间隔件130，从而成为FET 21(例如，Vt变换后的FET)，并且从而将CMOS电路1000变为多Vt CMOS电路1001。如上所讨论的，包括气隙135的间隔件130可以通过沉积作为一些示例的原硅酸四乙酯(TEOS)或氮化硅(例如，Si3N4)的CVD、PE-CVD、LP-CVD、RP-CVD或ALD工艺来形成。而且，如上所讨论的，形成包括气隙135的间隔件130的方法利用了诸如硅烷(SiH4)气体、原硅酸四乙酯(TEOS)、氧、含氧气体和氢气的某些气体，金属栅极14在形成间隔件130期间暴露于气体。当暴露于诸如硅烷气体、原硅酸四乙酯(TEOS)、氧、含氧气体和氢气的气体时，金属栅极14的WFM堆叠件的eWF根据在形成间隔件130期间的工艺条件而改变，从而成为具有与金属栅极14的eWF不同的eWF的金属栅极140。
通过利用形成间隔件130时的氧化环境，金属栅极140的WFM堆叠件的eWF增大。在这样的情况下，未经处理的FET 10(例如，不包括气隙的FET 10)可以被视为具有低Vt(nLVT)的nFET，而由于FET 21的Vt大于FET 10的Vt，所以经处理的FET 21(例如，包括气隙135的FET 21)可以被视为具有常规Vt(nRVT)的nFET。另一方面，未经处理的FET 10(例如，不包括气隙的FET 10)可以被视为具有较高常规Vt(pRVT)的pFET，而由于FET 21的Vt小于FET 10的Vt，所以经处理的FET 21(例如，包括气隙135的FET 21)可以被视为具有较低Vt(pLVT)的pFET。
通过利用形成间隔件130时的还原环境，金属栅极140的WFM堆叠件的eWF减小。在这样的情况下，未经处理的FET 10可以被视为具有常规Vt(nRVT)的nFET，而由于FET 21的Vt低于FET 10的Vt，所以经处理的FET 21可以被视为具有低Vt(nLVT)的nFET。另一方面，未经处理的FET 10(例如，不包括气隙的FET 10)可以被视为具有较低常规Vt(pLVT)的pFET，而由于FET 21的Vt大于FET 10的Vt，所以经处理的FET 21(例如，包括气隙135的FET 21)可以被视为具有较高Vt(pRVT)的pFET。
参照图6，在形成包括气隙135的间隔件130之后，在所有FET 10和21之上形成密封剂层190(例如，连续的密封剂层)以保护FET 10和21免受外部环境影响。可以通过使用相对低温工艺来形成密封剂层190。此外，在形成间隔件130之后的用于形成多Vt CMOS电路1001的所有工艺可以是相对低温工艺，从而确保使任何随后的氧再分布减少或最小化，以确保由气隙间隔件形成工艺步骤获得的Vt变换是稳定的。
因此，多Vt CMOS电路1001包括具有彼此不同的阈值电压Vt的多个FET 10和20。
虽然已经参照示例实施例描述了本发明，但是本领域技术人员将认识到的是，在全都不脱离本发明的精神和范围的情况下，可以执行对描述的实施例的各种改变和修改。此外，各个领域的技术人员将认识到的是，在这里描述的本发明提出了对其它任务的解决方案和适用于其它应用的解决方案。申请人的意图是，在全都不脱离本发明的精神和范围的情况下，通过这里的权利要求来覆盖本发明的所有这些用途以及可对出于公开的目的而在此选择的本发明的示例实施例做出的改变和修改。因此，本发明的示例实施例应当在所有方面被认为是说明性的而不是限制性的，并使本发明的精神和范围由所附权利要求及其等同物来表示。

Claims (22)

1.一种互补金属氧化物半导体电路，包括基底以及位于基底上的第一场效应晶体管和第二场效应晶体管，每个场效应晶体管包括：
多个接触件；
源极，连接到所述多个接触件中的一个接触件；
漏极，连接到所述多个接触件中的另一个接触件；
栅极；以及
间隔件，位于所述栅极和所述接触件之间，
其中，第一场效应晶体管的间隔件具有比第二场效应晶体管的间隔件的气隙大的气隙。
2.根据权利要求1所述的互补金属氧化物半导体电路，其中，第一场效应晶体管的间隔件具有比第二场效应晶体管的间隔件的整体密度小的整体密度。
3.根据权利要求1所述的互补金属氧化物半导体电路，其中，每个场效应晶体管的栅极包括金属栅极以及形成在金属栅极的底部处和外围周围的高k介电材料，每个金属栅极包括相同的材料，
其中，第一场效应晶体管的金属栅极的有效功函数不同于第二场效应晶体管的金属栅极的有效功函数。
4.根据权利要求1所述的互补金属氧化物半导体电路，其中，第二场效应晶体管的间隔件不具有气隙。
5.根据权利要求4所述的互补金属氧化物半导体电路，其中，每个场效应晶体管的栅极包括相同的功函数金属。
6.一种制造互补金属氧化物半导体电路的方法，所述方法包括以下步骤：
在基底上形成多个场效应晶体管；
选择性地蚀刻所述多个场效应晶体管中的一个场效应晶体管的间隔件；以及
在所述多个场效应晶体管中的所述一个场效应晶体管中形成另一间隔件，所述另一间隔件包括气隙。
7.根据权利要求6所述的方法，所述方法还包括在所有的场效应晶体管上形成连续的密封剂层。
8.根据权利要求6所述的方法，其中，形成所述多个场效应晶体管的步骤包括替代金属栅极工艺。
9.根据权利要求6所述的方法，其中，形成所述另一间隔件的步骤包括化学气相沉积工艺、等离子体增强化学气相沉积工艺、低压化学气相沉积工艺、减压化学气相沉积工艺和原子层沉积工艺中的至少一种。
10.根据权利要求9所述的方法，其中，形成所述另一间隔件的步骤还包括在氧、臭氧和/或氧化环境下沉积原硅酸四乙酯。
11.根据权利要求9所述的方法，其中，形成所述另一间隔件的步骤还包括在氢或还原环境下沉积氮化硅、碳氮氧化硅或碳氮化硅硼。
12.一种制造互补金属氧化物半导体电路的方法，所述方法包括以下步骤：
在基底上形成多个场效应晶体管，每个场效应晶体管包括多个接触件、连接到所述多个接触件中的一个接触件的源极、连接到所述多个接触件中的另一个接触件的漏极、栅极以及位于所述栅极与所述接触件之间的间隔件；
仅对来自所述多个场效应晶体管中的一些场效应晶体管的间隔件进行蚀刻；以及
在间隔件被蚀刻的场效应晶体管中形成另一间隔件，所述另一间隔件包括气隙。
13.根据权利要求12所述的方法，其中，在对所述间隔件的蚀刻的步骤之后并且在形成所述另一间隔件的步骤之前，所述多个场效应晶体管中的第一组包括所述间隔件，所述多个场效应晶体管中的第二组在栅极和接触件之间具有未被占有的空隙。
14.根据权利要求13所述的方法，其中，在形成所述另一间隔件的步骤之后，所述多个场效应晶体管中的所述第二组具有与所述多个场效应晶体管中的所述第一组的阈值电压不同的阈值电压。
15.根据权利要求12所述的方法，其中，形成所述多个场效应晶体管的步骤包括使栅极平坦化。
16.根据权利要求15所述的方法，其中，对所述间隔件进行蚀刻的步骤直接发生在所述使栅极平坦化的步骤之后。
17.根据权利要求12所述的方法，其中，形成所述另一间隔件的步骤包括化学气相沉积工艺、等离子体增强化学气相沉积工艺、低压化学气相沉积工艺、减压化学气相沉积工艺或原子层沉积工艺。
18.根据权利要求17所述的方法，其中，形成所述另一间隔件的步骤还包括在氧和/或臭氧环境下沉积原硅酸四乙酯。
19.根据权利要求17所述的方法，其中，形成所述另一间隔件的步骤还包括在氢或还原环境下沉积氮化硅、碳氮氧化硅或碳氮化硅硼。
20.根据权利要求12所述的方法，其中，形成所述多个场效应晶体管的步骤包括替代金属栅极工艺。
21.根据权利要求12所述的方法，其中，基底具有(100)或(110)的晶体学取向。
22.根据权利要求12所述的方法，其中，基底是体基底或绝缘体上硅基底。
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