CN107851646A - 配线基板及其制造方法 - Google Patents

配线基板及其制造方法 Download PDF

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Publication number
CN107851646A
CN107851646A CN201680040449.8A CN201680040449A CN107851646A CN 107851646 A CN107851646 A CN 107851646A CN 201680040449 A CN201680040449 A CN 201680040449A CN 107851646 A CN107851646 A CN 107851646A
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CN
China
Prior art keywords
wiring substrate
base material
resin bed
opening portion
light transmissive
Prior art date
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Pending
Application number
CN201680040449.8A
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English (en)
Inventor
土田彻勇起
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Toppan Inc
Original Assignee
Toppan Printing Co Ltd
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Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Publication of CN107851646A publication Critical patent/CN107851646A/zh
Pending legal-status Critical Current

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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
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Abstract

本发明的目的在于提供一种在形成光透过部时能够抑制基材中裂纹的产生、并且同时具有高的光透过率且可形成微细配线的配线基板及其制造方法。该配线基板包括：具有光透过性的基材；在基材的至少一侧层叠金属层和树脂层而成的层叠体；以及设置在层叠体的一部分中的作为开口的光透过部，该配线基板的特征在于：限定光透过部的侧面的至少一部分由树脂层构成，在基材的表面附近，金属层的一部分被设置为与构成限定光透过部的侧面的至少一部分的树脂层邻接且包围该树脂层。

Description

配线基板及其制造方法
技术领域
本发明涉及配线基板及其制造方法。
背景技术
近年来，使用半导体芯片以及外部连接部件的半导体装置被用于电子仪器以及汽车等各种各样的领域中。另外，在电子设备变得高功能化、小型化及轻量化的过程中，需要半导体封装的小型化、更多的引脚数以及外部端子的微细间距化，对高密度配线基板的要求日益提高。以往的芯材料使用了以玻璃环氧树脂为代表的有机材料，但是在芯上形成的配线的微细化是有限度的。此外，例如在连接传感器装置时，需要使用具有保护传感器及高的光透过性这样的功能的芯材。在这种情况下，能够进行配线的微细化、并且以具有高透明性和高折射率的玻璃为基材的配线基板的开发受到了关注，并且被期待应用到光学装置。
现有技术文献
专利文献
专利文献1：日本特开2005-5488号公报
在使用用于以往的半导体封装基板用途的非感光性的层间绝缘树脂的情况下，难以制造具有光透过部的配线基板，另外，在配线基板的基材是玻璃的情况下，在为了形成光透过部而采用激光将形成在玻璃上的树脂分解除去时，会有由于激光引起的热而使玻璃产生裂纹等问题。
另外，在通过激光将玻璃上的树脂除去的情况下，若为了洗净芯上的树脂残留物而将玻璃浸渍于高锰酸钾溶液中，则由于玻璃的一部分溶解而起雾，因而会有折射率降低、光透过率降低的问题。
此外，在专利文献1所公开的多层配线基板中，由于隔着绝缘层而设置配线层，因而配线的微细化是有限度的。另外，由于使用了聚酰亚胺作为绝缘层，因而在使用玻璃作为基材的情况下，聚酰亚胺和玻璃之间的密合性会有问题。
发明内容
发明所要解决的课题
本发明的目的在于提供一种能够在形成光透过部时抑制基材中裂纹的产生、并且同时具有高的光透过率且可形成微细配线的配线基板及其制造方法。
用于解决课题的方案
本发明为一种配线基板，包括：具有光透过性的基材；在基材的至少一侧层叠金属层和树脂层而成的层叠体；以及设置在层叠体的一部分中的作为开口的光透过部，所述配线基板的特征在于：限定光透过部的侧面的至少一部分由树脂层构成，在基材表面附近，金属层的一部分被设置为与构成限定光透过部的侧面的至少一部分的树脂层邻接且包围该树脂层。
另外，本发明为一种配线基板，包括：具有光透过性的基材；在基材的至少一侧层叠金属层和树脂层而成的层叠体；以及设置在层叠体的一部分中的作为开口的光透过部，所述配线基板的特征在于：在基材表面附近，金属层的一部分被设置为包围光透过部。
此外，本发明为一种具有光透过部的配线基板的制造方法，包括：以覆盖具有光透过性的基材上的光透过部形成区域及其周围的方式形成金属层的步骤；以覆盖所形成的金属层的方式形成树脂层的步骤；选择性地除去光透过部形成区域上的树脂层的一部分而形成开口部的步骤；以及除去从开口部露出的金属层的步骤。
本发明的效果
根据本发明的配线基板及其制造方法，可以实现在形成光透过部时抑制基材中裂纹的产生、并且同时具有高的光透过率且可形成微细配线的配线基板及其制造方法。
附图简要说明
[图1]图1为使用本实施方式的配线基板而制造的半导体装置的说明图。
[图2]图2为本实施方式的配线基板的说明图。
[图3]图3为根据本实施方式的另一配线基板的说明图。
[图4]图4为从(a)到(o)来说明根据本实施方式的配线基板的制造步骤的图。
[图5]图5为从(a)到(h)来说明根据本实施方式的另一配线基板的制造步骤的图。
具体实施方式
以下，参照附图，对本发明的优选实施方式进行详细说明。需要说明的是，在以下的说明中，将相同的符号用于相同要素或具有相同功能的要素，并省略重复的说明。另外，以下，在本说明书中，将以在基材的一侧形成2层树脂层的情况为例来进行说明。
图1为使用本实施方式的配线基板而制造的半导体装置的说明图。如图1所示，半导体装置1包括：层叠体101、层叠体201、光透过部60、基材30、接合端子80、外部连接端子90、部件70以及密封树脂100。需要说明的是，将在后述说明层叠体101、层叠体102及光透过部60的详细情况。
部件70(例如)是具有形成于半导体基板表面上的晶体管或二极管等的集成电路(IC或LSI)，并具有大致长方体的形状。半导体基板使用(例如)硅基板(Si基板)、氮化镓基板(GaN基板)或碳化硅基板(SiC基板)等以无机物为主成分的基板。在本实施方式中，使用硅基板作为半导体基板。使用硅基板形成的部件70的线膨胀系数(CTE：Coefficient ofThermal Expansion)约为2至4ppm/K(例如3ppm/K)。本实施方式中的线膨胀系数是指(例如)在20℃以上260℃以下的温度范围内对应于温度上升而变化的长度。另外，部件70也可以是(例如)CMOS传感器或CCD传感器等固体成像元件。
基材30由(例如)具有使光透过的性质(透明性)的材料构成。基材30的厚度为(例如)0.05mm以上1mm以下。基材30的主表面30a为(例如)大致矩形状、大致圆形状或者大致椭圆形状等。透过基材30的光的波长范围可以为(例如)100nm以上20000nm以下，也可以为300nm以上1100nm以下。基材30使用(例如)玻璃。在使用玻璃的情况下，玻璃中的成分种类、成分比率及其制造方法均没有限制。例如，作为玻璃，可以列举出无碱玻璃、碱性玻璃、硼硅酸玻璃、石英玻璃、蓝宝石玻璃、感光玻璃等，但也可以使用任意的玻璃。另外，作为制造方法，可以列举出浮法、下拉法、熔融法、上拉法、辊出法等，但也可以使用通过任意方法所制作的玻璃。玻璃的线膨胀系数优选为与上述部件70的线膨胀系数接近的值，例如为-1ppm/K以上10.0ppm/K以下、或者0.5ppm/K以上5.0ppm/K以下。基于JIS B 0601：2013的基材30的主表面30a的最大高度粗糙度Rz可以为(例如)0.01μm以上5μm以下，也可以为0.1μm以上3μm以下。通过使基材30的主表面30a的最大高度粗糙度Rz为0.01μm以上，可以抑制制备基材30的成本增加。通过使基材30的主表面30a的最大高度粗糙度Rz为5μm以下，能够抑制由主表面30a的凹凸所引起的导体层的断线及短路等，并且同时能够实现配线微细化所带来的高密度封装。
接合端子80和外部连接端子90都设置在层叠体201上，接合端子80与部件70电连接。接合端子80和外部连接端子90通过(例如)Sn、Sn-Pb、Sn-Ag、Sn-Cu、Sn-Ag-Cu或Sn-Bi等的焊料而形成。在接合端子80和外部连接端子90由焊料构成的情况下，在形成接合端子80和外部连接端子90之前，可以对金属层在层叠体201的主表面201a露出的部分进行(例如)Ni镀覆、Au镀覆、Sn镀覆或预钎焊处理，也可以进行OSP(Organic SolderabilityPreservative，有机可焊性保护层)等有机覆膜处理。
图2及图3分别是本实施方式的配线基板的说明图。如图2及图3所示，根据本实施方式的配线基板11及根据本实施方式的另一配线基板12分别包括：基材30、层叠体101、层叠体201、光透过部60、接合端子80、外部连接端子90以及金属层500。层叠体101包括：籽晶层102、金属层103、金属层202的一部分、籽晶层106的一部分、通孔104的一部分、以及树脂层105。层叠体201包括：金属层202的一部分、籽晶层106的一部分、通孔104的一部分、树脂层203、以及表面处理层204。需要说明的是，可以在基材30中形成通孔，另外可以在该通孔内形成金属。此外，通过增加由树脂层及金属层等构成的层叠体，从而可以增加层叠数。另外，在层叠体101与基材30之间可以具有用于提高密合的处理层。
表面处理层204由(例如)厚度为0.001μm以上3μm以下的单层或复合层形成。例如，在单层中可以使用Au、Pd、Sn、Cu、Ni，在复合层中可以使用Au/Ni、Au/Pd、Au/Pd/Ni。在此，金属层的形成方法有以湿法处理为代表的镀覆法和以真空工艺为代表的溅射法，但从节拍时间方面来看，优选使用镀覆法，并且可以使用无电解镀覆和电解镀覆中的任一方法。在表面处理层204是无电解Ni镀膜的情况下，Ni镀膜中可以包含磷或硼等无机物，另外在Pd覆膜中，还可以含有上述无机物之外的W等，可以形成(例如)Au/无电解Pd-P/无电解Ni-P覆膜等。另外，也可以对表面处理层204施加OSP等有机覆膜。
籽晶层102和籽晶层106可以单独或组合地使用(例如)Cu、Al、Ti、Cr、Mo、W、Ta、Au、Ir、Ru、Pd、Pt、AlSi、AlSiCu、AlCu、NiFe、ITO、IZO、AZO、ZnO、PZT、TiN、Cu3N4等，其厚度为(例如)0.0001μm以上10μm以下。
金属层103及金属层202是由(例如)Au、Cu、Ni等金属构成的导电层，并设置在树脂层105内及树脂层203内。金属层202经由层叠体101中的通孔104而与籽晶层102及金属层103电连接。金属层103和金属层202的厚度为(例如)1μm以上20μm以下。需要说明的是，金属层202的一部分中可以使用作为金属和有机物的复合材料的金属膏。
金属层500由籽晶层102的一部分及金属层103的一部分形成，该金属层500为在形成光透过部60时未被蚀刻去除而残留的部分。金属层500的厚度为(例如)1.0001μm以上30μm以下。
树脂层105及树脂层203包含(例如)环氧树脂、聚酰亚胺、马来酰亚胺树脂、聚对苯二甲酸乙二醇酯、聚苯醚、液晶聚合物、抗反射层、红外截止层或有机硅等树脂材料、以及它们的复合材料。配线基板11及配线基板12的树脂层105可以使用感光性材料和非感光性材料中的任一者。配线基板11的树脂层203使用感光性材料。配线基板12的树脂层203可以使用感光性材料和非感光性材料中的任一者。树脂层105的厚度为(例如)5μm以上50μm以下。树脂层203的厚度为(例如)5μm以上50μm以下。
树脂层203的开口部205和开口部206可以具有相同的形状和尺寸，另外，开口部205可以比开口部206大，开口部205也可以比开口部206小。
需要说明的是，如图3所示，在配线基板12中，表面处理层204形成在金属层500的光透过部侧。
(配线基板11的制造方法)
参照图4(a)至(o)，对根据本实施方式的配线基板11的制造方法进行说明。
首先，如图4(a)所示，将籽晶层102施加到基材30的一侧。籽晶层102通过(例如)公知的溅射法、CVD法或无电解镀覆法形成。例如，由Cu层、镀覆有Ni的Cu层、镀覆有Au的Cu层、进行了钎焊镀覆的Cu层、Al层、或Ag/Pd合金层等形成。在本实施方式中，从成本、电特性及制造容易程度的观点出发，使用Cu层。
接着，如图4(b)所示，在籽晶层102上形成树脂层300。树脂层300通过(例如)印刷法、真空压制法、真空层压法、辊层压法、旋涂法、模涂法、幕涂法、辊涂法等公知的方法形成。对树脂层300进行激光照射或光刻法，除去树脂层的一部分，从而形成了开口部300a和300b。在此，开口部300a是成为光透过部的部位。在本实施方式中，从成本、电特性及制造容易程度的观点出发，使用可以通过光刻法形成的感光性树脂。
然后，如图4(c)所示，在开口部300a和300b内形成金属层103。金属层103通过印刷法、无电解镀覆法、电解镀覆法形成，但在本实施方式中，从成本、电特性及制造容易程度的观点出发，使用电解镀覆法，并且金属层103使用Cu层。
接着，如图4(d)所示，除去树脂层300，然后除去没有形成金属层103的位置处的籽晶层102a，从而得到如图4(e)所示的金属层103a、103b和103c。籽晶层102a通过(例如)湿式蚀刻或干式蚀刻来除去。也就是说，本实施方式中的配线图案是通过半加成法形成的。半加成法是指这样的方法：其中，形成Cu层等籽晶层，在籽晶层上形成具有所需图案的抗蚀剂，通过电解镀覆法等使籽晶层中的露出部分的厚度增大，在除去抗蚀剂之后，对薄的籽晶层进行蚀刻，从而得到配线图案。
然后，如图4(f)所示，形成树脂层105以覆盖基材30和金属层103a、103b、103c。树脂层105通过(例如)印刷法、真空压制法、真空层压法、辊层压法、旋涂法、模涂法、幕涂法、辊涂法等公知的方法形成。在本实施方式中，从制造容易程度的观点出发，使用真空层压法、真空压制法。
接着，如图4(g)所示，在金属层103a上的树脂层105中设置开口部105a，并且同时在金属层103b、103c上的树脂层105中设置开口部105b。在树脂层105为感光性的情况下，开口部105a及开口部105b采用光刻法或激光来形成，在树脂层105为非感光性的情况下，开口部105a及开口部105b通过激光来形成。在此，开口部105a的直径需要小于金属层103a的直径由此，如后所述，可以抑制对基材30的损伤，并且可以避免在使用玻璃作为基材30时的裂纹的产生。此外，金属层103a具有释放激光热量的效果，因而在基材30为玻璃并且不具有金属层103a的情况下，会有产生裂纹的可能性。
然后，如图4(h)所示，设置树脂层400以保护开口部105b，并且同时形成开口部400a。开口部105a和开口部400a的尺寸的大小没有限制。在树脂层400为感光性的情况下，开口部400a采用光刻法或激光来形成，在树脂层400为非感光性的情况下，开口部400a通过激光来形成。在本实施方式中，从成本、电特性及制造容易程度的观点出发，使用可以通过光刻法形成的感光性树脂。
接着，如图4(i)所示，通过除去开口部400a内的金属层103a及籽晶层102，从而形成光透过部60。金属层103a及籽晶层102的除去通过湿式蚀刻或干式蚀刻来进行，但从成本及制造容易程度的观点出发，采用湿式蚀刻。此时，通过蚀刻后残留的金属层103a及籽晶层102，在光透过部60的外周形成了金属层500。然后，如图4(j)所示，将树脂层400剥离。树脂层(例如)在碱性溶液中进行剥离和去除。
然后，如图4(k)所示，施加籽晶层106。籽晶层106通过(例如)公知的溅射法、CVD法或无电解镀覆法形成。例如，由Cu层、镀覆有Ni的Cu层、镀覆有Au的Cu层、进行了钎焊镀覆的Cu层、Al层、或Ag/Pd合金层等形成。在本实施方式中，从成本、电特性及制造容易程度的观点出发，使用Cu层。接着，通过与上述树脂层400的加工相同的处理，在籽晶层106上形成树脂层107，并设置开口部107a和开口部107b。
接着，如图4(l)所示，在开口部107a和开口部107b内形成金属层202。然后，在(例如)碱性溶液中剥离除去树脂层107之后，通过蚀刻除去不要的籽晶层106，从而得到图4(m)所示的配线基板。
然后，如图4(n)所示，在形成树脂层203之后，设置开口部203a、开口部203b和开口部203c。树脂层203使用感光性树脂，开口部203a、开口部203b和开口部203c采用光刻法来形成。构成开口部203c的内壁的树脂层203与金属层500的内周接触。另外，在开口部203a及开口部203b内的金属层202上设置表面处理层204，如图4(o)所示，分别设置接合端子80及外部连接端子90。由此，可以得到根据本实施方式的配线基板11。
(配线基板12的制造方法)
使用图5(a)至(h)来说明根据本实施方式的另一配线基板12的制造方法。需要说明的是，由于配线基板12的制造步骤具有与上述配线基板11的制造方法中的图4(a)至(l)的步骤相同的步骤，因而在此省略。
如图4(l)所示，在开口部107a和开口部107b内形成金属层202，然后，如5(a)所示，在(例如)碱性溶液中剥离除去树脂层107。
接着，如图5(b)所示，在开口部400a中形成树脂层108。然后，如图5(c)所示，通过蚀刻将形成有金属层202及树脂层108的位置以外的籽晶层106溶解并除去。
然后，如图5(d)所示，在碱性溶液中剥离树脂层108。接着，如图5(e)所示，在形成树脂层203之后，设置开口部203a、开口部203b和开口部203d。在树脂层203为感光性的情况下，采用光刻法或激光来形成开口部203a、开口部203b和开口部203d，在树脂层203为非感光性的情况下，通过激光来形成开口部203a、开口部203b和开口部203d。
接着，如图5(f)所示，通过蚀刻除去开口部203d内的籽晶层106，并设置开口部203e。然后，如图5(g)所示，在开口部203a及开口部203b内的金属层202上以及在金属层500的光透过部侧设置表面处理层204。接着，如图5(h)所示，分别设置接合端子80及外部连接端子90。由此，可以得到根据本实施方式的配线基板12。
根据本实施方式的配线基板及其制造方法，在光透过部60的形成中，通过光刻法或激光照射而在金属层103a上的树脂层105中设置开口部400a，然后，通过刻蚀将开口部400a内的金属层103a除去，因而在基材30上直接形成的树脂或金属层并没有通过激光的照射而除去，其结果是，可以抑制在形成光透过部60时基材30中的损伤。另外，在基材30使用玻璃的情况下，可以避免基材30中的裂纹的产生。此外，不需要洗净在形成光透过部60时由激光照射而生成的树脂残渣，其结果是，也不需要浸渍于高锰酸钾溶液中，因而玻璃的一部分不会溶解而起雾。另外，通过在基材上直接形成金属层，从而可以形成微细配线。因此，可以得到具有高的光透过率、并可形成微细配线的配线基板。
另外，通过使基材的线膨胀系数为-1ppm/K以上10ppm/K以下，从而使部件的线膨胀系数与基材的线膨胀系数成为相互接近的数值，因此，可以抑制在将部件搭载于配线基板时发生的位置错位。此外，通过使基材为玻璃，从而使得价格低廉、且可以提高强度，并且同时大型化也变得容易。另外，可以容易地调整基材的表面粗糙度。
此外，由于配线基板的金属层与部件经由包含焊料的连接端子而相互连接，因而即使在配线基板侧的金属层与部件之间产生位置错位的情况下，通过包含焊料的连接端子也可以将错位包埋，从而可以抑制在部件与配线基板的层叠体之间产生的连接不良。需要说明的是，配线基板的连接端子可以含有金。在这种情况下，连接端子的导电性提高，并且同时该连接端子的腐蚀也得到了抑制。另外，层叠体作为用于与半导体芯片连接的外部连接部件而发挥作用，从而可以分别制造半导体芯片和具有外部连接部件的配线基板，因此，半导体装置的制造效率得到了改善。
实施例
通过以下的实施例来更详细地说明本发明，但本发明不限于这些实施例。
(关于配线基板11的实施例1)
在关于配线基板11的实施例1中，首先，如图4(a)至(o)所示，在基材30的主表面30a上形成了籽晶层102。作为基材30，使用玻璃(OA-10G(日本電気硝子株式会社制)，厚度为0.5mm)。基材30的线膨胀系数约为4ppm/K。籽晶层102使用了铜溅射覆膜。接着，使用感光性干膜抗蚀剂(25μm)作为树脂层300并将其图案化，使得开口部300a和开口部300b的直径分别为和然后在开口部300a和开口部300b内通过电解铜镀覆以厚度10μm的方式设置金属层103。在剥离树脂层300之后，除去不要的籽晶层102a，得到了由电解铜镀层和铜溅射覆膜构成的金属层103a、103b和103c(厚度约为10μm)。然后，通过真空层压法形成厚度为20μm的“味の素ファインテクノ”制的GX-T31作为树脂层105，并通过UV-YAG激光以直径分别为和的方式设置了开口部105a和开口部105b。接着，设置感光性干膜抗蚀剂(25μm)作为树脂层400，通过光刻法设置的开口部400a。在硫酸和过氧化氢水溶液的混合液中将金属层103a溶解并除去，并通过剥离树脂层400，从而得到了图4(j)所示的基板。
然后，层叠Ti(100nm)和Cu(500nm)作为籽晶层106，设置感光性干膜抗蚀剂(25μm)作为树脂层107，并通过光刻法以直径分别为和的方式设置了开口部107a和开口部107b。通过电解铜镀覆在籽晶层106上设置厚度为10μm的金属层202，从而得到了图4(l)所示的基板。将树脂层107剥离之后，使用硫酸和过氧化氢水溶液的混合液除去铜层，采用钛蚀刻液除去钛层。接着，设置厚度为20μm的感光性阻焊层(solder resistlayer)作为树脂层203，并设置开口部203a、开口部203b及开口部203c。然后，进行无电解Ni/Au镀覆处理，使得开口部203a和开口部203b的表面处理层204的厚度分别为3μm和0.05μm。最后，将由和的Sn-3wt％Ag-0.5wt％Cu构成的焊料球在峰温度260℃下分别安装在开口部203a和开口部203b内的表面处理层204上，从而得到了外部连接端子90和接合端子80。由此，得到了图2所示的具有光透过部的配线基板11。
对于根据上述实施例1的配线基板11，已经确认，可以在基材30的主表面30a上形成线/间距(Line/Space)＝2/2μm的配线图案。
另外，为了评价根据上述实施例1的配线基板11的光学特性，通过与形成根据实施例1的光透过部60的步骤相同的步骤，形成了的评价用开口部。
在分光测定上述评价用开口部时发现，在5％以内的范围内，在光透过率和雾度方面与基材30是一致的。在实施例1中，由于在形成光透过部60时没有通过激光将在玻璃上直接形成的树脂除去，因而不需要浸渍于高锰酸钾溶液中以将玻璃上的树脂残渣洗净。因此，不会由于玻璃的一部分溶解并起雾而使折射率和光透过率降低。
(关于配线基板12的实施例2)
在关于配线基板12的实施例2中，首先，通过与上述实施例1的制造方法相同的制造方法，得到了图4(l)所示的基板。接着，在将树脂层107剥离之后，在开口部400a中形成感光性干膜抗蚀剂作为树脂层108。然后，对于由Cu层和Ti层构成的籽晶层106，使用硫酸和过氧化氢水溶液的混合液除去Cu层，使用钛蚀刻液除去Ti层。接着，在采用碱性液将树脂层108剥离之后，设置厚度为20μm的感光性阻焊层作为树脂层203，并设置开口部203a、开口部203b及开口部203d。然后，对于开口部203d内的由Cu层和Ti层构成的籽晶层106，使用硫酸和过氧化氢水溶液的混合液除去Cu层，使用钛蚀刻液除去Ti层，得到了开口部203e。接着，作为表面处理层204，通过OSP处理将有机覆膜施加到开口部203a上、开口部203b上以及金属层500的光透过部侧。最后，将由和的Sn-3wt％Ag-0.5wt％Cu构成的焊料球在峰温度260℃下分别安装在开口部203a和开口部203b内的表面处理层204上，从而得到了外部连接端子90和接合端子80。由此，得到了图3所示的具有光透过部的配线基板12。
对于根据上述实施例2的配线基板12，已经确认，可以在基材30的主表面30a上形成线/间距(Line/Space)＝2/2μm的配线图案。
另外，为了评价根据上述实施例2的配线基板12的光学特性，通过与形成根据实施例2的光透过部60的步骤相同的步骤，形成了的评价用开口部。
在分光测定上述评价用开口部时发现，在5％以内的范围内，在光透过率和雾度方面与基材30是一致的。同样在实施例2中，由于在形成光透过部60时没有通过激光将在玻璃上直接形成的树脂除去，因而不需要浸渍于高锰酸钾溶液中以将玻璃上的树脂残渣洗净。因此，不会由于玻璃的一部分溶解并起雾而使折射率和光透过率降低。
(半导体装置)
接着，将部件70搭载于所得的配线基板11及配线基板12上。部件70具有在Cu柱的末端形成有Sn-3.5Ag焊料层而得的突起电极。另外，部件70的线膨胀系数约为3ppm/K。在将部件70的突起电极与配线基板11及配线基板12的接合端子80进行位置对齐之后，将部件70压接到配线基板11及配线基板12，再进行加热。随后，使用密封树脂100将接合端子80的外周密封。由此，得到了图1所示的半导体装置1。
工业实用性
根据本发明的配线基板及其制造方法，可以用于适用于光学装置的以玻璃为芯的配线基板。
符号的说明
1···半导体装置
11、12···配线基板
30、30a···芯
60···光透过部
70···部件
80···接合端子
90···外部连接端子
101···层叠体
102···籽晶层
103、103a、103b、103c···金属层
104···通孔
105···树脂层
105a、105b···开口部
106···籽晶层
107···树脂层
108···树脂层
201、201a···层叠体
202···金属层
203···树脂层
203a、203b、203c、203d、203e···开口部
204···表面处理层
300···树脂层
300a、300b···开口部
400···树脂层
400a···开口部
500···金属层

Claims (5)

1.一种配线基板，包括：
具有光透过性的基材；
在所述基材的至少一侧层叠金属层和树脂层而成的层叠体；以及
设置在所述层叠体的一部分中的作为开口的光透过部，
所述配线基板的特征在于：
限定所述光透过部的侧面的至少一部分由所述树脂层构成，
在所述基材的表面附近，所述金属层的一部分被设置为与构成限定所述光透过部的所述侧面的至少一部分的树脂层邻接且包围该树脂层。
2.一种配线基板，包括：
具有光透过性的基材；
在所述基材的至少一侧层叠金属层和树脂层而成的层叠体；以及
设置在所述层叠体的一部分中的作为开口的光透过部，
所述配线基板的特征在于：
在所述基材的表面附近，所述金属层的一部分被设置为包围所述光透过部。
3.根据权利要求1或2所述的配线基板，其特征在于：所述基材的线膨胀系数为-1ppm/K以上10ppm/K以下。
4.根据权利要求1或2所述的配线基板，其特征在于：所述基材为玻璃。
5.一种配线基板的制造方法，所述配线基板具有光透过部，所述方法包括：
以覆盖具有光透过性的基材上的所述光透过部的形成区域及其周围的方式形成金属层的步骤；
以覆盖所形成的所述金属层的方式形成树脂层的步骤；
选择性地除去所述光透过部的形成区域上的所述树脂层的一部分而形成开口部的步骤；以及
除去从所述开口部露出的所述金属层的步骤。
CN201680040449.8A 2015-07-10 2016-07-06 配线基板及其制造方法 Pending CN107851646A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004309532A (ja) * 2003-04-02 2004-11-04 Andes Intekku:Kk 外面拡散半透過型反射板および外面拡散半透過型カラー液晶表示装置
JP2005158948A (ja) * 2003-11-25 2005-06-16 Fuji Photo Film Co Ltd 固体撮像装置及びその製造方法
CN101010807A (zh) * 2004-09-02 2007-08-01 阿帕托佩克股份有限公司 制造晶片级摄像头模块的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3756041B2 (ja) * 1999-05-27 2006-03-15 Ｈｏｙａ株式会社 多層プリント配線板の製造方法
US6864116B1 (en) * 2003-10-01 2005-03-08 Optopac, Inc. Electronic package of photo-sensing semiconductor devices, and the fabrication and assembly thereof
US20060043513A1 (en) * 2004-09-02 2006-03-02 Deok-Hoon Kim Method of making camera module in wafer level
KR100769722B1 (ko) * 2006-10-10 2007-10-24 삼성전기주식회사 이미지센서의 웨이퍼 레벨 칩 스케일 패키지 및 그제조방법
KR20100032857A (ko) * 2007-07-19 2010-03-26 가부시키가이샤후지쿠라 반도체 패키지와 그 제조 방법
JP2010165939A (ja) * 2009-01-16 2010-07-29 Sharp Corp 固体撮像装置及びその製造方法
JP5531778B2 (ja) * 2010-05-24 2014-06-25 パナソニック株式会社 タッチパネル
JP5768396B2 (ja) * 2011-02-15 2015-08-26 ソニー株式会社 固体撮像装置、および、その製造方法、電子機器
US9472479B2 (en) * 2014-01-31 2016-10-18 Corning Incorporated Methods and apparatus for providing an interposer for interconnecting semiconductor chips

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004309532A (ja) * 2003-04-02 2004-11-04 Andes Intekku:Kk 外面拡散半透過型反射板および外面拡散半透過型カラー液晶表示装置
JP2005158948A (ja) * 2003-11-25 2005-06-16 Fuji Photo Film Co Ltd 固体撮像装置及びその製造方法
CN101010807A (zh) * 2004-09-02 2007-08-01 阿帕托佩克股份有限公司 制造晶片级摄像头模块的方法

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