CN107634056A - 半导体装置及其形成方法 - Google Patents

半导体装置及其形成方法 Download PDF

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CN107634056A
CN107634056A CN201610531514.9A CN201610531514A CN107634056A CN 107634056 A CN107634056 A CN 107634056A CN 201610531514 A CN201610531514 A CN 201610531514A CN 107634056 A CN107634056 A CN 107634056A
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semiconductor device
dopant well
grid structure
device described
doped region
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CN107634056B (zh
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李志成
黄昱豪
李凯霖
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United Microelectronics Corp
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Abstract

本发明公开一种半导体装置以及形成半导体装置的形成方法，该半导体装置包含第一及第二掺杂阱、源极区、漏极区、二栅极结构以及掺杂区。第一掺杂阱，是设置在一基底内且具有第一导电型式，而源极区则是设置在第一掺杂阱内。第二掺杂阱是设置在该基底内且邻接第一掺杂阱，第二掺杂阱具有第二导电型式，而漏极区则是设置在第二掺杂阱内。二栅极结构是设置在该基底上并位于源极区与漏极区之间。掺杂区具有第一导电型式，并且其是设置在第二掺杂阱内并位于二栅极结构之间。

Description

半导体装置及其形成方法
技术领域
本发明涉及一种具有金属氧化物半导体(metal-oxide semiconductor,MOS)晶体管的半导体装置及其形成方法，尤其是涉及一种具有横向扩散金属氧化物半导体(lateraldiffused metal-oxide semiconductor,LDMOS)晶体管的半导体装置及其形成方法。
背景技术
由于在加入适当偏压的情形下，金属氧化物半导体晶体管可以视为电路中一种固态的开关(switch)，用来控制电流的导通，因此耗电量较少且适合高集成度(integration)半导体的金属氧化物半导体晶体管，已广泛地被应用在半导体工业中。而对于需承受高电压的电路，例如位于电路输入/输出端(input/output)的元件，一般多使用横向扩散金属氧化物半导体晶体管以承受较高的电压值，以避免其他核心区域因无法承受高电压而导致电性击穿(breakdown)进而造成短路。随着集成电路的发展日趋精密与复杂，如何精确地控制高压元件横向扩散金属氧化物半导体晶体管及其制作工艺，是目前集成电路制作工艺中重要的课题。
发明内容
本发明的目的在于提供一种半导体装置及其形成方法，该半导体装置是在横向扩散金属氧化物半导体晶体管的栅极与漏极之间额外设置具相反导电型式的掺杂区，因而能承受较高的电压值并能达到较佳的元件效能。
为达上述目的，本发明提供一种半导体装置，其包含一第一及第二掺杂阱、一源极区、一漏极区、二栅极结构以及一掺杂区。该第一掺杂阱，是设置在一基底内且具有第一导电型式，而该源极区则是设置在该第一掺杂阱内。该第二掺杂阱是设置在该基底内且邻该第一掺杂阱，该第二掺杂阱具有第二导电型式，而该漏极区则是设置在该第二掺杂阱内。该二栅极结构是设置在该基底上并位于该源极区与该漏极区之间。该掺杂区具有该第一导电型式，并且其是设置在该第二掺杂阱内并位于该二栅极结构之间。
本发明还提供一种半导体装置的制作工艺，包含以下步骤。首先，提供一基底。然后，在该基底内形成具有第一导电型式的一第一掺杂阱，并且在该第一掺杂阱内形成一源极区。接着，在该基底内形成具有第二导电型式的一第二掺杂阱，该第二掺杂阱邻接该第一掺杂阱，且在该第二掺杂阱内形成一漏极区。在该基底上形成二栅极结构，该栅极结构位于该源极区与该漏极区之间。最后，在该第二掺杂阱内形成具有该第一导电型式的至少一掺杂区，该掺杂区位于该二栅极结构之间。
本发明的半导体装置是在其内的LDMOS晶体管的漏极侧额外设置至少一个具有相反导电型式的掺杂区，或者是至少一个被具有相反导电型式的掺杂区环绕的浅沟槽隔离，由此，可有效提升该LDMOS晶体管的通道长度而获得内在电阻的提升。利用本发明额外设置掺杂区或浅沟槽隔离的方式，不仅可有效提升该LDMOS晶体管的内在电阻，更可有效改善习用装置内因电场与电流路径高度重叠而产生热载流子注入效应的问题。因此，本发明的半导体装置内的LDMOS晶体管能承受较高的电压值并能达到较佳的元件效能。
附图说明
图1至图5为本发明第一实施例中形成半导体装置的步骤剖面示意图，其中：
图1为本发明于本发明制作工艺之初的半导体装置；
图2为本发明于形成一沟槽后的半导体装置；
图3为本发明于形成外延结构后的半导体装置；
图4为本发明于形成一掺杂区后的半导体装置；
图5为本发明于形成插塞后的半导体装置；
图6为本发明第二实施例中半导体装置的剖面示意图；
图7至图8为本发明第三实施例中形成半导体装置的步骤剖面示意图，其中：
图7为本发明于形成一浅沟槽隔离后的半导体装置；
图8为本发明于形成一掺杂区后的半导体装置；
图9为本发明第四实施例中半导体装置的剖面示意图；
图10为本发明第五实施例中半导体装置的剖面示意图；
图11为本发明第六实施例中半导体装置的剖面示意图。
主要元件符号说明
200、400 光致抗蚀剂层
210 沟槽
240 浅沟槽
241、243、245、247 浅沟槽隔离
300 半导体基底
301 第一掺杂阱
302 第二掺杂阱
303 外延结构
303a 源极区
303b 漏极区
304、314、306、308、318、328 掺杂区
305 鳍状结构
310 氧化硅层
320 层间介电层
330a、330b 栅极结构
331 栅极介电层
332 栅极
333 间隙壁
350、370 接触插塞
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个较佳实施例，并配合所附附图，详细说明本发明的构成内容及所欲达成的功效。
请参照图1至图5，所绘示者为本发明第一实施例中形成半导体装置的制作工艺示意图。首先，如图1所示，提供一半导体基底300。具体来说，半导体基底300例如是一含硅基底(silicon substrate)、外延硅基底(epitaxial silicon substrate)或是硅覆绝缘基底(silicon on insulator,SOI)等，但并不以此为限。在一实施例中，还可选择进一步在半导体基底300内形成至少一浅沟槽隔离(shallow trench isolation,STI,未绘示)，以在半导体基底300定义出不同的主动区域(active area,AA,未绘示)。
在半导体基底300上形成一介电层，例如是一氧化硅层310，以作为一垫氧化层(pad oxide)，如图1所示。在本实施例中，该介电层的形成方式例如是进行一热氧化制作工艺，以在半导体基底300的表面上形成氧化硅层310，其可用来作为后续离子注入时的牺牲氧化层(sacrificial oxide)，以增加注入离子的散射，进而避免通道效应的发生。然而，在另一实施例中，也可选择省略该介电层而直接进行后续的离子注入，或是通过用以形成浅沟槽隔离的掩模层(未绘示)的一部分作为该介电层。
然后，在半导体基底300内依序形成彼此邻接的第一掺杂阱301及第二掺杂阱302。在一实施例中，第一掺杂阱301的形成方式例如是先在半导体基底300的表面形成一光致抗蚀剂层200，并利用一黄光制作工艺以在光致抗蚀剂层200中定义出预定形成的第一掺杂阱301的区域。然后利用光致抗蚀剂层200作为一掩模进行一第一离子注入制作工艺，在半导体基底300内形成第一掺杂阱301，如图1所示。在本实施例中，半导体基底300例如是一P型的硅基底，而第一掺杂阱301较佳具有与半导体基底300具有相同导电型式的P型掺质，但不以此为限。
接着，移除光致抗蚀剂层200，并形成同样位于半导体基底300内的第二掺杂阱302。在一实施例中，第二掺杂阱302的形成方式可与第一掺杂阱301的形成方式相同，例如是在半导体基底300的表面形成另一光致抗蚀剂层(未绘示)，并再利用一黄光制作工艺以在该光致抗蚀剂层中定义出预定形成的第二掺杂阱302的区域。然后利用该光致抗蚀剂层作为一掩模进行一第二离子注入制作工艺，以在半导体基底300内形成邻接第一掺杂阱301的第二掺杂阱302，如图2所示。第二掺杂阱302较佳具有与第一掺杂阱301具有相反的导电型式的N型掺质，但不以此为限。然后，移除该光致抗蚀剂层以及氧化硅层310。
继续于半导体基底300上形成至少一个栅极结构330。栅极结构330包含一栅极介电层331、一栅极(gate electrode)332以及一间隙壁(spacer)333。其中，栅极介电层331例如是包含氧化硅或氮化硅；栅极332则可包含不具有任何掺质多晶硅(undopedpolysilicon)材料、具有掺质的多晶硅材料、非晶硅材料或者也可以是金属材料；间隙壁333则可具有如图2所示的单层结构或者是一多层结构，并可包含高温氧化硅层(hightemperature oxide,HTO)、氮化硅、氧化硅或氮氧化硅或使用六氯二硅烷(hexachlorodisilane,Si2Cl6)形成的氮化硅(HCD-SiN)等材质，但不以此为限。
在一实施例中，栅极结构330的形成步骤例如包含在半导体基底300上形成依序堆叠的一栅极介质材料层(未绘示)以及一栅极材料层(未绘示)后，再图案化这些堆叠材料层，形成一堆叠结构。接着，在该堆叠结构两侧的半导体基底300内形成一轻掺杂源极/漏极(未绘示)，最后再于该堆叠结构的侧壁上形成间隙壁333，构成栅极结构330。然而，在另一实施例中，也可选择不移除氧化硅层310，而是于氧化硅层310上直接形成该栅极材料层，并同时图案化氧化硅层310与该栅极材料层，利用图案化后的氧化硅层310(未绘示)作为栅极结构330的栅极介电层。需注意的是，在本实施例中是选择形成两栅极结构330，其中，栅极结构330a是形成在第一掺杂阱301与第二掺杂阱302的交界之上，而栅极结构330b则是形成在第二掺杂阱302之上，如图2所示。
然后，进行一第一蚀刻制作工艺，以在栅极结构330a、330b两侧的半导体基底300内形成一沟槽210。具体来说，该第一蚀刻制作工艺在操作时应是同时以栅极结构330a、330b以及一掩模层(未绘示)作为掩模，该掩模层会遮蔽栅极结构330a、330b之间的半导体基底300，因此，仅会在栅极结构330a的左侧与栅极结构330b右侧的半导体基底300内分别形成沟槽210，如图2所示。在一实施例中，沟槽210较佳具有500埃(angstroms)至550埃的深度，但不以此为限。
于沟槽210形成后，则可选择性进行一预清洗(pre-clean)步骤，例如是利用稀释氢氟酸水溶液(diluted hydrofluoric acid)或一含有硫酸、过氧化氢、与去离子水的SPM混合溶液等清洗液来去除沟槽210表面的原生氧化物或其他不纯物质。然后，在沟槽210内形成填满沟槽210的一外延结构303，如图3所示。
外延结构303可以是如图3所示具有与半导体基底300的顶表面齐平的一表面，也可以具有高于半导体基底300的顶表面的一表面(未绘示)。外延结构303的形成方式例如是先在沟槽210的表面上共形地(conformally)形成一缓冲层(buffer layer,未绘示)，然后，接着进行一选择性外延成长制作工艺，以在该缓冲层上形成填满沟槽210的外延结构303。
需注意的是，该缓冲层例如是包含纯硅(pure silicon)或仅含10％以下掺质(dopant)的硅；外延结构303可根据后续形成的横向扩散金属氧化物半导体(LDMOS)晶体管的类型而可以具有不同的材质。举例来说，在本实施例中，预计形成N型的LDMOS晶体管，而外延结构303则可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。并且，该选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如碳原子)也可以浓度梯度的方式改变，以利后续的制作工艺。然而，在另一实施例中，若预计形成P型的LDMOS晶体管，外延结构303则可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。
然后，还可进行一掺杂制作工艺，例如较佳是与外延结构303形成时一并进行一原位掺杂(in situ doping)制作工艺或者是另外进行一离子注入制作工艺，而在栅极结构330a、330b两侧的外延结构303的至少一部分形成一源极区303a与漏极区303b，并且，源极区303a与漏极区303b是分别位于导电型是不同的第一掺杂阱301与第二掺杂阱302内，如图3所示。源极区303a与漏极区303b具有与第二掺杂阱302相同导电型式的N型掺质，但具有较浓的掺杂浓度。举例来说，第二掺杂阱302中N型掺质的掺杂浓度例如是介于5×1012至5×1013ions/cm2之间；而源极区303a与漏极区303b中N型掺质的掺杂浓度则是介于1×1015至5×1015ions/cm2之间，但不以此为限。此外，该掺杂制作工艺或该离子注入制作工艺在操作时同样是同时以栅极结构330a、330b以及该掩模层作为掩模，利用该掩模层遮盖栅极结构330a、330b之间的半导体基底300，因此，仅会在栅极结构330a的左侧与栅极结构330b右侧的外延结构303内形成源极区303a与漏极区303b。而后，移除该掩模层。
接着，再于栅极结构330a、330b之间的半导体基底300内另外形成掺杂区304，如图4所示。在一实施例中，掺杂区304的形成方式类似于前述源极区303a与漏极区303b的制作工艺，例如是先形成另一掩模层遮蔽位于栅极结构330a的左侧与栅极结构330b右侧的源极区303a与漏极区303b，然后进行一第二蚀刻制作工艺，以在栅极结构330a、330b之间的半导体基底300内形成一沟槽(未绘示)。之后，可选择性进行一预清洗步骤，例如是利用稀释氢氟酸水溶液或一含有硫酸、过氧化氢、与去离子水的SPM混合溶液等清洗液来去除该沟槽表面的原生氧化物或其他不纯物质，然后，在该沟槽内依序形成一缓冲层(未绘示)以及填满该沟槽的一外延结构(未绘示)。需注意的是，该缓冲层例如是包含纯硅或仅含10％以下掺质的硅；该外延结构则可根据后续形成的横向扩散金属氧化物半导体(LDMOS)晶体管的类型而具有相反的导电形式与材质。举例来说，在本实施例中，预计形成N型的LDMOS晶体管，该外延结构则可选择包含硅化锗，但不以此为限。再另一实施例中，若预计形成P型的LDMOS晶体管，该外延结构则可选择包含碳化硅或磷化硅。
然后，在该外延结构的至少一部分中形成掺杂区304。在本实施例中，是在进行一选择性外延成长制作工艺时同时进行一原位掺杂制作工艺，而在形成外延结构时一并于其内形成掺杂区304，如图4所示。掺杂区304具有与第一掺杂阱301相同导电型式的P型掺质，但具有较浓的掺杂浓度。举例来说，第一掺杂阱301中P型掺质的掺杂浓度例如是介于5×1012至5×1013ions/cm2之间；而掺杂区304中P型掺质的掺杂浓度则是介于1×1015至5×1015ions/cm2之间，但不以此为限。此外，在一实施例中，该选择性外延制作工艺也可以用单层或多层的方式来形成，且其异质原子(例如锗原子)也可以浓度梯度的方式改变，以利后续的制作工艺。
后续，可继续进行一应变硅通道技术(strained-Si channel technology)，以在半导体基底300上形成一接触蚀刻停止层(contact etching stop layer,CESL,未绘示)；一金属栅极置换(replacement metal gate)制作工艺，将栅极332转换为一金属栅极(未绘示)；一金属硅化物制作工艺，例如可先在源极区303a与漏极区303b的顶表面形成一硅盖层(silicon cap,未绘示)，再于源极区303a与漏极区303b的至少部分表面形成一金属硅化物层(未绘示)；及/或一接触插塞制作工艺，形成电连接源极区303a与漏极区303b与电连接栅极结构330a的接触插塞370、350。其中，接触插塞370、350是形成在位于半导体基底300上方的一层间介电层320内，层间介电层320覆盖整个栅极结构330b，使栅极结构330b作为其不会与其他外部的信号输出/输入端连结的一浮置(floating)结构，例如是作为一虚置栅极(dummy gate)结构。另一方面，掺杂区304同样是作为一浮置区域，其会被层间介电层320整体覆盖，而不会与其他外部的信号输出/输入端连结，如插塞，因此，掺杂区304表面并不会形成任何金属硅化物层。
由此，即完成本案第一实施例的半导体装置。其中，该半导体装置内的栅极结构330a、源极区303a与漏极区303b可构成一N型的LDMOS晶体管，并且该LDMOS晶体管的栅极结构330a的栅极332与漏极区303b之间额外设置有导电型式与源极区303a/漏极区303b相反的掺杂区304。掺杂区304较佳是由具有相反导电型式(P型)的外延结构而形成，且具有500埃至550埃的深度。在一般高压元件中，栅极的内在电阻值与扩散金属氧化物半导体晶体管的通道长度有关，但在本实施例中，该LDMOS晶体管由源极区303a至漏极区303b的通道因受到漏极区303b一侧的掺杂区304影响而可具有较大的通道长度，使该LDMOS晶体管的内在电阻可有效提升。此外，本发明通过在漏极区303b一侧额外设置具相反导电型式的掺杂区304的方式，还可进一步将该LDMOS晶体管的电场(electric field)拉离通道表面，因而可与电流路径(current density)区隔。由此，该LDMOS晶体管可有效降低其内的热载流子注入效应(hot carrier injection effect,HCI effect)，约降低50％左右的热载流子注入效应，故能承受较高的电压值并能达到较佳的元件效能。
此外，本领域者应可轻易了解，本发明的半导体装置也可能以其他方式形成，并不限于前述的制作步骤。因此，下文将进一步针对本发明半导体装置的其他实施例或变化型进行说明。且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
请参照图6，所绘示者为本发明第二实施例中半导体装置的剖面示意图。本实施例的半导体装置的结构与制作工艺大体上和前述第一实施例相同，其差异仅在于本实施例是在栅极结构330a、330b之间的半导体基底300内形成多个彼此分隔的掺杂区。
在本实施例中是选择形成两个掺杂区306，各掺杂区306的一侧壁分别与栅极结构330a、330b的间隙壁333切齐，如图6所示。在本实施例中，掺杂区306的形成方式、掺杂浓度与材质皆与前述第一实施例中的掺杂区304相似，容不再赘述。本实施例中虽是以形成两个掺杂区306为例，但本发明可依据装置需求随时调整形成在栅极结构330a、330b之间的掺杂区的数量，而不限于两个掺杂区。
在本实施例的半导体装置中，是在N型的LDMOS晶体管的栅极332与漏极区303b之间额外设置有多个具有相反导电型式(P型)的掺杂区306。而本实施例中的该LDMOS晶体管可因掺杂区306的作用，而获得更大的通道长度，使该LDMOS的内在电阻可有效提升。此外，本发明通过在漏极区303b一侧额外设置多个掺杂区306的方式，同样可有效降低其热载流子注入效应，故该LDMOS晶体管因而能承受较高的电压值并能达到较佳的元件效能。
请参照图7至图8所示，所绘示者为本发明第三实施例中形成半导体装置的步骤剖面示意图。本实施例的制作工艺大体上和前述第一实施例相同，其差异在于本实施例是在栅极结构330a、330b形成之前，先在半导体基底300内形成浅沟槽隔离241。
具体来说，在形成如第一实施例中图2所示的第一掺杂阱301与第二掺杂阱302之后，随即在半导体基底300的表面形成一光致抗蚀剂层400，并利用光致抗蚀剂层400进行一光刻暨蚀刻制作工艺，以在半导体基底300内形成至少一浅沟槽240。其中，浅沟槽240较佳是形成在第二掺杂阱302内，如图7所示。
然后，在浅沟槽240的表面形成一掺杂区308。在本实施例中，掺杂区308的形成方式例如是进行一选择性外延成长制作工艺并搭配一原位掺杂制作工艺，以在所形成的外延结构(未绘示)内形成掺杂区308，如图8所示。此外，掺杂区308的材质选择与导电型式等特征皆与前述第一实施例中掺杂区304大体相同，容不再赘述。然后，移除光致抗蚀剂层400，并于浅沟槽240内填入一绝缘层(未绘示)，以形成浅沟槽隔离241，其是位于第二掺杂阱302内，如图8所示。
后续，即可如第一实施例的图2所示，形成栅极结构330a、330b以及位于栅极结构330a、330b两侧的源极区303a与漏极区303b，使得浅沟槽隔离241可位于栅极结构330a、330b之间，并被掺杂区308环绕。其中，掺杂区308的两相对侧壁较佳是分别与栅极结构330a、330b的间隙壁333切齐，如图8所示，但不以此为限。
此外，在后续制作工艺中还可如前述第一实施例所示，进行一应变硅通道技术，以在半导体基底300上形成一接触蚀刻停止层(未绘示)；一金属栅极置换制作工艺，将栅极332转换为一金属栅极(未绘示)；一金属硅化物制作工艺，例如可先在源极区303a与漏极区303b的顶表面形成一硅盖层(未绘示)，再于源极区303a与漏极区303b的至少部分表面形成一金属硅化物层(未绘示)；及/或一接触插塞制作工艺，形成电连接源极区303a与漏极区303b与电连接栅极结构330a的接触插塞(未绘示)。其中，该些接触插塞是形成在一层间介电层(未绘示)内，该层间介电层可覆盖整个栅极结构330b，使栅极结构330b作为其不会与其他外部的信号输出/输入端连结的一浮置结构，例如是作为一虚置栅极结构。另一方面，掺杂区304同样是作为一浮置区域，其会被该层间介电层整体覆盖，而不会与其他外部的信号输出/输入端连结，如插塞，因此，掺杂区304表面并不会形成任何金属硅化物层。
在本实施例的半导体装置中，是在N型的LDMOS晶体管的栅极结构330a的栅极332与漏极区303b之间额外设置由相反导电型式(P型)的掺杂区306环绕的浅沟槽隔离241。而本实施例中的该LDMOS晶体管可因浅沟槽隔离241的作用，而获得较大的通道长度，使该LDMOS晶体管的内在电阻可有效提升。此外，本发明通过在漏极区303b一侧额外设置浅沟槽隔离241的方式，同样可有效降低其热载流子注入效应，故该LDMOS晶体管因而能承受较高的电压值并能达到较佳的元件效能。
请参照图9，所绘示者为本发明第四实施例中半导体装置的剖面示意图。本实施例的半导体装置的结构与制作工艺大体上和前述第三实施例相同，其差异仅在于本实施例是在栅极结构330a、330b之间的半导体基底300内形成多个浅沟槽隔离243。
在本实施例中是选择形成两个浅沟槽隔离243，其皆被同一掺杂区318所环绕，如图9所示。而掺杂区318的两相对侧壁较佳是与330a、330b的间隙壁333切齐，但不以此为限。在本实施例中，掺杂区318的形成方式、掺杂浓度与材质皆与前述第三实施例中的掺杂区308相似，容不再赘述。本实施例中虽是以形成两个浅沟槽隔离243为例，但本发明可依据装置需求随时调整形成在栅极结构330a、330b之间的浅沟槽隔离的数量，并使该些浅沟槽隔离皆被同一个相反导电型式的掺杂区所环绕。
在本实施例的半导体装置中，是在N型的LDMOS晶体管的栅极结构330a的栅极332与漏极区303b之间额外设置有多个浅沟槽隔离243以及环绕浅沟槽隔离243的相反导电型式(P型)掺杂区318。而本实施例中的LDMOS晶体管可因多个浅沟槽隔离243与掺杂区318的作用，而获得较大的通道长度，使LDMOS晶体管该的内在电阻可有效提升。此外，本发明通过在漏极区303b一侧额外设置多个浅沟槽隔离243与掺杂区318的方式，同样可有效降低其热载流子注入效应，故该LDMOS晶体管因而能承受较高的电压值并能达到较佳的元件效能。
请参照图10，所绘示者为本发明第五实施例中半导体装置的剖面示意图。本实施例的半导体装置的结构与制作工艺大体上和前述第四实施例相同，其差异仅在于本实施例是在栅极结构330a、330b之间的半导体基底300内形成多个分别被多个掺杂区328环绕的浅沟槽隔离245。
在本实施例中是选择形成两个浅沟槽隔离245，且各浅沟槽隔离245分别被两个掺杂区328所环绕。其中，各掺杂区328的一侧壁分别与栅极结构330a、330b的间隙壁333切齐，如图10所示。在本实施例中，浅沟槽隔离245与掺杂区328的形成方式、掺杂浓度与材质皆与前述第三实施例中的浅沟槽隔离241与掺杂区308相似，容不再赘述。本实施例中虽是以形成两个掺杂区328为例，但本发明可依据装置需求随时调整形成在栅极结构330a、330b之间的掺杂区的数量，而不限于图10所示的两个掺杂区。
在本实施例的半导体装置中，是在N型的LDMOS晶体管的栅极结构330a的栅极332与漏极区303b之间额外设置有多个具有相反导电型式(P型)的掺杂区328，且其内分别设置有浅沟槽隔离245。而本实施例中，LDMOS晶体管可因掺杂区328的作用，而获得更大的通道长度，使该LDMOS晶体管的内在电阻可有效提升。此外，本发明通过在漏极区303b一侧额外设置多个掺杂区328的方式，同样可有效降低其热载流子注入效应，故该LDMOS晶体管因而能承受较高的电压值并能达到较佳的元件效能。
请参照图11，所绘示者为本发明第六实施例中半导体装置的剖面示意图。本实施例的半导体装置的结构与制作工艺大体上和前述第一实施例相同，其差异仅在于本实施例的第一掺杂阱301、第二掺杂阱302以及栅极结构330等是分别形成在一鳍状结构305内或其上。
在本实施例中，是先在半导体基底300内形成突出于的至少一浅沟槽隔离247鳍状结构305，再分别形成位于鳍状结构305内或其上的源极区303a、漏极区303b以及栅极结构330等，如图11所示。然后，再于栅极结构330之间的鳍状结构305内形成由外延结构构成的掺杂区314。掺杂区314的形成方式、掺杂浓度与材质皆与前述第一实施例中的掺杂区304相似，容不再赘述。
本实施例的半导体装置是在鳍状结构305上形成N型的LDMOS晶体管，并于其漏极区303b一侧额外设置具有相反导电型式(P型)的掺杂区314，因此，同样可有效降低其热载流子注入效应而能达到较佳的元件效能。此外，另需特别注意的是，本实施例掺杂区314虽是形成在鳍状结构305内，但其制作工艺并不会导致鳍状结构305的侧边(fin edge)暴露，因而有利于半导体装置的元件稳定性。也就是说，本发明的装置与制作工艺也可以应用于其他非平面晶体管(non-planar transistor)，如鳍状场效晶体管(Fin-FET)，例如是前述第二至第五实施例中的LDMOS晶体管，同样可应用于非平面晶体管的实施样态中，且该些实施例仍应属本发明所涵盖的范围。
本发明的半导体装置是在其内的LDMOS晶体管的漏极区一侧额外设置至少一个与该漏极区的导电型式相反的掺杂区，或者是至少一个被该掺杂区环绕的浅沟槽隔离，由此，可有效提升该LDMOS晶体管的通道长度而获得内在电阻的提升。其中，该掺杂区较佳是具有外延结构，且具有500埃至550埃的深度。由此，利用本发明额外设置掺杂区或浅沟槽隔离的方式，不仅可有效提升该LDMOS晶体管的内在电阻，更可有效改善习用装置内因电场与电流路径高度重叠而产生热载流子注入效应的问题。因此，本发明的半导体装置内的LDMOS晶体管能承受较高的电压值并能达到较佳的元件效能。
此外，另需注意的是，本案前述实施例，虽皆是利用N型的LDMOS晶体管或其形成方式做为实施样态进行说明，但本发明也可用以形成P型的LDMOS晶体管，例如是在一N型的硅基底(未绘示)内形成N型的第一掺杂阱(未绘示)与P型的第二掺杂阱(未绘示)，再于该硅基底上形成P型的LDMOS晶体管，而其漏极侧则额外设置有一N型的掺杂区(未绘示)。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种半导体装置，其特征在于包含：
第一掺杂阱，设置在一基底内且具有第一导电型式；
源极区，设置在该第一掺杂阱内；
第二掺杂阱，设置在该基底内且邻接该第一掺杂阱，该第二掺杂阱具有第二导电型式；
漏极区，设置在该第二掺杂阱内；
二栅极结构，设置在该基底上并位于该源极区与该漏极区之间；以及
至少一掺杂区，设置在该第二掺杂阱内并位于该二栅极结构之间，该掺杂区具有该第一导电型式。
2.依据权利要求1所述的半导体装置，其特征在于，该二栅极结构包含第一栅极结构，该第一栅极结构设置在该第一掺杂阱与该第二掺杂阱的交界上。
3.依据权利要求1所述的半导体装置，其特征在于，该二栅极结构包含第二栅极结构，该第二栅极结构设置在该第二掺杂阱上。
4.依据权利要求3所述的半导体装置，其特征在于还包含：
介电层，该介电层覆盖该第二栅极结构。
5.依据权利要求1所述的半导体装置，其特征在于包含多个该掺杂区，该些掺杂区是分隔地设置在该二栅极结构之间。
6.依据权利要求1所述的半导体装置，其特征在于还包含：
至少一浅沟槽隔离，设置在该第二掺杂阱内并位于该二栅极结构之间。
7.依据权利要求6所述的半导体装置，其特征在于该浅沟槽隔离被该掺杂区环绕于该第二掺杂阱内。
8.依据权利要求6所述的半导体装置，其特征在于包含多个浅沟槽隔离，该些浅沟槽隔离设置在该二栅极结构之间并且被该掺杂区环绕。
9.依据权利要求6所述的半导体装置，其特征在于包含多个浅沟槽隔离，该些浅沟槽隔离设置在该二栅极结构之间并且被多个该掺杂区分别环绕。
10.依据权利要求1所述的半导体装置，其特征在于该掺杂区包含一外延结构。
11.依据权利要求10所述的半导体装置，其特征在于该掺杂区具有一顶表面，该顶表面与该基底的顶表面齐平。
12.一种形成半导体装置的方法，其特征在于包含：
提供一基底；
在该基底内形成一第一掺杂阱，该第一掺杂阱具有第一导电型式；
在该第一掺杂阱内形成一源极区；
在该基底内形成一第二掺杂阱，该第二掺杂阱邻接该第一掺杂阱并且具有第二导电型式；
在该第二掺杂阱内形成一漏极区；
在该基底上形成二栅极结构，该栅极结构位于该源极区与该漏极区之间；以及
在该第二掺杂阱内形成至少一掺杂区，该掺杂区具有该第一导电型式并位于该二栅极结构之间。
13.依据权利要求12所述的形成半导体装置的方法，其特征在于该栅极结构的形成包含：
在该第一掺杂阱与该第二掺杂阱的交界上形成一第一栅极结构。
14.依据权利要求12所述的形成半导体装置的方法，其特征在于该栅极结构的形成包含：
在该第二掺杂阱上形成一第二栅极结构。
15.依据权利要求14所述的形成半导体装置的方法，其特征在于还包含：
在该基底上形成一介电层覆盖该第二栅极结构。
16.依据权利要求12所述的形成半导体装置的方法，其特征在于该掺杂区的形成包含：
形成多个该掺杂区，该些掺杂区是分隔地形成在该二栅极结构之间。
17.依据权利要求12所述的形成半导体装置的方法，其特征在于还包含：
在该第二掺杂阱内形成至少一浅沟槽隔离，该浅沟槽隔离位于该二栅极结构之间。
18.依据权利要求17所述的形成半导体装置的方法，其特征在于该掺杂区环绕该浅沟槽隔离。
19.依据权利要求17所述的形成半导体装置的方法，其特征在于该浅沟槽隔离是在该栅极结构形成之前形成。
20.依据权利要求12所述的形成半导体装置的方法，其特征在于还包含：
在该基底上形成至少一鳍状结构，该源极区、该漏极区与该掺杂区皆形成在该鳍状结构内。
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