CN107452691B - 电子电路封装 - Google Patents
电子电路封装 Download PDFInfo
- Publication number
- CN107452691B CN107452691B CN201710276033.2A CN201710276033A CN107452691B CN 107452691 B CN107452691 B CN 107452691B CN 201710276033 A CN201710276033 A CN 201710276033A CN 107452691 B CN107452691 B CN 107452691B
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- magnetic
- electronic circuit
- circuit package
- metal film
- substrate
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
- H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
- H01F1/03—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity
- H01F1/0302—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity characterised by unspecified or heterogeneous hardness or specially adapted for magnetic hardness transitions
- H01F1/0306—Metals or alloys, e.g. LAVES phase alloys of the MgCu2-type
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
- H05K9/003—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields made from non-conductive materials comprising an electro-conductive coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
- H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
- H01F1/03—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity
- H01F1/12—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials
- H01F1/14—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys
- H01F1/20—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys in the form of particles, e.g. powder
- H01F1/22—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys in the form of particles, e.g. powder pressed, sintered, or bound together
- H01F1/24—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys in the form of particles, e.g. powder pressed, sintered, or bound together the particles being insulated
- H01F1/26—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys in the form of particles, e.g. powder pressed, sintered, or bound together the particles being insulated by macromolecular organic substances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
本说明书中所涉及的电子电路封装具备:基板,其具有电源图案;电子部件,其搭载于上述基板的表面;磁性铸模树脂,其以埋入上述电子部件的方式覆盖上述基板的上述表面并且由包含热固化性树脂材料以及磁性填料的复合磁性材料构成;金属膜,其连接于上述电源图案并且覆盖上述磁性铸模树脂的至少上表面。上述磁性铸模树脂的体积电阻值为1010Ω以上,上述磁性铸模树脂的上述上表面与上述金属膜的界面处的电阻值为106Ω以上。
Description
技术领域
本发明涉及一种电子电路封装,尤其是涉及一种具有兼备电磁屏蔽功能和磁屏蔽功能的复合屏蔽功能的电子电路封装。
背景技术
近年来,智能手机等电子设备倾向于采用高性能的无线通信电路以及数字芯片,并且所使用的半导体IC的工作频率也倾向于提高。进一步,具有以最短配线连接多个半导体IC的2.5D结构或3D结构的系统级封装(SIP:system in package)化在加速,并且可以预测电源系统电路的模块化也会在今后不断增加。进一步,可以预测多个电子部件(电感、电容、电阻、滤波器等无源元件;晶体管、二极管等有源元件;半导体IC等集成电路元件;以及其它对电子电路构成来说必要的元件的总称)被模块化后的电子电路模块也会在今后日益增加,总称这些技术的电子电路封装正处于因智能手机等电子设备的高功能化以及小型化、薄型化而被高密度安装的倾向。而另一方面,这种倾向显示由噪音引起的功能障碍以及电磁干扰变得明显,用现有的噪音对策难以防止功能障碍以及电磁干扰。因此,近年来,电子电路封装的自屏蔽化在发展,现已有通过导电性浆料或者电镀法或溅射法进行的电磁屏蔽的提案以及实用化,但是今后要求更高的屏蔽特性。
为了实现上述要求,近年来有提出兼备电磁屏蔽功能和磁屏蔽功能的复合屏蔽结构的方案。为了获得复合屏蔽结构,需要在电子电路封装中形成由导电膜(金属膜)得到的电磁屏蔽和由磁性膜得到的磁屏蔽。
例如,在日本特开昭59-132196号公报中公开有一种通过用磁性铸模树脂来将塑造电子电路并用金属盒来覆盖整体,从而提高屏蔽性的电子电路封装。
然而,在日本特开昭59-132196号公报所记载的电子电路封装中,由于用金属盒覆盖了整体,因此难以实现低背化。另外,由于在金属盒上设置了多个孔并且金属盒不连接于基板的地线图案等,所以不能获得充分的屏蔽效果。而且,如果由于电磁波噪音入射到金属盒而产生涡电流,则会有该涡电流流入到磁性铸模树脂并且磁性铸模树脂的磁特性降低的问题。
发明内容
因此,本发明的目的在于提供一种能够兼备高复合屏蔽效果和低背化并且防止由涡电流引起的磁性铸模树脂的磁特性的降低的电子电路封装。
本发明所涉及的电子电路封装具备:基板,其具有电源图案;电子部件,其搭载于上述基板的表面;磁性铸模树脂,其以埋入上述电子部件的方式覆盖上述基板的上述表面,并且由包含热固化性树脂材料以及磁性填料的复合磁性材料构成;金属膜,其连接于所述电源图案并且覆盖上述磁性铸模树脂的至少上表面,上述磁性铸模树脂的体积电阻值为1010Ω以上,上述磁性铸模树脂的上述上表面与上述金属膜的界面处的电阻值为106Ω以上。
通过本发明,由于磁性铸模树脂的体积电阻值为1010Ω以上,所以能够确保铸模构件所要求的充分的绝缘性。而且,由于磁性铸模树脂与金属膜的界面处的体积电阻值为106Ω以上,所以通过电磁波噪音入射到金属膜而产生的涡电流基本上不会流入到磁性铸模树脂。因此,能够防止由涡电流的流入引起的磁性铸模树脂的磁特性的降低。进一步,由于不使用金属盒而使用金属膜,也没有必要在铸模材料上形成磁性膜,因此能够实现低背化。
在本发明中,优选上述金属膜进一步覆盖上述磁性铸模树脂的侧面,并且上述磁性铸模树脂的上述侧面与上述金属膜的界面处的电阻值为106Ω以上。由此,能够提高侧面方向上的复合屏蔽特性。
本发明所涉及的电子电路封装也可以进一步具备设置于上述磁性铸模树脂与上述金属膜之间的绝缘材料。由此,即使是磁性铸模树脂的表面电阻低的情况下也能够将磁性铸模树脂与金属膜的界面处的电阻值控制为106Ω以上。
在本发明中,上述磁性填料优选包含软磁性金属。由此,能够提高磁性铸模树脂的磁导率。软磁性金属优选以选自Fe、Fe-Co、Fe-Ni、Fe-Al以及Fe-Si中的至少一种磁性材料作为主成分。另外,优选上述磁性填料的表面被绝缘涂布,更优选上述绝缘涂层的膜厚为10nm以上。由此,能够充分提高磁性铸模树脂的体积电阻值。上述磁性填料的形状优选为大致球状。由此,能够提高磁性铸模树脂中的磁性填料的比例。
在本发明中,上述磁性铸模树脂也可以进一步包含非磁性填料。由此,由于通过添加非磁性填料从而在磁性铸模树脂中填料被高填充率化,所以能够调整热膨胀系数。另外,通过磁性填料还能够调整成形时的流动性、介电特性以及强度、弹性模量等机械物性等,并且也能够提高耐压、绝缘性、阻燃性等。
在本发明中,上述金属膜优选以选自Au、Ag、Cu以及Al中的至少一种金属作为主成分,并且更加优选上述金属膜的表面被氧化防止覆盖层覆盖。
在本发明中,优选上述电源图案露出于上述基板的侧面,并且上述金属膜与露出于上述基板的上述侧面的上述电源图案相接触。由此,能够容易并且切实地将金属膜连接于电源图案。
本发明所涉及的电子电路封装也可以进一步具备设置于上述电子部件与上述磁性铸模树脂之间的非磁性构件。由此,能够抑制由于电子部件与磁性铸模树脂相接近而引起的电子部件特性的变动等。
这样,根据本发明,能够兼备高复合屏蔽效果和低背化,并且能够防止由涡电流引起的磁性铸模树脂的磁特性的降低。
附图说明
以下结合附图根据优选实施方式进一步说明上述本发明的特征和优点。
图1是表示本发明的第1实施方式所涉及的电子电路封装结构的截面图。
图2是表示第1实施方式的第1变形例所涉及的电子电路封装结构的截面图。
图3是表示第1实施方式的第2变形例所涉及的电子电路封装结构的截面图。
图4~图6是用于说明图1所示的电子电路封装的制造方法的工序图。
图7是表示本发明的第2实施方式所涉及的电子电路封装的结构的截面图。
图8是表示第2实施方式的变形例所涉及的电子电路封装结构的截面图。
图9和图10是用于说明图7所示的电子电路封装的制造方法的工序图。
图11是表示本发明的第3实施方式所涉及的电子电路封装的结构的截面图。
图12~图14是用于说明图11所示的电子电路封装的制造方法的工序图。
图15是表示第3实施方式的变形例所涉及的电子电路封装的结构的截面图。
图16是表示本发明的第4实施方式所涉及的电子电路封装的结构的截面图。
图17是表示实施例的测定结果的表。
具体实施方式
以下是参照附图针对本发明的优选的实施方式进行详细说明。
<第1实施方式>
图1是表示本发明的第1实施方式所涉及的电子电路封装11A的结构的截面图。
如图1所示,本实施方式所涉及的电子电路封装11A具备:基板20;搭载于基板20的多个电子部件31、32;以埋入电子部件31、32的方式覆盖基板20表面21的磁性铸模树脂40;覆盖磁性铸模树脂40的金属膜60。
对于本实施方式所涉及的电子电路封装11A的种类来说没有特别的限定,例如,可以列举处理高频信号的高频模块、进行电源控制的电源模块、具有2.5D结构或3D结构的系统级封装(SIP)、无线电通信用或数字电路用半导体封装等。在图1中只表示了2个电子部件31、32,实际上能够内置更多的电子部件。
基板20具有内部埋入有多个配线的两面以及多层配线结构,不论FR-4、FR-5、BT、氰酸酯树脂、酚醛树脂、聚酰亚胺树脂等热固化性树脂基的有机基板;液晶聚合物等热可塑性树脂基的有机基板;LTCC基板;HTCC基板;柔性基板等种类都可以。在本实施方式中,基板20为4层结构,并且具有形成于基板20的表面21以及背面22的配线层、被埋入到内部的双层配线层。在基板20的表面21上形成多个焊盘图案23。焊盘图案23是用于与电子部件31、32连接的内部电极,两者通过焊锡24(或者导电性浆料)而电连接并且机械连接。作为一个例子,电子部件31是控制器等的半导体芯片,电子部件32是电容器和线圈等无源元件。电子部件的一部分(例如薄型化了的半导体芯片等)也可以被埋入到基板20。
焊盘图案23可以通过形成于基板20内部的内部配线25连接于形成于基板20的背面22的外部端子26。在实际使用时,电子电路封装11A被安装于未图示的主板等,主板上的焊盘图案和电子电路封装11A的外部端子26电连接。作为构成焊盘图案23、内部配线25以及外部端子26的导体材料,可以是铜、银、金、镍、铬、铝、钯、铟等金属或者其金属合金,也可以是将树脂或玻璃作为胶粘剂的导电材料,但在基板20为有机基板或者柔性基板的情况下,从成本和电导率等观点出发,更优选使用铜、银。作为这些导电材料的形成方法,可以使用印刷、电镀、箔层压、溅射、蒸镀、喷墨等方法。
另外,在图1中,在符号的末尾标注有G的内部配线25表示电源图案。电源图案25G是典型地提供接地电位的地线图案,不过只要是能够提供固定电位的图案即可,并不限定于地线图案。
磁性铸模树脂40是通过以埋入电子部件31、32的方式覆盖基板20的表面21来设置的。磁性铸模树脂40是铸模构件并且也作为磁屏蔽来发挥功能。在本实施方式中,磁性铸模树脂40的侧面42和基板20的侧面27构成同一平面。磁性铸模树脂40由磁性填料分散于热固化性树脂材料所得到的复合磁性材料构成。因为磁性铸模树脂40与电子部件31、32或焊盘图形23相接触,因此有必要要求其体积电阻值充分高,具体而言有必要为1010Ω以上。
作为用于复合磁性材料的热固化性树脂材料可以使用环氧树脂、酚醛树脂、硅酮树脂、邻苯二甲酸二烯丙酯树脂、聚酰亚胺树脂、聚氨酯树脂等,并且优选使用环氧树脂或者酚醛树脂类的被用于半导体密封材料的主剂以及固化剂。材料的形态可以是液状以及固体状的任意一种,材料的形态根据对应于成形方法的主剂以及固化剂的选择而不同。在使用固体状材料的情况下,作为转送成形(transfer molding)用可以使用形成为片剂形状的材料,作为注射和压缩成型用可以使用形成为颗粒状的材料。另外,关于成形方法有通过转送成形、压缩成型、注射成形、铸造、真空铸造、配置(dispense)法、狭缝喷嘴涂布法的方法等,可作适当选择。成形条件可以根据所使用的主剂、固化剂、固化促进材料的组合作适当选择,也可以在成形后根据需要实施后固化。
作为用于复合磁性材料的磁性填料优选使用块状的磁导率高的软磁性金属。作为软磁性金属可以列举选自Fe、Fe-Co、Fe-Ni、Fe-Al以及Fe-Si中的至少一种磁性材料。作为具体例子可以列举坡莫合金(Fe-Ni合金)、超级坡莫合金(Fe-Ni-Mo合金)、铁硅铝(sendust)(Fe-Si-Al合金)、Fe-Si合金、Fe-Co合金、Fe-Cr合金、Fe-Cr-Si合金、Fe-Ni-Co合金、Fe等。对于磁性填料的形状来说并没有特别的限定,但是为了高填充化可以做成球状,并以成为最密填充的方式混合调配多个粒度分布的填料。另外,如果将磁性填料做成大致球形,则还能够减少对电子部件31、32的铸模时的损害。
为了提高流动性、紧密附着性、绝缘性,优选用Si、Al、Ti、Mg等金属的氧化物或者有机材料来将磁性填料的表面进行绝缘涂布。为了充分提高磁性铸模树脂40的体积电阻值,优选将绝缘涂层的膜厚做到10nm以上。绝缘涂层可以用热固化性材料对磁性填料的表面实行涂布处理或者由四乙氧基硅烷或四甲氧基硅烷的金属醇盐的脱水反应来形成氧化膜,最优选的是形成氧化硅的涂布覆膜。进一步更优选在其上实施有机官能性耦合处理。
在构成磁性铸模树脂40的复合磁性材料中,也可以配合非磁性填料。作为非磁性填料,如果使用熔融二氧化硅、碳酸钙、氧化镁、氧化铝、氧化钛等,则磁性铸模树脂40的绝缘性以及耐压性提高,并且能够赋予阻燃性。另外,能够调整流动性、介电常数、强度和弹性模量等机械物性。另外,通过由添加非磁性填料所达到的高填充率化,从而能够降低热膨胀系数。在此情况下,优选使用具有低热膨胀系数的填料,例如优选使用熔融二氧化硅或磷酸锆等。进一步,为了填料之间的润滑性的提高以及流动性的提高,优选使用经表面处理过的粒径为200nm以下的纳米二氧化硅。进一步,也可以对非磁性填料的表面实施用于提高紧密附着性以及流动性的耦合处理。
磁性铸模树脂40的上表面41和侧面42以及基板20的侧面27被金属膜60覆盖。金属膜60为电磁屏蔽,优选以选自Au、Ag、Cu以及Al中的至少1种金属作为主成分。金属膜60优选尽可能是低电阻,如果鉴于成本等,最优选使用Cu。另外,金属膜60的外侧表面优选被SUS、Ni、Cr、Ti、黄铜等防腐蚀性金属或者被由环氧树脂、酚醛树脂、聚酰亚胺树脂、聚氨酯树脂、硅酮树脂等树脂构成的氧化防止覆盖层覆盖。这是由于金属膜60会在热、湿度等外部环境下发生氧化劣化,所以为了抑制以及防止发生这种氧化劣化而优选实施上述处理。金属膜60的形成方法可以从溅射法、蒸镀法、无电解电镀法、电解电镀法等公知的方法中适时选择,并且也可以在形成金属膜60之前施以作为提高紧密附着性的前处理的等离子体处理、耦合处理、喷砂处理、蚀刻处理等。另外,作为金属膜60的基底可以在事前较薄地形成钛或铬、SUS等高紧密附着性金属膜。
如图1所示,电源图案25G露出于基板20的侧面27,金属膜60通过覆盖基板20的侧面27从而与电源图案25G相连接。
金属膜60与磁性铸模树脂40的界面处的电阻值为106Ω以上。因此,因为由电磁波噪音入射到金属膜60而产生的涡电流基本上不会流入到磁性铸模树脂40,所以能够防止由涡电流的流入而引起的磁性铸模树脂40的磁特性的降低。金属膜60与磁性铸模树脂40的界面处的电阻值在两者直接接触的情况下是指磁性铸模树脂40的表面电阻,在两者之间存在绝缘膜的情况下是指绝缘膜的表面电阻。另外,金属膜60与磁性铸模树脂40的界面处的电阻值优选遍布整个面为106Ω以上,也可以存在部分电阻小于106Ω的区域。
磁性铸模树脂40的表面电阻值基本上与磁性铸模树脂40的体积电阻值大致一致。因此,如果磁性铸模树脂40的体积电阻值为1010Ω以上,则基本上磁性铸模树脂40的表面电阻值也成为1010Ω以上。然而,如后面所述,磁性铸模树脂40因为在制造时被切割,所以会有由软磁性金属构成的磁性填料露出于切断面(即,侧面42)的情况,在此情况下,与体积电阻值相比,侧面42的表面电阻值相对有可能变低。同样,在以低背化或粗面化为目的而研磨磁性铸模树脂40的上表面41的情况下,也会有由软磁性金属构成的磁性填料露出于上表面41的情况,在此情况下,与体积电阻值相比,上表面41的表面电阻值有可能变低。其结果,即使磁性铸模树脂40的体积电阻为1010Ω以上,也会有磁性铸模树脂40的表面电阻值小于1010Ω的情况,但即使是这样的情况下,如果磁性铸模树脂40的表面电阻值为106Ω以上,则也能够防止涡电流的流入。
另外,在磁性铸模树脂40的上表面41或者侧面42的表面电阻值降低到小于106Ω的情况下,可以在磁性铸模树脂40的上表面41或者侧面42上形成薄的绝缘材料。图2是表示由第1变形例得到的电子电路封装11B的结构的截面图,在磁性铸模树脂40的上表面41以及侧面42与金属膜60之间夹着薄的绝缘膜70这一点上与图1所示的电子电路封装11A不同。如果夹着这样的绝缘膜70,则即使是磁性铸模树脂40的上表面41或者侧面42的表面电阻值降低到小于106Ω的情况下,也能够将金属膜60与磁性铸模树脂40的界面处的电阻值控制为106Ω以上,并防止由涡电流引起的磁特性的降低。
进一步,如果高频电感器等电子部件与磁性铸模树脂40的距离过近,则电感值等特性会从设计值偏离。在这样的情况下,通过用非磁性构件来覆盖该电子部件的一部分或者全部,从而能够减少特性的变动。图3是表示第2变形例所涉及的电子电路封装11C的结构的截面图,在电子部件32被非磁性构件50覆盖这一点上与图1所示的电子电路封装11A不同。作为非磁性构件50,可以使用一般的树脂。如果将这样的非磁性构件50夹在电子部件32与磁性铸模树脂40之间,则由于电子部件32与磁性铸模树脂40的距离拉开,因此能够降低电感值等特性的变动。
这样,本实施方式所涉及的电子电路封装11A~11C由于使用磁性铸模树脂40并且其表面被金属膜60覆盖,因此可以不在铸模树脂之外另使用磁性膜等,而获得复合屏蔽结构。由此,既能够实现低背化又能够有效地屏蔽从电子部件31、32放射的电磁波噪音或从外部入射到电子部件31、32的电磁波噪音。特别是本实施方式所涉及的电子电路封装11A~11C能够更有效地屏蔽从电子部件31、32放射的电磁波噪音。这是因为从电子部件31、32发生的电磁波噪音在通过磁性铸模树脂40时其一部分被吸收,没有被吸收的电磁波噪音的一部分在金属膜60上反射并再次通过磁性铸模树脂40。这样,由于磁性铸模树脂40相对于入射的电磁波噪音发挥2次作用,所以能够有效地屏蔽从电子部件31、32放射的电磁波噪音。
另外,由于本实施方式所涉及的电子电路封装11A~11C中,磁性铸模树脂40的体积电阻值为1010Ω以上,所以能够确保铸模构件所要求的充分的绝缘性。而且,由于磁性铸模树脂40与金属膜60的界面处的电阻值为106Ω以上,所以由于电磁波噪音入射到金属膜60而产生的涡电流基本上不会流入到磁性铸模树脂40。因此,能够防止由涡电流的流入引起的磁性铸模树脂40的磁特性的降低。
接下来,针对本实施方式所涉及的电子电路封装11A的制造方法进行说明。
图4~图6是用于说明电子电路封装11A的制造方法的工序图。
首先,如图4所示,准备具有多层配线结构的集合基板20A。在集合基板20A的表面21上形成多个焊盘图形23,在集合基板20A的背面22上形成多个外部端子26。另外,在集合基板20A的内层形成包含电源图案25G的多个内部配线25。另外,图4所示的虚线a是指在之后的切割工序中应该被切断的部分。如图4所示,电源图案25G被设置于在俯视图中与虚线a相重叠的位置。
接下来,如图4所示,以连接于焊盘图形23的方式将多个电子部件31、32搭载于集合基板20A的表面21。具体而言,可以通过在将焊锡24提供给焊盘图形23上之后搭载电子部件31、32并进行回流焊从而将电子部件31、32连接于焊盘图形23。
接下来,如图5所示,以埋入电子部件31、32的方式用体积电阻值为1010Ω以上的磁性铸模树脂40覆盖集合基板20A的表面21。作为磁性铸模树脂40的形成方法,如上所述,可以使用转送成形、压缩成型、注射成形、铸造、真空铸造、配置(dispense)法、狭缝喷嘴涂布得方法等。
接下来,如图6所示,通过沿着虚线a切断集合基板20A,从而将基板20个片化。在本实施方式中,由于电源图案25G是横切作为切割位置的虚线a,所以如果沿着虚线a切断集合基板20A,则电源图案25G从基板20的侧面27露出。
然后,如果以覆盖磁性铸模树脂40的上表面41以及侧面42、以及基板20的侧面27的方式形成金属膜60,从而完成本实施方式所涉及的电子电路封装11A。作为金属膜60的形成方法,可以使用溅射法、蒸镀法、无电解电镀法、电解电镀法等。另外,在形成金属膜60之前也可以实施作为提高紧密附着性的前处理的等离子体处理、耦合处理、喷砂处理、蚀刻处理等。进一步,作为金属膜60的基底,也可以在事前较薄地形成钛或铬等的高紧密附着性金属膜。
另外,如图2所示的变形例那样,在磁性铸模树脂40与金属膜60之间夹着绝缘膜70的情况下,可以在形成金属膜60之前,在磁性铸模树脂40的上表面41以及/或者侧面42上较薄地形成热固化性材料或耐热性热塑性材料、Si的氧化物、低熔点玻璃等绝缘材料。
这样,根据本实施方式所涉及的电子电路封装11A的制造方法,由于使用体积电阻值为1010Ω以上的磁性铸模树脂40并在其表面形成金属膜60,因此既能够实现低背化又能够获得复合屏蔽结构。
<第2实施方式>
图7是表示本发明的第2实施方式所涉及的电子电路封装12A的结构的截面图。
如图7所示,本实施方式所涉及的电子电路封装12A除了基板20以及金属膜60的形状不同这一点之外,其它均与图1所示的第1实施方式所涉及的电子电路封装11A相同。因此,将相同符号标注于相同要素,并省略重复的说明。
在本实施方式中,基板20的侧面27成为阶梯状。具体而言,具有侧面下部27b比侧面上部27a更突出的形状。然后,金属膜60不是在基板20的侧面整体地形成,而是以覆盖侧面上部27a和段差部分27c的方式设置,侧面下部27b不被金属膜60覆盖。因为在本实施方式中,电源图案25G也在基板20的侧面上部27a露出,所以金属膜60经由该部分而连接于电源图案25G。另外,在磁性铸模树脂40的上表面41以及/或者侧面42的表面电阻值小于106Ω的情况下,可以如图8所表示的变形例所涉及的电子电路封装12B那样在磁性铸模树脂40与金属膜60之间夹着薄的绝缘膜70。
图9以及图10是用于说明电子电路封装12A制造方法的工序图。
首先,根据使用图4以及图5来说明的方法在将磁性铸模树脂40形成于集合基板20A的表面21之后,如图9所示沿着表示切割位置的虚线a形成沟槽43。沟槽43的深度为完全切断磁性铸模树脂40并且不完全切断集合基板20A的深度。由此,磁性铸模树脂40的侧面42、基板20的侧面上部27a以及段差部分27c露出于沟槽43的内部。在此,作为侧面上部27a的深度,需要设定成至少露出电源图案25G的深度。
接下来,如图10所示使用溅射法、蒸镀法、无电解电镀法、电解电镀法等来形成金属膜60。由此,磁性铸模树脂40的上表面41以及沟槽43的内部被金属膜60覆盖。此时,在基板20的侧面上部27a露出的电源图案25G被连接于金属膜60。
然后,如果通过沿着虚线a切断集合基板20A从而使基板20个片化,则完成了本实施方式所涉及的电子电路封装12A。
这样,由于根据由本实施方式所涉及的电子电路封装12A的制造方法形成了沟槽43,所以能够在将集合基板20A个片化之前形成金属膜60,并且金属膜60的形成变得容易而且确实。
另外,在如图8所示的变形例那样将绝缘膜70夹在磁性铸模树脂40与金属膜60之间的情况下,可以在形成金属膜60之前,将热固化性材料或耐热性热塑性材料、Si的氧化物、低熔点玻璃等的绝缘材料较薄地形成于磁性铸模树脂40的上表面41以及/或者侧面42上。
<第3实施方式>
图11是表示本发明的第3实施方式所涉及的电子电路封装13A的结构的截面图。
如图11所示,本实施方式所涉及的电子电路封装13A中,磁性铸模树脂40的平面尺寸比基板20的平面尺寸小一点,由此基板20的表面21的外周部从磁性铸模树脂40露出,在这一点上与图1所示的第1实施方式所涉及的电子电路封装11A不同。因为其它结构均与第1实施方式所涉及的电子电路封装11A相同,所以将相同符号标注于相同要素,并省略重复的说明。
如本实施方式所涉及的电子电路封装13A所例示,在本发明中磁性铸模树脂40的侧面42不需要构成与基板20的侧面27相同的平面,也可以是磁性铸模树脂40更小。
图12~图14是用于说明电子电路封装13A制造方法的工序图。
首先,如图12所示,准备预先切断的基板20,并且以被连接于其表面21的焊盘图形23的方式搭载多个电子部件31、32。具体而言,可以通过在将焊锡24提供给焊盘图形23上之后,搭载电子部件31、32并进行回流焊从而将电子部件31、32连接于焊盘图形23。
接下来,如图13所示,将搭载有电子部件31、32的基板20装配于模具80中。然后,如图14所示,从模具80的流路81注入作为磁性铸模树脂40的材料的复合磁性材料,并进行加压及加热。之后,从模具80取出基板20,如果在磁性铸模树脂40的上面41和侧面42、以及基板20的侧面27上形成金属膜60,则完成了本实施方式所涉及的电子电路封装13A。
这样,也可以先将基板20个片化,之后再形成磁性铸模树脂40。
另外,如变形例图15所示的电子电路封装13B所示,也可以是金属膜60不覆盖基板20的侧面27的结构。在此情况下,基板20的表面21中,电源图案28G被设置于从磁性铸模树脂40露出的外周部,该电源图案28G接触于金属膜60。由此,将接地电位等固定电位提供给金属膜60。
<第4实施方式>
图16是表示本发明的第4实施方式所涉及的电子电路封装14的结构的截面图。
如图16所示,本实施方式所涉及的电子电路封装14中,磁性铸模树脂40的平面尺寸比基板20的平面尺寸大一点,在这一点上与图1所示的第1实施方式所涉及的电子电路封装11A不同。因为其它结构均与第1实施方式所涉及的电子电路封装11A相同,所以将相同符号标注于相同要素,并省略重复的说明。
如本实施方式所涉及的电子电路封装14所例示的,在本发明中,磁性铸模树脂40也可以具有大于基板20的平面尺寸。
以上针对本发明的优选实施方式进行了说明,但是本发明并不限定于上述的实施方式,可以在不脱离本发明的宗旨的范围内进行各种变更,显然那些变更也包含于本发明的范围内。
实施例
<磁性填料的制作>
首先,准备三菱制钢株式会社制造的AKT4.5Si-5.0Cr(D50=30μm)以及BASF公司制造的羰基铁粉(D50=6μm),通过金属醇盐的水解在表面上形成SiO2覆膜。SiO2覆膜的膜厚有5种:0nm(没有SiO2覆膜);5nm;10nm;30nm以及40nm。膜厚是通过FE-SEM来确认。
<复合磁性材料的制作>
接下来,以重量比成为8:2的方式秤取AKT4.5Si-5.0Cr和羰基铁粉,相对于热固化性树脂添加90wt%。所使用的热固化性树脂以及溶剂分别使用作为主剂的DIC公司制造的HP-7200H(双环戊二烯型环氧树脂)、作为固化剂的DIC公司制造的TD2231(酚醛清漆phenolnovolak)、作为固化促进剂的相对于主剂为2wt%的San-Apro Ltd.制造的U-CAT SA841(DBU的酚醛清漆树脂盐)。这样,在调配了这些化合物之后,用捏和机进行加热混炼,并获得了复合磁性材料。
<磁导率的测定>
使用上述的复合磁性材料,并制作出外径φ=8mm、内径φ=3.1mm、厚度为2mm的环状试样,使用Agilent Technologies公司制的阻抗分析仪(impedance analyzer)E4991的材料分析仪功能来测定10MHz下的磁导率μ’。测定结果为,无论SiO2覆膜的膜厚如何,磁导率都为μ’=13.8~14.5,并没有发现显著的差别(参照图17)。
<体积电阻值以及表面电阻值的测定>
接下来,依照JIS K6911使用上述的复合磁性材料来制作外径φ=100mm;厚度2mm的圆盘状试样,并其表面形成电极之后通过在电极之间施加500V电压1分钟,从而测定了体积电阻值和表面电阻值。将结果示于图17。
如图17所示,确认了SiO2覆膜的膜厚变得越厚则体积电阻值以及表面电阻值变得越高。具体而言,SiO2覆膜的膜厚为5nm的情况下的体积电阻值以及表面电阻值为107Ω,相对于此,SiO2覆膜的膜厚为10nm的情况下的体积电阻值以及表面电阻值为1012Ω。由此,能够确认到如果SiO2覆膜的膜厚为10nm以上,能够获得充分的体积电阻值以及表面电阻值。另外,在本测定中,没有对测定试样的表面实施研磨等处理,所以体积电阻值与表面电阻值显示了相同值。
<噪音衰减量测定试样的制作>
[试样A1的制作]
用压模法将上述的复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了形成于磁性填料表面的SiO2覆膜的膜厚为30nm的材料。由此,完成了试样A1。还有,在试样A1上,不形成作为电磁屏蔽的金属膜。
[试样A2的制作]
用压模法将非磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。作为非磁性材料,使用了作为通常的半导体密封材料的Sumitomo Bakelite Co.,Ltd制造的G-770H,以推荐的成形条件进行密封成形。之后,通过切割机实行个片化切断,并使地线图案露出于基板的侧面。然后,以通过实施无电解电镀从而以与地线图案相接触的方式在铸模树脂的上表面和侧面以及基板的侧面上形成由Cu(膜厚1μm)和Ni(膜厚2μm)的层叠膜构成的金属膜,并获得了试样A2。因此,试样A2不具有磁屏蔽功能。
[试样A3的制作]
用压模法将复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了没有在磁性填料的表面上施以SiO2覆膜(膜厚=0nm)的材料。之后,与试样A2同样进行个片化切割以及金属膜的形成,并获得了试样A3。
[试样A4的制作]
用压模法将复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了形成于磁性填料的表面的SiO2覆膜的膜厚为5nm的材料。之后,与试样A2同样进行了个片化切割以及金属膜的形成,并获得了试样A4。
[试样B1的制作]
用压模法将复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了形成于磁性填料的表面的SiO2覆膜的膜厚为10nm的材料。之后,与试样A2同样进行了个片化切割以及金属膜的形成,并获得了试样B1。
[试样B2的制作]
用压模法将复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了形成于磁性填料的表面的SiO2覆膜的膜厚为30nm的材料。之后,与试样A2同样进行了个片化切割以及金属膜的形成,并获得了试样B2。
[试样B3的制作]
用压模法将复合磁性材料成型于在基板上安装有50Ω的电阻的屏蔽评价用基板上。所使用的复合磁性材料使用了形成于磁性填料的表面的SiO2覆膜的膜厚为40nm的材料。之后,与试样A2同样进行了个片化切割以及金属膜的形成,并获得了试样B3。
<噪音衰减量的测定>
将试样A1~A4、B1~B3连接于信号发生器并将规定频率(20MHz、50MHz、100MHz)的信号传输至50Ω的电阻,用近磁场测定装置来测定从各个试样放射的噪音量。此时,通过事先制作了不具有磁性铸模树脂以及金属膜的基准试样,并测定从基准试样放射的噪音量从而计算出基准试样上的噪音量与测定用试样A1~A4、B1~B3上的噪音量之差,将所获得的差值作为噪音衰减量。结果示于图17中。
如图17所示,相对于不具有金属膜的试样A1,试样B1~B3在20MHz的频率中获得了22~23dBμV的屏蔽特性提高效果;在50MHz的频率中获得了28~29dBμV的屏蔽特性提高效果;在100MHz的频率中获得了32~33dBμV的屏蔽特性提高效果。另外,相对于不使用磁性铸模树脂而是使用通常的铸模树脂的试样A2,试样B1~B3在20MHz频率下获得15~16dBμV的屏蔽特性提高效果;在50MHz频率下获得了16~17dBμV的屏蔽特性提高效果;在100MHz频率下获得了14~15dBμV的屏蔽特性提高效果。进一步,相对于形成于磁性填料上的SiO2覆膜的膜厚为0nm或者5nm的试样A3、A4,试样B1~B3在20MHz的频率下获得了6~9dBμV的屏蔽特性提高效果;在50MHz的频率下获得了7~10dBμV的屏蔽特性提高效果;在100MHz的频率下获得了5~7dBμV的屏蔽特性提高效果。
由此,确认到通过使用对磁性铸模树脂施以了厚度10nm以上的SiO2覆膜的复合磁性材料来形成磁性铸模树脂,进一步用金属膜覆盖其表面从而能够获得高屏蔽特性。
Claims (13)
1.一种电子电路封装,其特征在于:
具备:
基板,其具有电源图案;
电子部件,其搭载于所述基板的表面;
磁性铸模树脂,其以埋入所述电子部件的方式覆盖所述基板的所述表面并且由包含热固化性树脂材料以及磁性填料的复合磁性材料构成;
金属膜,其连接于所述电源图案并且覆盖所述磁性铸模树脂的至少上表面,
所述磁性铸模树脂的体积电阻值为1010Ω以上,所述磁性铸模树脂的所述上表面与所述金属膜的界面处的电阻值比所述体积电阻值低,且为106Ω以上。
2.如权利要求1所述的电子电路封装,其特征在于:
所述金属膜进一步覆盖所述磁性铸模树脂的侧面,
所述磁性铸模树脂的所述侧面与所述金属膜的界面处的电阻值比所述体积电阻值低,且为106Ω以上。
3.如权利要求1所述的电子电路封装,其特征在于:
进一步具备设置于所述磁性铸模树脂与所述金属膜之间的绝缘材料。
4.如权利要求1所述的电子电路封装,其特征在于:
所述磁性填料包含软磁性金属。
5.如权利要求4所述的电子电路封装,其特征在于:
所述磁性填料的表面被绝缘涂层涂布。
6.如权利要求5所述的电子电路封装,其特征在于:
所述绝缘涂层的膜厚为10nm以上。
7.如权利要求4所述的电子电路封装,其特征在于:
所述磁性填料的形状为大致球状。
8.如权利要求4所述的电子电路封装,其特征在于:
所述磁性填料以选自Fe、Fe-Co、Fe-Ni、Fe-Al以及Fe-Si中的至少一种磁性材料作为主成分。
9.如权利要求1所述的电子电路封装,其特征在于:
所述磁性铸模树脂进一步包含非磁性填料。
10.如权利要求1所述的电子电路封装,其特征在于:
所述金属膜以选自Au、Ag、Cu以及Al中的至少一种金属作为主成分。
11.如权利要求10所述的电子电路封装,其特征在于:
所述金属膜的表面被氧化防止覆盖层覆盖。
12.如权利要求1所述的电子电路封装,其特征在于:
所述电源图案露出于所述基板的侧面,所述金属膜与露出于所述基板的所述侧面的所述电源图案相接触。
13.如权利要求1所述的电子电路封装,其特征在于:
进一步具备设置于所述电子部件与所述磁性铸模树脂之间的非磁性构件。
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JP6394719B2 (ja) | 2018-09-26 |
TWI654724B (zh) | 2019-03-21 |
CN107452691A (zh) | 2017-12-08 |
TW201739016A (zh) | 2017-11-01 |
US20170311448A1 (en) | 2017-10-26 |
JP2017199896A (ja) | 2017-11-02 |
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