CN107342237B - 制造半导体封装件的方法和制造PoP半导体装置的方法 - Google Patents

制造半导体封装件的方法和制造PoP半导体装置的方法 Download PDF

Info

Publication number
CN107342237B
CN107342237B CN201710269901.4A CN201710269901A CN107342237B CN 107342237 B CN107342237 B CN 107342237B CN 201710269901 A CN201710269901 A CN 201710269901A CN 107342237 B CN107342237 B CN 107342237B
Authority
CN
China
Prior art keywords
package
dummy
solder
balls
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710269901.4A
Other languages
English (en)
Other versions
CN107342237A (zh
Inventor
史洪宾
李俊镐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN107342237A publication Critical patent/CN107342237A/zh
Application granted granted Critical
Publication of CN107342237B publication Critical patent/CN107342237B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

公开了一种制造半导体封装件的方法和制造层叠封装(PoP)半导体装置的方法。制造半导体封装件的方法包括：提供下半导体封装件，下半导体封装件包括下封装基底以及在下封装基底的顶表面上的下虚设球和下焊料球；提供上半导体封装件，上半导体封装件包括上封装基底以及在上封装基底的底表面上的上虚设球和上焊料球；在第一温度下将上虚设球接合到下虚设球，以形成焊料接合件；在第二温度下将上焊料球接合到下焊料球，以形成连接端子。

Description

制造半导体封装件的方法和制造PoP半导体装置的方法
本专利申请要求于2016年4月28日提交到韩国知识产权局的第10-2016-0052144号韩国专利申请的优先权，该韩国专利申请的全部内容通过引用包含于此。
技术领域
发明构思涉及一种半导体封装件和一种制造该半导体封装件的方法。具体地，发明构思涉及一种层叠封装半导体装置和一种制造该层叠封装半导体装置的方法。
背景技术
在半导体产业中，对于高性能、高速度和紧凑的半导体装置和/或具有半导体装置的电器的需求正在增加。为了满足这样的需求，已经提出了各种半导体封装技术。例如，已经建议在单个基底上堆叠多个半导体芯片的方法或在一个半导体封装件上堆叠另一半导体封装件的方法。在这些情况下，需要用高的连接可靠性来连接半导体封装件。
发明内容
根据发明构思，提供了一种制造半导体封装件的方法，该方法包括：提供下半导体封装件，下半导体封装件包括下封装基底以及在下封装基底的顶表面上的下虚设球和下焊料球；提供上半导体封装件，上半导体封装件包括上封装基底以及在上封装基底的底表面上的上虚设球和上焊料球；在第一温度下将上虚设球接合到下虚设球；在第二温度下将上焊料球接合到下焊料球，以形成连接端子。
根据发明构思，还提供了一种制造半导体封装件的方法，该方法包括：提供具有第一焊料焊盘和第二焊料焊盘的下半导体封装件；在下半导体封装件上堆叠包括上焊料球和上虚设球的上半导体封装件；执行回流工艺，以将上半导体封装件连接到下半导体封装件，其中，所述回流工艺包括将上虚设球接合到第一焊料焊盘的第一工艺以及将上焊料球接合到第二焊料焊盘的第二工艺，上焊料球在第一工艺期间与下焊料球对准，其中，第一工艺中的工艺温度低于第二工艺中的工艺温度。
根据发明构思，还提供了一种制造层叠封装(PoP)半导体装置封装件的方法，该方法包括：提供下半导体装置封装件，下半导体装置封装件包括下封装基底、安装到下封装基底的下封装芯片和设置在下封装基底的上侧上的导电构件；提供上半导体装置封装件，上半导体装置封装件包括上封装基底、安装到上封装基底的上封装芯片和设置在上封装基底的下侧上的导电构件；形成包括下半导体装置封装件和上半导体装置封装件的预组装件，其中，上封装基底的下侧面对下封装基底的上侧，并且虚设构件置于上封装基底的下侧与下封装基底的上侧之间；将预组装件的下半导体装置封装件和上半导体装置封装件彼此既物理连接又电连接，其中，导电构件包括焊料，将预组装件的下半导体装置封装件和上半导体装置封装件连接的步骤包括使虚设构件液化使得在液化的虚设构件的表面处产生表面张力，并且通过对焊料进行回流来形成PoP半导体装置的内部电连接，虚设构件在对焊料进行回流之前被液化。
附图说明
通过以下结合附图对发明构思的非限制性示例的简要描述将更加清楚地理解发明构思。
图1A是根据发明构思的层叠封装件的示例的下半导体封装件的平面图。
图1B是沿图1A的线A-A'截取的剖视图。
图1C是示出根据发明构思的层叠封装件的下半导体封装件的另一示例的剖视图。
图2A是根据发明构思的层叠封装件的示例的上半导体封装件的底视图。
图2B是沿图2A的线B-B'截取的剖视图。
图3、图4、图5和图6是根据发明构思的层叠封装半导体装置在其制造过程期间并且一起示出了制造该层叠封装半导体装置的方法的剖视图。
图7至图8是根据发明构思的层叠封装半导体装置在其制造过程期间并且一起示出了制造该层叠封装半导体装置的方法的其它示例的剖视图。
图9是示出根据发明构思的层叠封装半导体装置的示例的剖视图。
应该注意的是，这些附图意图示出某些示例的方法、结构和/或材料的一般的特性，并且意图补充以下提供的书面描述。然而，这些附图不是按比例的，并且可以不精确地反映任何给出的示例的精确的结构特性或性能特性，并且不应被解释为限定或限制发明构思所包括的值或性质的范围。例如，为了清楚起见，可以减小或夸大分子、层、区域和/或结构元件的相对厚度和位置。在各种附图中的相似或相同的附图标记的使用意图表示存在相似或相同的元件或特征。
具体实施方式
图1A是根据发明构思的下半导体封装件100的平面图。图1B是沿图1A的线A-A'截取的剖视图。图1C是示出根据发明构思的下半导体封装件101的剖视图。图2A是根据发明构思的上半导体封装件200的底视图。图2B是沿图2A的线B-B'截取的剖视图。
参照图1A和图1B，下半导体封装件100可以包括下封装基底110、下半导体芯片120、下成型层130、下焊料球140和下虚设球150。在这里以及在以下的描述中，为了方便起见，将以单数描述诸如下焊料球140和下虚设球150的某些元件，虽然根据发明构思这样的元件可以如附图中所示和在实际生活示例中设置为多个。另外，在这里以及在以下的描述中，术语“球”可以不必用于描述完全地或基本上球形的物体，而是可以仅表示物体具有例如如在图1A中示出的平面图中所观察到的大体上圆形的形状。
下封装基底110可以具有在相对方向上背对的第一顶表面110a和第一底表面110b。下封装基底110可以是具有电路图案的印刷电路板(PCB)或再分布基底。外部端子112(例如，焊料球或焊料凸块)可以设置在下封装基底110的第一底表面110b上。
下半导体芯片120可以是逻辑芯片或存储芯片。在下半导体芯片120是逻辑芯片的示例中，逻辑芯片可以被构造为包括逻辑元件和存储元件。在下半导体芯片120是存储芯片的示例中，存储芯片可以包括DRAM、NAND FLASH、NOR FLASH、One-NAND、PRAM、ReRAM和MRAM装置中的至少一种。此外，下半导体芯片120可以安装在下封装基底110的第一顶表面110a上。例如，下半导体芯片120可以通过使用倒装芯片键合方法安装在下封装基底110上。换言之，下半导体芯片120可以通过连接端子122(例如，焊料球或焊料凸块)电连接到下封装基底110。然而，发明构思不限于此；例如，下半导体芯片120可以通过键合引线(未示出)电连接到下封装基底110。
下成型层130可以设置在下封装基底110上以围绕下半导体芯片120。下成型层130可以由绝缘聚合物材料(例如，环氧模塑化合物(EMC))形成或者包括绝缘聚合物材料(例如，环氧模塑化合物(EMC))。在一些示例中，下成型层130可以设置为暴露下半导体芯片120的顶表面。在某些示例中，虽然未示出，但下成型层130可以设置为覆盖下半导体芯片120的顶表面。另外，连接孔132可以穿过下成型层130来设置。连接孔132可以与下半导体芯片120分隔开。作为示例，连接孔132被设置为关于下半导体芯片120对称。
下焊料球140和下虚设球150可以设置在连接孔132中，并且可以与下封装基底110接触。例如，当在平面图中观察时，下焊料球140相比于下虚设球150可以较靠近于下封装基底110的边缘。换言之，下虚设球150相比于下焊料球140可以较靠近于下半导体芯片120。当在平面图中观察时，下虚设球150的宽度w2可以比下焊料球140的宽度w1大。
另外，下焊料球140可以电连接到下封装基底110。另一方面，顾名思义，下虚设球150可以被电隔离，以免在最终的封装件中形成任何电连接。另外，下虚设球150的体积可以比下焊料球140的体积大。这可以使得连接焊料(连接焊料可以通过使上虚设球和下虚设球150熔化的后续工艺来形成)具有增大的表面张力。下虚设球150可以具有从128℃至216℃的范围的熔点。例如，下虚设球150可以由Bi58Sn42、In97Ag3、In90Ag10、In75Pb25、In70Pb30、In60Pb40、In50Sn50、In52Sn48、Sn86.5Zn5.5In4.5Bi3.5、Bi57Sn42Ag1、Sn43Pb43Bi14、Sn46Pb46Bi8、Bi52Pb32Sn16或Bi46Sn34Pb20形成，或者可以包括Bi58Sn42、In97Ag3、In90Ag10、In75Pb25、In70Pb30、In60Pb40、In50Sn50、In52Sn48、Sn86.5Zn5.5In4.5Bi3.5、Bi57Sn42Ag1、Sn43Pb43Bi14、Sn46Pb46Bi8、Bi52Pb32Sn16或Bi46Sn34Pb20。下焊料球140可以由熔点比下虚设球150的熔点高的材料形成，或者可以包括熔点比下虚设球150的熔点高的材料。例如，下焊料球140可以由Sn96.5Ag3Cu0.5、Sn96.8Ag3Cu0.2或Sn97Ag2.5Cu0.5形成，或者可以包括Sn96.5Ag3Cu0.5、Sn96.8Ag3Cu0.2或Sn97Ag2.5Cu0.5。下焊料球140可以设置在下封装基底110的第一顶表面110a上，并且可以电连接到下封装基底110和下半导体芯片120。在本说明书中，术语“焊料”可以指导电材料(例如，锡、金、银或铜)或其合金(例如，Sn-In、Sn-Au、Sn-Cu或Sn-Bi)，术语“焊料球”可以指具有球形形状等的导电元件。
作为图1B中示出的示例的替代，如图1C中所示，下半导体封装件101还可以包括插入基底160。参照图1C，插入基底160可以设置在下半导体芯片120和下成型层130上。第一焊料焊盘170和第二焊料焊盘180可以设置在插入基底160的顶表面上。当在平面图中观察时，第二焊料焊盘180相比于第一焊料焊盘170可以较靠近于下半导体芯片120。第二焊料焊盘180的宽度可以比第一焊料焊盘170的宽度大。第一焊料焊盘170可以通过下焊料球140电连接到下封装基底110。在某些示例中，省略了下虚设球150。为了方便起见，下面的描述将参照图1B的下半导体封装件100，但是以下将描述的方法可按相同的方式应用于图1C的结构。
参照图2A和图2B，上半导体封装件200可以包括上封装基底210、上半导体芯片220、上成型层230、上焊料球240和上虚设球250。
上封装基底210可以具有在相对方向上背对的第二顶表面210a和第二底表面210b。上封装基底210可以是具有电路图案的印刷电路板(PCB)。
上半导体芯片220可以安装在上封装基底210的第二顶表面210a上。例如，上半导体芯片220可以通过使用引线键合方法安装在上封装基底210上。换言之，上半导体芯片220可以通过键合引线222电连接到上封装基底210。此外，上半导体芯片220可以通过置于上半导体芯片220和上封装基底210之间的绝缘粘附层(未示出)附着到上封装基底210。上半导体芯片220可以是逻辑芯片或存储芯片。虽然图2B示出了具有单个上半导体芯片的上半导体封装件200，但发明构思不限于此。上半导体封装件200可以包括堆叠在上封装基底210上的至少两个上半导体芯片。
上成型层230可以设置在上封装基底210上以围绕上半导体芯片220。例如，上成型层230可以覆盖上半导体芯片220和上封装基底210的第二顶表面210a。上成型层230可以由绝缘聚合物材料(例如，环氧模塑化合物(EMC))形成，或者可以包括绝缘聚合物材料(例如，环氧模塑化合物(EMC))。
上焊料球240和上虚设球250可以设置在上封装基底210的第二底表面210b上。例如，当在平面图中观察时，上焊料球240相比于上虚设球250可以较靠近于上封装基底210的边缘。这里，上焊料球240和上虚设球250可以分别设置在与下焊料球140和下虚设球150对应的位置处。当在平面图中观察时，上虚设球250的宽度w4可以比上焊料球240的宽度w3大。
另外，上焊料球240可以通过上封装基底210电连接到上半导体芯片220。另一方面，顾名思义，上虚设球250可以被电隔离，以免在最终的封装件中形成任何电连接。另外，上虚设球250的体积可以比上焊料球240的体积大，这可以使得连接焊料((连接焊料可以通过使上虚设球250和下虚设球150熔化的后续工艺来形成))具有增大的表面张力。在一些示例中，上虚设球250可以由与下虚设球150的材料相同的材料形成，或者可以包括与下虚设球150的材料相同的材料。换言之，上虚设球250可以具有从128℃至216℃的范围的熔点。例如，上虚设球250可以由Bi58Sn42、In97Ag3、In90Ag10、In75Pb25、In70Pb30、In60Pb40、In50Sn50、In52Sn48、Sn86.5Zn5.5In4.5Bi3.5、Bi57Sn42Ag1、Sn43Pb43Bi14、Sn46Pb46Bi8、Bi52Pb32Sn16或Bi46Sn34Pb20形成，或者可以包括Bi58Sn42、In97Ag3、In90Ag10、In75Pb25、In70Pb30、In60Pb40、In50Sn50、In52Sn48、Sn86.5Zn5.5In4.5Bi3.5、Bi57Sn42Ag1、Sn43Pb43Bi14、Sn46Pb46Bi8、Bi52Pb32Sn16或Bi46Sn34Pb20。上焊料球240的熔点可以比上虚设球250的熔点高。上焊料球240可以由与下焊料球140的材料相同的材料形成，或者可以包括与下焊料球140的材料相同的材料。例如，上焊料球240可以由Sn96.5Ag3Cu0.5、Sn96.8Ag3Cu0.2或Sn97Ag2.5Cu0.5形成，或者包括Sn96.5Ag3Cu0.5、Sn96.8Ag3Cu0.2或Sn97Ag2.5Cu0.5。上焊料球240可以附着到上封装基底210的第二底表面210b，并且可以电连接到上封装基底210和上半导体芯片220。
在下文中，将描述根据发明构思的制造半导体封装件的方法。为了简明起见，可以通过相似或相同的附图标记来表示前面描述的元件，并且不重复对其详细方面的描述。
图3至图8是示出根据发明构思的制造半导体封装件的方法的剖视图。
参照图3，可以将上半导体封装件200设置在下半导体封装件100上。下半导体封装件100可以被制造为具有与参照图1A和图1B描述的特征基本上相同的特征。例如，下半导体封装件100可以被制造为包括下封装基底110、下半导体芯片120、下成型层130、下焊料球140和下虚设球150。
上半导体封装件200可以被制造为具有与参照图2A和图2B描述的特征基本上相同的特征。例如，上半导体封装件200可以被制造为包括上封装基底210、上半导体芯片220、上成型层230、上焊料球240和上虚设球250。
可以将上焊料球240和上虚设球250分别设置在与下焊料球140和下虚设球150对应的位置处。换言之，当在平面图中观察时，上焊料球240可以设置在下焊料球140上，上虚设球250可以设置在下虚设球150上。在某些情况中，上焊料球240和下焊料球140可能未对准，上虚设球250和下虚设球150可能彼此未对准。这样的未对准可能是通过例如制造系统的机械误差引起的。
结果，形成了层叠封装式的半导体封装件的预组装件。图3示出了下半导体封装件100和上半导体封装件200以距离d未对准(即，在给定的水平方向上彼此横向偏离)的预组装件的示例。
参照图4和图5，可以执行第一工艺以将上虚设球250接合到下虚设球150。可以在第一温度下执行第一工艺。第一温度可以比上焊料球240和下焊料球140的熔点低并且比上虚设球250和下虚设球150的熔点高。在一些示例中，第一温度可以在从128℃至216℃的范围。因此，可以使上虚设球250和下虚设球150熔化并熔合为单个焊料接合件。例如，可以使上虚设球250和下虚设球150熔合以形成连接焊料310。
作为第一工艺的结果，可以使下半导体封装件100和上半导体封装件200自对准。更具体地，当连接焊料310处于液态时，连接焊料310可以具有与其表面积成比例的表面能。结果，连接焊料310的上部分和下部分可以在由图4中示出的箭头表示的方向上相对于彼此横向移动。即，连接焊料310可以具有比在开始时下半导体封装件100和上半导体封装件200便对准的情况下将另外具有的表面积大的表面积。因此，连接焊料310可以由于表面张力而变形，以这样的方式来减小其表面积。因此，如图5中所示，连接焊料310的上部分和下部分可以变得对准。此时，上焊料球240也可以与下焊料球140对准。换言之，上半导体封装件200的上焊料球240和下半导体封装件100的下焊料球140可以由于在连接焊料310中产生的表面张力而对准。
同时，在上虚设球250的宽度w4和下虚设球150的宽度w2相对大的情况下，连接焊料310可以具有相对大的体积和相应地大的表面积。连接焊料310的表面积可以与表面张力成比例，大的表面积因此可以使得上半导体封装件200和下半导体封装件100能够有效地对准。随后，可以在升高的温度的条件下在执行第一工艺的同一腔室中执行第二工艺。
参照图6，可以执行第二工艺以将下半导体封装件100连接到上半导体封装件200，从而形成半导体封装件1。例如，在第二工艺期间，可以使下焊料球140和上焊料球240接合或混合以形成在半导体封装件1中构成内部电连接的连接端子400。即，下半导体封装件100可以通过连接端子400电连接且物理连接到上半导体封装件200。可以在第二温度下执行第二工艺。第二温度可以基本上等于或高于上焊料球240和下焊料球140的熔点。例如，第二温度可以在从217℃至245℃的范围。即，第二温度下的第二工艺可以引起上焊料球240和下焊料球140的焊料的回流或熔化。随后，可以将工艺温度降低至室温。当工艺温度降低到第二温度以下时，可以使处于液态的上焊料球240和下焊料球140凝固以彼此熔合并且形成连接端子400。连接端子400可以是使形成下焊料球140和上焊料球240的材料混合的合金。另外，当工艺温度降低到第一温度以下时，可以使连接焊料310凝固以形成虚设端子320。可以通过虚设端子320使下半导体封装件100物理连接到上半导体封装件200。虚设端子320在得到的半导体封装件1中被电隔离，即，虚设端子320至少与外部端子112电隔离。
作为以上工艺的结果，半导体封装件1可以包括下半导体封装件100、上半导体封装件200、连接端子400和虚设端子320。
可以使连接端子400和虚设端子320设置在下半导体封装件100与上半导体封装件200之间。可以使连接端子400和虚设端子320设置在下半导体芯片120的外围处。当在平面图中观察时，虚设端子320相比于连接端子400可以较靠近于下半导体芯片120设置。另外，虚设端子320的宽度w6可以比连接端子400的宽度w5大。连接端子400可以将下半导体封装件100与上半导体封装件200电连接。虚设端子320可以使得半导体封装件1对热应力具有高的耐受性。例如，当半导体封装件1的温度有变化时，半导体封装件1可能遭受热应力，所述热应力可能由于在封装基底110和210与半导体芯片120和220的热膨胀系数上的差异而出现。热应力的大小可以随着距离半导体芯片120和220的距离减小而增大。根据发明构思的一些示例，半导体封装件1可以包括相邻于半导体芯片120和220设置的虚设端子320。虚设端子320可以吸收由热膨胀系数上的差异引起的热应力，因此，可以能够防止连接端子400被热应力损坏。
图7至图8是示出了根据发明构思的其它示例的制造半导体封装件的方法的剖视图。
参照图7，可以将图6的半导体封装件1安装在板510上。板510可以是用于移动装置(例如，蜂窝电话)或存储模块的板。可以在板510上设置板端子520。可以将板端子520连接到外部端子112以将板510电连接到半导体封装件1。
在某些示例中，可以在第一工艺之前执行外部端子112和板端子520的连接。参照图8，可以使板端子520和外部端子112接合以将板510电连接到下半导体封装件100。随后，可以执行第一工艺和第二工艺来将上半导体封装件200连接到下半导体封装件100。
在某些示例中，可以在将上焊料球240附着到下焊料球140的第二工艺期间执行外部端子112和板端子520的连接。例如，第二工艺可以包括回流工艺，可以在回流工艺期间使外部端子112和板端子520接合。
根据发明构思的一些示例，可以通过将图2B的上半导体封装件200安装在包括插入基底160的下半导体封装件101(例如，如图1C中所示)上来制造半导体封装件。除此以外，在这些示例中，制造半导体封装件的方法可以与参照图3至图6描述的方法相同。
图9是示出根据发明构思的另一示例的半导体封装件的剖视图。
参照图1C、图2B和图9，上半导体封装件200可以设置在下半导体封装件101上。当在平面图中观察时，上焊料球240可以设置在第一焊料焊盘170上，上虚设球250可以设置在第二焊料焊盘180上。在某些情况下，上焊料球240可能与第一焊料焊盘170未对准，上虚设球250可能与第二焊料焊盘180未对准。
可以执行第一工艺以使上虚设球250附着到第二焊料焊盘180。可以在低于上焊料球240的熔点并且高于上虚设球250的熔点的第一温度下执行第一工艺。因此，在第一工艺期间，可以使上虚设球250熔化以形成连接焊料310。与图4和图5的示例相似，下半导体封装件101可以在第一工艺期间与上半导体封装件200自对准。例如，连接焊料310的上部分可以与其下部分横向偏离。与没有未对准的情况相比，这可以引起连接焊料310的表面积的增加，在未对准的情况下，由于表面张力，连接焊料310可以变形而具有减小的表面积。作为连接焊料310的表面张力的结果，上焊料球240和第一焊料焊盘170可以彼此对准。
可以执行第二工艺以使上焊料球240附着到第一焊料焊盘170。可以在高于上焊料球240的熔点的第二温度下执行第二工艺。因此，在第二工艺期间，可以使上焊料球240熔化。随后，可以将工艺温度降低至室温。因此，可以使熔化的上焊料球240凝固以形成连接端子400，可以使连接焊料310凝固以形成虚设端子320。
如上所述，所述方法可以应用于制造设置有具有插入基底160的下半导体封装件101的半导体封装件，但发明构思可以不限于此。在某些示例中，下半导体封装件可以是包括半导体层(例如，硅层)的芯片级或晶圆级半导体基底，或者可以包括具有半导体层(例如，硅层)的芯片级或晶圆级半导体基底。因此，术语“芯片”可以指封装的IC或裸IC。
在制造半导体封装件的工艺中，上半导体封装件和下半导体封装件之间的未对准可能超过给定的公差。具体地，随着半导体装置的集成密度的增加，用于上半导体封装件和下半导体封装件之间的未对准的公差变得越来越小。根据发明构思的一些示例，虚设端子320可以使得上半导体封装件200与下半导体封装件100以提高的精度对准。
根据发明构思的一些示例，制造半导体封装件的方法可以包括在低于上焊料球和下焊料球的熔点的温度下对上虚设球和下虚设球执行回流工艺。在回流工艺期间，可以使上虚设球和下虚设球熔化以形成连接焊料，连接焊料的表面张力可以使得上焊料球能够与下焊料球对准。结果，上焊料球和下焊料球可以在没有未对准的情况下彼此接合。
根据发明构思的一些示例，半导体封装件可以被制造为对热应力具有高的耐受性。例如，半导体封装件可以包括虚设端子，虚设端子相邻于半导体芯片设置并且用于吸收将要在半导体封装件中产生的机械应力。因此，可以能够防止或者抑制机械应力作用在用于将上半导体封装件和下半导体封装件彼此电连接的连接端子上。
虽然已经具体地示出和描述了发明构思的示例，但本领域普通技术人员将理解的是，在不脱离由附加权利要求限定的发明构思的精神和范围的情况下，可以对这样的示例做各种形式上和细节上的改变。

Claims (17)

1.一种制造半导体封装件的方法，所述方法包括以下步骤：
提供下半导体封装件，下半导体封装件包括下封装基底、位于下封装基底的顶表面上的下虚设球和下焊料球以及安装在下封装基底的顶表面上的下半导体芯片；
提供上半导体封装件，上半导体封装件包括上封装基底以及位于上封装基底的底表面上的上虚设球和上焊料球；
通过在第一温度下将上虚设球接合到下虚设球来形成焊料的虚设接合件，以使上焊球对准到下焊球；
在比第一温度高的第二温度下将上焊料球接合到下焊料球，以形成连接端子，其中，在形成连接端子期间，焊料的虚设接合件处于液态；
将工艺温度降低到第二温度以下，使得连接端子凝固；以及
将工艺温度降低到第一温度以下，使得焊料的虚设接合件凝固以形成虚设端子，
其中，在平面图中，下虚设球相比于下焊料球较靠近于下半导体芯片。
2.根据权利要求1所述的方法，其中，第一温度比上虚设球和下虚设球的熔点高并且比上焊料球和下焊料球的熔点低。
3.根据权利要求1所述的方法，其中，第二温度比上焊料球和下焊料球的熔点高。
4.根据权利要求1所述的方法，其中，上虚设球和下虚设球的熔点比上焊料球和下焊料球的熔点低。
5.根据权利要求1所述的方法，其中，上半导体封装件还包括安装在上封装基底的顶表面上的上半导体芯片。
6.根据权利要求5所述的方法，其中，在平面图中，上虚设球相比于上焊料球较靠近于上半导体芯片。
7.根据权利要求1所述的方法，其中，上虚设球具有比上焊料球的宽度大的宽度，
下虚设球具有比下焊料球的宽度大的宽度。
8.根据权利要求1所述的方法，所述方法还包括在将上虚设球接合到下虚设球之前，将下半导体封装件安装在板上，所述板设置在下半导体封装件的底表面上。
9.一种制造半导体封装件的方法，所述方法包括以下步骤：
提供具有第一焊料焊盘和第二焊料焊盘的下半导体封装件；
在下半导体封装件上堆叠包括上焊料球和上虚设球的上半导体封装件；
执行回流工艺，以将上半导体封装件连接到下半导体封装件；以及
将工艺温度降至室温，以在上半导体封装件与下半导体封装件之间形成连接端子和虚设端子，
其中，所述回流工艺包括：将上虚设球熔化并接合到第一焊料焊盘的第一工艺，上焊料球在第一工艺期间与第二焊料焊盘对准；
将上焊料球熔化并接合到第二焊料焊盘的第二工艺，
其中，第一工艺中的工艺温度低于第二工艺中的工艺温度，
其中，所述上虚设球在第二工艺期间处于液态，
其中，在将工艺温度降至室温期间，熔化的上焊料球凝固以形成连接端子，然后，熔化的上虚设球凝固以形成虚设端子，并且
其中，上焊料球相比于上虚设球较靠近于上半导体封装件的边缘。
10.根据权利要求9所述的方法，其中，上虚设球的熔点比上焊料球的熔点低。
11.根据权利要求9所述的方法，其中，上虚设球具有比上焊料球的宽度大的宽度。
12.根据权利要求9所述的方法，其中，下半导体封装件还包括：
下半导体芯片，安装在下封装基底上；以及
插入基底，设置在下半导体芯片上，
其中，第一焊料焊盘和第二焊料焊盘设置在插入基底的顶表面处。
13.一种制造层叠封装半导体装置的方法，所述方法包括以下步骤：
提供下半导体装置封装件，所述下半导体装置封装件包括下封装基底、安装到下封装基底的下封装芯片和设置在下封装基底的上侧上的导电构件；
提供上半导体装置封装件，所述上半导体装置封装件包括上封装基底、安装到上封装基底的上封装芯片和设置在上封装基底的下侧上的导电构件；
形成包括所述下半导体装置封装件和所述上半导体装置封装件的预组装件，其中，上封装基底的下侧面对下封装基底的上侧，并且虚设构件置于上封装基底的下侧与下封装基底的上侧之间；以及
将预组装件的下半导体装置封装件和上半导体装置封装件彼此既物理连接又电连接，
其中，下封装芯片置于预组装件中的下封装基底与上封装基底之间，并且在预组装件的平面图中，虚设构件定位为相比于导电构件较靠近于下封装芯片，
其中，导电构件包括焊料，
将预组装件的下半导体装置封装件和上半导体装置封装件连接的步骤包括：使虚设构件液化，使得在液化的虚设构件的表面处产生表面张力；通过使焊料回流来形成层叠封装半导体装置的内部电连接，
虚设构件在焊料回流之前被液化，并且在经回流的焊料凝固之后凝固。
14.根据权利要求13所述的方法，其中，虚设构件具有一定的熔点，焊料具有焊料开始回流时的回流温度，
焊料的回流温度比虚设构件的熔点高，
将预组装件的下半导体装置封装件和上半导体装置封装件连接的步骤包括：将虚设构件加热到虚设构件的熔点处或虚设构件的熔点以上的温度；在虚设构件已被液化之后，将焊料加热到回流温度处或回流温度以上的温度。
15.根据权利要求13所述的方法，其中，虚设构件均具有比每个导电构件的体积大的体积。
16.根据权利要求13所述的方法，其中，下半导体装置封装件具有所述虚设构件的设置在下封装基底的上侧上的下面一组虚设构件，
上半导体装置封装件具有所述虚设构件的设置在上封装基底的下侧上的上面一组虚设构件，
形成预组装件的步骤包括将下面一组虚设构件与上面一组虚设构件彼此相对地放置。
17.根据权利要求13所述的方法，其中，预组装件包括置于上半导体装置封装件与下封装芯片之间的插入件，所述插入件具有导电材料的焊盘，
形成预组装件的步骤包括将一组虚设构件与插入件彼此相对地放置。
CN201710269901.4A 2016-04-28 2017-04-24 制造半导体封装件的方法和制造PoP半导体装置的方法 Active CN107342237B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2016-0052144 2016-04-28
KR1020160052144A KR102544776B1 (ko) 2016-04-28 2016-04-28 반도체 패키지의 제조 방법

Publications (2)

Publication Number Publication Date
CN107342237A CN107342237A (zh) 2017-11-10
CN107342237B true CN107342237B (zh) 2023-07-04

Family

ID=60158529

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710269901.4A Active CN107342237B (zh) 2016-04-28 2017-04-24 制造半导体封装件的方法和制造PoP半导体装置的方法

Country Status (3)

Country Link
US (1) US9985008B2 (zh)
KR (1) KR102544776B1 (zh)
CN (1) CN107342237B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210075662A (ko) * 2019-12-13 2021-06-23 삼성전자주식회사 반도체 패키지
KR20210131548A (ko) 2020-04-24 2021-11-03 삼성전자주식회사 반도체 패키지
US20220199593A1 (en) * 2020-12-22 2022-06-23 Mediatek Inc. Semiconductor device with dummy thermal features on interposer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112463A (ja) * 1992-09-25 1994-04-22 Mitsubishi Electric Corp 半導体装置及びその実装方法
JP2007194274A (ja) * 2006-01-17 2007-08-02 Nec Electronics Corp 半導体装置の製造方法
CN101071779A (zh) * 2006-05-08 2007-11-14 矽品精密工业股份有限公司 半导体封装件堆栈结构及其制法
CN104576557A (zh) * 2013-10-29 2015-04-29 三星电子株式会社 包括插入件开口的半导体封装件装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112463A (ja) * 1984-06-29 1986-01-20 Hankyu Dentetsu Kk 車両用非常空気ブレ−キの操作回路
JPH11243156A (ja) 1998-02-25 1999-09-07 Toshiba Corp 半導体装置
US6781245B2 (en) 2001-01-08 2004-08-24 Siliconware Precision Industries Co., Ltd. Array structure of solder balls able to control collapse
JP2002373914A (ja) 2001-06-15 2002-12-26 Ricoh Co Ltd 電子部品接続構造体
JP2003031614A (ja) 2001-07-13 2003-01-31 Sony Corp 半導体デバイス、半導体モジュール及びこれらの実装方法
JP4082220B2 (ja) * 2003-01-16 2008-04-30 セイコーエプソン株式会社 配線基板、半導体モジュールおよび半導体モジュールの製造方法
JP2004259886A (ja) 2003-02-25 2004-09-16 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP2006012883A (ja) 2004-06-22 2006-01-12 Matsushita Electric Ind Co Ltd 電子部品はんだ接合方法，エリアアレイ型電子部品，電子回路基板および電子部品ユニット
KR101131138B1 (ko) * 2006-01-04 2012-04-03 삼성전자주식회사 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지
KR20070075718A (ko) 2006-01-16 2007-07-24 삼성전자주식회사 스택 패키지와 그 제조 방법
KR101624973B1 (ko) * 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
KR20110139367A (ko) 2010-06-23 2011-12-29 앰코 테크놀로지 코리아 주식회사 미스 얼라인먼트 방지 구조를 갖는 반도체 패키지
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US8389329B2 (en) * 2011-05-31 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US8901730B2 (en) * 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US9111896B2 (en) 2012-08-24 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package semiconductor device
US9831214B2 (en) 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112463A (ja) * 1992-09-25 1994-04-22 Mitsubishi Electric Corp 半導体装置及びその実装方法
JP2007194274A (ja) * 2006-01-17 2007-08-02 Nec Electronics Corp 半導体装置の製造方法
CN101071779A (zh) * 2006-05-08 2007-11-14 矽品精密工业股份有限公司 半导体封装件堆栈结构及其制法
CN104576557A (zh) * 2013-10-29 2015-04-29 三星电子株式会社 包括插入件开口的半导体封装件装置

Also Published As

Publication number Publication date
KR102544776B1 (ko) 2023-06-20
US9985008B2 (en) 2018-05-29
CN107342237A (zh) 2017-11-10
US20170317062A1 (en) 2017-11-02
KR20170123376A (ko) 2017-11-08

Similar Documents

Publication Publication Date Title
US8076232B2 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
TWI518812B (zh) 形成導線上凸塊互連的半導體裝置及方法
US7420814B2 (en) Package stack and manufacturing method thereof
JP5068990B2 (ja) 電子部品内蔵基板
US8963311B2 (en) PoP structure with electrically insulating material between packages
US20100258933A1 (en) Semiconductor device, method of forming the same, and electronic device
US20070216008A1 (en) Low profile semiconductor package-on-package
CN101145545A (zh) 包括元件安装表面被树脂层涂覆的布线基板的半导体装置
US11869829B2 (en) Semiconductor device with through-mold via
US20080258286A1 (en) High Input/Output, Low Profile Package-On-Package Semiconductor System
US8008765B2 (en) Semiconductor package having adhesive layer and method of manufacturing the same
US11482500B2 (en) Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
CN107342237B (zh) 制造半导体封装件的方法和制造PoP半导体装置的方法
KR101712459B1 (ko) 적층 패키지의 제조 방법, 및 이에 의하여 제조된 적층 패키지의 실장 방법
US9633966B2 (en) Stacked semiconductor package and manufacturing method thereof
US20200075494A1 (en) Through-holes of a semiconductor chip
KR101847162B1 (ko) 반도체 패키지 및 그 제조방법
US20060220245A1 (en) Flip chip package and the fabrication thereof
JP3847602B2 (ja) 積層型半導体装置及びその製造方法並びに半導体装置搭載マザーボード及び半導体装置搭載マザーボードの製造方法
USRE44500E1 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
CN102412241B (zh) 半导体芯片封装件及其制造方法
CN100539102C (zh) 电路板嵌埋有半导体芯片的电性连接结构
KR102029804B1 (ko) 패키지 온 패키지형 반도체 패키지 및 그 제조 방법
CN104051393A (zh) 具有高支护外围焊料凸块的晶片级封装器件
CN104392979A (zh) 芯片堆叠封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant