CN107293575B - 薄膜晶体管基底 - Google Patents

薄膜晶体管基底 Download PDF

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CN107293575B
CN107293575B CN201710088783.7A CN201710088783A CN107293575B CN 107293575 B CN107293575 B CN 107293575B CN 201710088783 A CN201710088783 A CN 201710088783A CN 107293575 B CN107293575 B CN 107293575B
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layer
electrode
insulating layer
gate electrode
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CN107293575A (zh
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李一正
朴永祐
李旺宇
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Samsung Display Co Ltd
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Abstract

提供一种薄膜晶体管基底，所述薄膜晶体管基底包括：基底；半导体层，设置在基底上，半导体层包括沟道区、位于沟道区的第一侧和第二侧处的源区和漏区；栅电极，设置在半导体层上；栅极绝缘层，设置在栅电极与半导体层之间；第一绝缘层，设置在基底上，第一绝缘层暴露栅电极的上表面并围绕栅电极。

Description

薄膜晶体管基底
本申请要求与2016年4月12日在韩国知识产权局提交的第10-2016-0044926号韩国专利申请的优先权，该韩国专利申请的公开通过引用全部包含于此。
技术领域
本发明涉及薄膜晶体管基底、包括该薄膜晶体管基底的显示装置及其制造方法。
背景技术
由于显示装置正被越来越多地提供有轻重量和纤薄外型，所以显示装置的使用已经多样化。随着显示装置被制造得更轻和更纤薄，期望高分辨率和大尺寸的屏幕。为了实现此点，薄膜晶体管正在小型化。然而，随着薄膜晶体管缩小，可能劣化它们的特性。
发明内容
本发明的示例性实施例提供了一种薄膜晶体管基底。薄膜晶体管基底包括：基底；半导体层，设置在基底上，半导体层包括沟道区、位于沟道区的第一侧和第二侧处的源区和漏区；栅电极，设置在半导体层上；栅极绝缘层，设置在栅电极与半导体层之间；第一绝缘层，设置在基底上。第一绝缘层暴露栅电极的上表面并围绕栅电极。
根据本发明的示例性实施例，薄膜晶体管基底还可以包括第一孔。第一孔可以在第一绝缘层中。栅电极可以设置在第一孔内。
根据本发明的示例性实施例，栅电极的上表面和第一绝缘层的上表面可以在同一平面处相遇。
根据本发明的示例性实施例，薄膜晶体管基底还可以包括第二绝缘层。第二绝缘层可以设置在栅电极的上表面和第一绝缘层的上表面上。
根据本发明的示例性实施例，薄膜晶体管基底还可以包括辅助电极。辅助电极可以设置在第二绝缘层上。辅助电极可以经由第二绝缘层中的接触孔来接触栅电极。
根据本发明的示例性实施例，薄膜晶体管基底还可以包括电极。电极可以设置在第二绝缘层上。电极可以电连接到源区和漏区中的至少一个。
根据本发明的示例性实施例，电极可以包括第一电极层。第一电极层可以接触源区或漏区中的至少一个。电极还可以包括第二电极层。第二电极层可以设置在第一电极层上。第二电极层可以接触第一电极层。
根据本发明的示例性实施例，第一电极层可以包括与栅电极相同的材料。
根据本发明的示例性实施例，薄膜晶体管基底还可以包括第二孔。第二孔可以设置在第一绝缘层中。第二孔可以暴露源区和漏区中的至少一个。第一电极层可以设置在第二孔内。
根据本发明的示例性实施例，第一绝缘层可以围绕第一电极层。第一绝缘层可以暴露第一电极层的上表面。
根据本发明的示例性实施例，第二电极层可以设置在第二绝缘层上。第二电极层可以经由第二绝缘层中的孔接触第一电极层。
根据本发明的示例性实施例，栅电极的上表面可以具有比栅电极的下表面的宽度大的宽度。
根据本发明的示例性实施例，半导体层可以在如半导体层的长度的方向的方向上具有比栅极绝缘层的长度大的长度。
本发明的示例性实施例提供了一种显示装置。显示装置包括根据本发明的示例性实施例的薄膜晶体管基底和设置在薄膜晶体管基底上的显示元件。
根据本发明的示例性实施例，显示元件可以包括有机发光二极管。
根据本发明的示例性实施例，显示元件可以包括液晶电容器。
本发明的示例性实施例提供一种制造薄膜晶体管基底的方法。制造薄膜晶体管基底的方法包括：在基底上形成半导体层，半导体层包括沟道区、位于沟道区的第一侧和第二侧处的源区和漏区；在半导体层上形成栅极绝缘层；在栅极绝缘层上形成第一初始绝缘层；在第一初始绝缘层中形成第一孔；在第一初始绝缘层上形成金属层，金属层包括填充第一孔的第一部分；去除第一初始绝缘层和金属层，其中，保留第一初始绝缘层的一部分和金属层的第一部分的至少一部分。第一初始绝缘层的剩余部分是覆盖半导体层和栅极绝缘层的第一绝缘层。金属层的第一部分的剩余部分是栅电极。
根据本发明的示例性实施例，第一绝缘层可以围绕栅电极。第一绝缘层可以暴露栅电极的上表面。
根据本发明的示例性实施例，栅极绝缘层可以通过第一孔而暴露。
根据本发明的示例性实施例，可以使用化学机械抛光来执行去除第一初始绝缘层和金属层的的步骤。
根据本发明的示例性实施例，可以使用干蚀刻来执行形成第一孔的步骤。
根据本发明的示例性实施例，栅电极的上表面和第一绝缘层的上表面可以在同一平面处相遇。
根据本发明的示例性实施例，可以使用干蚀刻来执行形成第一孔的的步骤。
根据本发明的示例性实施例，所述方法还可以包括形成第二绝缘层的步骤。第二绝缘层可以覆盖栅电极和第一绝缘层。
根据本发明的示例性实施例，所述方法还可以包括在第二绝缘层上形成辅助电极的步骤。辅助电极可以经由第二绝缘层中的孔接触栅电极。
根据本发明的示例性实施例，所述方法还可以包括在第一初始绝缘层中形成第二孔的步骤。可以通过同一工艺来执行形成第二孔的步骤和形成第一孔的步骤。
根据本发明的示例性实施例，第二孔可以暴露源区和漏区中的至少一个。金属层的第二部分可以填充第二孔。去除第一初始绝缘层和金属层的步骤可以留下金属层的第二部分的至少一部分。
根据本发明的示例性实施例，第一绝缘层可以围绕第一部分的至少一部分。第一绝缘层也可以暴露金属层的第一部分的至少一部分的上表面。
根据本发明的示例性实施例，所述方法还可以包括在第二绝缘层上形成电极层。电极层可以经由第二绝缘层中的孔接触金属层的第二部分的至少一部分。
根据本发明的示例性实施例，可以通过相同的掩模工艺来执行形成半导体层的步骤和形成栅极绝缘层的步骤。
根据本发明的示例性实施例，所述方法还可以包括对第一初始绝缘层执行湿清洗的步骤。第一孔可以设置在第一初始绝缘层中。
附图说明
通过参照附图对本发明的示例性实施例的详细描述，本发明的这些和/或其它特征将变得更加明显，在附图中：
图1是示出根据本发明的示例性实施例的薄膜晶体管基底的剖视图；
图2A至图7是示出根据本发明的示例性实施例的制造薄膜晶体管基底的方法的剖视图；
图8是示出根据对比示例的制造工艺的剖视图；
图9是示出根据本发明的示例性实施例的包括薄膜晶体管基底的显示装置的平面图；
图10是示出根据本发明的示例性实施例的一个像素区的像素的等效电路图；
图11是示出根据本发明的示例性实施例的像素的剖视图；
图12是示出根据本发明的示例性实施例的一个像素区的像素的等效电路图；
图13是示出根据本发明的示例性实施例的像素的剖视图。
具体实施方式
现在将参照附图描述本发明的示例性实施例。然而，本发明可以以许多不同的形式实施，并且不应该解释为局限于在此阐述的实施例。在附图中，同样的附图标记可以始终表示同样的元件。
如在此使用的，单数形式“一个”、“一种(者)”和“该(所述)”也意图包括复数形式，除非上下文另外明确表明。
为了解释的方便，可以夸大附图中元件的尺寸。
将理解的是，可以以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者以与描述的顺序相反的顺序执行两个连续地描述的工艺。
将理解的是，当层、区域或组件被称为“连接”到另一层、区域或组件时，该层、区域或组件可以“直接连接”到另一层、区域或组件，或者可以“间接连接”到所述另一层、区域或组件，其间插入有其它层、区域或组件。
图1是示出根据本发明的示例性实施例的薄膜晶体管(TFT)基底的剖视图。
参照图1，TFT基底可以包括基底100。TFT基底还可以包括设置在基底100上方的薄膜晶体管(TFT)TR。TFT TR可以是其中栅电极230设置在半导体层210上方的顶栅型TFT。缓冲层101可以设置在半导体层210与基底100之间。缓冲层101可以包括SiOx和/或SiNx。缓冲层101可以增大防止杂质渗透到半导体层210中。
半导体层210可以包括例如非晶硅(a-Si)或多晶硅(poly-Si)。根据本发明的示例性实施例，半导体层210可以包括铟(In)、镓(Ga)、锡(Sn)、锆(Zr)、钒(V)、铪(Hf)、镉(Cd)、锗(Ge)、铬(Cr)、钛(Ti)和锌(Zn)中的至少一种的氧化物。半导体层210可以包括沟道区210c。半导体层210还可以包括源区210s和漏区210d。源区210s和漏区210d可以分别设置在沟道区210c的任意一侧上。
栅极绝缘层103可以设置在半导体层210的沟道区210c之上。栅极绝缘层103可以包括无机材料，诸如SiOx、SiNx、SiON、氧化铝(Al2O3)、CuOx、七氧化四铽(Tb4O7)、氧化钇(III)(Y2O3)、氧化铌(V)(Nb2O5)和氧化镨(III)(Pr2O3)。栅极绝缘层103在从半导体层210的源区210s到漏区210d的第一方向上的长度L2可以比半导体层210的长度L1小。因此，栅极绝缘层103在从半导体层210的源区210s到漏区210d的第一方向上的长度L2可以与沟道区210c在同一方向上的长度基本上相同。
栅电极230可以设置在半导体层210的沟道区210c的上方，并与半导体层210的沟道区210c叠置。栅极绝缘层103可以设置在栅电极230与沟道区210c之间。栅电极230可以设置在第一孔H1中。第一孔H1可以在第一绝缘层105内部。第一绝缘层105可以设置在基底100和缓冲层101上。根据本发明的示例性实施例，栅电极230可以具有其上表面的宽度比它的下表面的宽度大的倒锥形形状。
栅电极230可以包括铜(Cu)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)和银(Ag)中的至少一种。
第一绝缘层105可以围绕栅电极230。第一绝缘层105也可以暴露栅电极230的上表面。第一绝缘层105可以包括无机绝缘材料，无机绝缘材料包括SiOx、SiNx、氧化铝(Al2O3)、CuOx、七氧化四铽(Tb4O7)、氧化钇(III)(Y2O3)、氧化铌(V)(Nb2O5)和氧化镨(III)(Pr2O3)。可选择地，第一绝缘层105可以包括至少一种有机绝缘材料，有机绝缘材料包括聚酰亚胺(PI)、聚酰胺(PA)、丙烯酸树脂、苯并环丁烯(BCB)和酚醛树脂中的一种。可选择地，第一绝缘层105可以包括多层结构。多层结构可以包括有机绝缘材料和无机绝缘材料。有机绝缘材料和无机绝缘材料可以交替地堆叠。
第一绝缘层105的上表面和栅电极230的上表面可以通过在这里描述的制造工艺而布置在竖直截面中的基本同一平面上方。第一绝缘层105和栅电极230可以通过化学机械抛光(CMP)来制造，因此，第一绝缘层105的上表面和栅电极230的上表面可以布置在基本同一平面上方。第一绝缘层105的上表面可以具有基本上均匀的粗糙度。栅电极230的上表面可以具有基本均匀的粗糙度。
可以被称为从基底100到栅电极230的上表面的第一距离的第一距离D1可以与可以被称为从基底100到第一绝缘层105的上表面的第二距离的第二距离D2基本上相同。因此，第一距离D1可以与第二距离D2基本上相同。第一距离D1与第二距离D2之差可以小于大约
Figure BDA0001228202610000061
栅电极230可以连接到辅助电极250。辅助电极250可以设置在第二绝缘层107上方。辅助电极250可以通过穿过第二绝缘层107的孔接触栅电极230的上表面。
辅助电极250可以包括铜(Cu)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)和银(Ag)中的至少一种。
半导体层210的源区210s和漏区210d中的至少一个可以连接到电极270。电极270可以包括多个电极层。例如，电极270可以包括第一电极层271和第二电极层272。
第一电极层271可以包括与栅电极230基本上相同的材料。第一电极层271的上表面可以设置在与栅电极230的上表面和第一绝缘层105的上表面基本同一平面上方。第一电极层271的上表面、第一绝缘层105的上表面以及栅电极230的上表面可以通过在这里描述的制造工艺而布置在基本同一平面上方。由于第一电极层271、第一绝缘层105和栅电极230可以通过化学机械抛光(CMP)来制造，所以第一电极层271的上表面、第一绝缘层105的上表面和栅电极230的上表面可以布置在基本同一平面上方。因此，第一电极层271的上表面、第一绝缘层105的上表面和栅电极230的上表面可以具有基本上均匀的粗糙度。
从基底100到第一电极层271的上表面的距离可以与从基底100到栅电极230的上表面的第一距离D1基本上相同。因此，从基底100到第一电极层271的上表面的距离可以与从基底100到栅电极230的上表面的第一距离D1基本上相同。该距离与第一距离D1之差可以小于大约
Figure BDA0001228202610000071
第二电极层272可以包括与辅助电极250基本上相同的材料。第二电极层272可以设置在第二绝缘层107上方。第二电极层272可以经由穿过第二绝缘层107的孔接触第一电极层271。
根据本发明的示例性实施例，栅电极230可以通过干蚀刻和化学机械抛光(CMP)来制造以具有精细的线宽。
图2A至图7是示出根据本发明的示例性实施例的制造薄膜晶体管(TFT)基底的方法的剖视图。
图2A至图2C示出了根据本发明的示例性实施例的第一掩模工艺。
参照图2A，可以在基底100上方顺序地形成半导体材料层210p'和绝缘材料层103p"。
基底100可以包括各种材料，诸如包含聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)和聚酰亚胺(PI)的塑料材料；然而，本发明的示例性实施例不限于此。
可以在基底100上方形成缓冲层101。这可以在形成半导体材料层210p'之前完成。缓冲层101可以增大防止杂质穿过基底100并渗透到半导体材料层210p'中。缓冲层101可以包括SiOx和/或SiNx。缓冲层101可以包括单层或多层。
半导体材料层210p'可以包括硅类材料，诸如非晶硅(a-Si)或多晶硅(poly-Si)。可选择地，半导体材料层210p'可以包括铟(In)、镓(Ga)、锡(Sn)、锆(Zr)、钒(V)、铪(Hf)、镉(Cd)、锗(Ge)、铬(Cr)、钛(Ti)和锌(Zn)中的至少一种的氧化物。
绝缘材料层103p"可以包括无机材料，诸如SiOx、SiNx、SiON、氧化铝(Al2O3)、CuOx、七氧化四铽(Tb4O7)、氧化钇(III)(Y2O3)、氧化铌(V)(Nb2O5)和氧化镨(III)(Pr2O3)。可以使用各种沉积方法来形成绝缘材料层103p"，诸如等离子体增强化学气相沉积(PECVD)、常压化学气相沉积(APCVD)和低压化学气相沉积(LPCVD)；然而，本发明的示例性实施例不限于此。
可以在绝缘材料层103p"上方涂覆诸如光致抗蚀剂的光敏材料。可以通过预烘烤或软烘烤来形成已经从中除去了溶剂的光致抗蚀剂层PR。为了使光致抗蚀剂层PR图案化，可以使用半色调掩模(half-tone mask)M。半色调掩模M可以具有预定的图案，并且可以在基底100上方对准。可以对光致抗蚀剂层PR执行对照射的在预定波长带中的光的暴露。
半色调掩模M可以包括光透射部M11、光阻挡部M12和半透射部M13。光透射部M11可以透射在预定的波长带中的光，光阻挡部M12可以阻挡照射的光，半透射部M13可以仅透射照射光的一部分。
图2B示出了在执行去除光致抗蚀剂层PR的曝光部分的显影工艺之后剩下的第一光致抗蚀剂图案PR1。
参照图2A和图2B，可以通过使用第一光致抗蚀剂图案PR1作为掩模使绝缘材料层103p"和半导体材料层210p'图案化来形成图案化的绝缘材料层103p'和半导体层210。
参照图2A至图2C，可以通过灰化来去除第一光致抗蚀剂图案PR1的与半透射部M13对应的部分。可以通过灰化来减小第一光致抗蚀剂图案PR1的与光阻挡部M12对应的部分的厚度。因此，可以形成第二光致抗蚀剂图案PR2。
可以通过使用第二光致抗蚀剂图案PR2作为掩模使图案化的绝缘材料层103p'图案化来形成栅极绝缘层103。栅极绝缘层103的长度L2可以小于半导体层210的长度L1。
可以使用第二光致抗蚀剂图案PR2作为掩模来掺杂半导体层210或等离子体处理半导体层210。根据本发明的示例性实施例，当半导体层210包括硅类材料时，可以通过使用第二光致抗蚀剂图案PR2作为掩模来用杂质掺杂半导体层210。半导体层210的被第二光致抗蚀剂图案PR2掩盖的非掺杂区可以成为沟道区210c。掺杂区可以分别成为源区210s和漏区210d。根据本发明的示例性实施例，当半导体层210包括氧化物时，可以通过使用第二光致抗蚀剂图案PR2作为掩模执行等离子体工艺使半导体层210成为导体。半导体层210的被第二光致抗蚀剂图案PR2掩盖的未处理区域可以成为沟道区210c。导电区域可以分别成为源区210s和漏区210d。
然后，可以去除第二光致抗蚀剂图案PR2。
图3示出了根据本发明的示例性实施例的第二掩模工艺。
参照图3，可以在半导体层210和栅极绝缘层103上方形成第一初始绝缘层105p。可以通过使用掩模来形成第一孔H1和第二孔H2。根据本发明的示例性实施例，第一孔H1和第二孔H2可以具有宽度朝向其上部增大的倒锥形形状；然而，本发明的示例性实施例不限于此。
第一初始绝缘层105p可以包括无机绝缘材料，无机绝缘材料包括SiOx、SiNx、氧化铝(Al2O3)、CuOx、七氧化四铽(Tb4O7)、氧化钇(III)(Y2O3)、氧化铌(V)(Nb2O5)和氧化镨(III)(Pr2O3)。可选择地，第一初始绝缘层105p可以包括至少一种有机绝缘材料，有机绝缘材料包括聚酰亚胺(PI)、聚酰胺(PA)、丙烯酸树脂、苯并环丁烯(BCB)和酚醛树脂中的一种。可选择地，第一初始绝缘层105p可以包括包含有机绝缘材料和无机绝缘材料的多层结构。有机绝缘材料和无机绝缘材料可以交替地堆叠。
第一孔H1可以与沟道区210c叠置并暴露栅极绝缘层103。第二孔H2可以暴露半导体层210的源区210s和漏区210d中的至少一个。
可以通过干蚀刻形成第一孔H1和第二孔H2。可以使用各向同性或各向异性干蚀刻。可以将栅电极230设置在第一孔H1内。可以由第一孔H1的宽度W1来确定栅电极230的线宽。例如，第一孔H1的宽度W1可以是栅电极230的线宽。如果通过湿蚀刻形成第一孔H1，则会发生底切。此外，会难以执行精细蚀刻，并且制造适合于高分辨率显示装置的TFT TR会变得无法获得。然而，在根据本发明的示例性实施例的蚀刻工艺中，由于第一孔H1可以通过干蚀刻形成，所以可以调节第一孔H1的宽度W1或将形成在第一孔H1内的栅电极230的精细线宽。
可以对包括第一孔H1和第二孔H2的第一初始绝缘层105p执行湿清洗(wetwashing)工艺。湿清洗工艺可以使用缓冲氧化蚀刻剂(BOE)。
图4和图5示出了根据本发明的示例性实施例的形成栅电极230的工艺。
参照图4，可以在第一初始绝缘层105p上方形成金属层ML。金属层ML可以包括铜(Cu)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)、锂(Li)、钙(Ca)、钼(Mo)、钛(Ti)、钨(W)和银(Ag)中的至少一种。金属层ML可以基本上完全地形成在第一初始绝缘层105p上方。金属层ML的第一部分ML1可以填充第一孔H1。金属层ML的第二部分ML2可以填充第二孔H2。
参照图5，可以去除第一初始绝缘层105p的一部分和金属层ML的一部分。可以通过诸如化学机械抛光(CMP)的抛光工艺来基本上同时地去除第一初始绝缘层105p的一部分和金属层ML的一部分。
通过化学机械抛光(CMP)，金属层ML的第一孔H1内的第一部分ML1的至少一部分可以保留并且可以成为栅电极230。第一初始绝缘层105p的剩余部分可以成为第一绝缘层105。金属层ML的第二孔H2内的第二部分ML2的至少一部分可以保留并且可以成为第一电极层271。第一绝缘层105可以具有比第一初始绝缘层105p的厚度T1小的厚度T2。
可以通过化学机械抛光(CMP)工艺将栅极电极230的上表面和第一绝缘层105的上表面布置在基本同一平面上方。例如，栅电极230的上表面和第一绝缘层105的上表面可以具有基本均匀的粗糙度。栅电极230的上表面和第一绝缘层105的上表面可以位于基本同一平面的上方。此外，从基底100到栅电极230的上表面的第一距离D1可以与从基底100到第一绝缘层105的上表面的第二距离D2基本相同。
由于栅电极230可以设置在第一绝缘层105中的第一孔H1内，并且可以直接接触第一绝缘层105的围绕第一孔H1的侧表面，所以栅电极230的线宽W2可以与第一孔H1的宽度W1基本相同。
由于第一电极层271可以在与栅电极230基本相同的工艺期间形成，所以第一电极层271的上表面可以布置在与栅电极230的上表面和第一绝缘层105的上表面基本同一平面的上方。例如，第一电极层271的上表面、栅电极230的上表面和第一绝缘层105的上表面可以具有基本均匀的粗糙度，并可以布置在基本同一平面的上方。因此，从基底100到第一电极层271的距离可以与第一距离D1基本上相同。
图6示出了根据本发明的示例性实施例的第三掩模工艺。
参照图6，可以形成覆盖栅电极230、第一电极层271和第一绝缘层105的第二绝缘层107，可以通过利用掩模来形成第三孔H3和第四孔H4。
第二绝缘层107可以包括无机绝缘材料，无机绝缘材料包括SiOx、SiNx、氧化铝(Al2O3)、CuOx、七氧化四铽(Tb4O7)、氧化钇(III)(Y2O3)、氧化铌(V)(Nb2O5)和氧化镨(III)(Pr2O3)中的至少一种。可选择地，第二绝缘层107可以包括至少一种有机绝缘材料，有机绝缘材料包括聚酰亚胺(PI)、聚酰胺(PA)、丙烯酸树脂、苯并环丁烯(BCB)和苯酚树脂中的一种。可选择地，第二绝缘层107可以包括其中可以交替地堆叠有有机绝缘材料和无机绝缘材料的多层结构。
第三孔H3可以暴露栅电极230。可以通过干蚀刻形成第三孔H3。第四孔H4可以暴露第一电极层271。可以通过干蚀刻形成第四孔H4。
图7示出了根据本发明的示例性实施例的第四掩模工艺。
参照图7，可以通过在第二绝缘层107上方形成金属层并使金属层图案化来形成辅助电极250和第二电极层272。
辅助电极250可以通过接触栅电极230的上表面电连接到栅电极230。第二电极层272可以通过接触第一电极层271电连接到第一电极层271。第一电极层271和第二电极层272可以通过彼此接触来构造电极270。
图8是示出根据对比示例的制造工艺的剖视图。
参照图8，在通过在半导体层21上方形成金属层并经由湿蚀刻使金属层图案化来形成栅电极23之后，使用栅电极23作为掩模，通过用杂质掺杂半导体层21，在作为非掺杂区的沟道区21c的两侧处形成源区21s和漏区21d。形成了包括暴露栅电极23的第一通孔TH1和分别暴露源区21s和漏区21d的第二通孔TH2的层间绝缘层104。通过在层间绝缘层104上方形成金属层并使金属层图案化来形成辅助电极25和电极27。
在形成金属层之前，可以通过缓冲氧化蚀刻剂(BOE)来清洗经由第二通孔TH2暴露的半导体层21的源区21s和漏区21d。缓冲氧化蚀刻剂(BOE)可以包括氟化氢(HF)。缓冲氧化蚀刻剂(BOE)会损坏金属。因此，缓冲氧化蚀刻剂(BOE)会损坏经由第一通孔TH1暴露的栅电极23。例如，缓冲氧化蚀刻剂(BOE)使包括铝(Al)或铜(Cu)的栅电极23的耐化学特性劣化，使得会劣化TFT TR'的驱动特性。尽管栅电极23可以包括氮化钛(TiN)和其它化合物，但是由于在形成氮化钛(TiN)的溅射工艺期间产生的颗粒会劣化TFT TR'的特性。
然而，根据如参照图2A至图7描述的本发明的示例性实施例，由于可以在形成栅电极230之前执行湿清洗工艺，所以可以防止栅电极230被缓冲氧化蚀刻剂(BOE)损坏。此外，可以不考虑形成栅电极230的金属类型地形成TFT TR。
如图8中所示，当通过形成金属层并使金属层图案化来形成栅电极23时，会通过湿蚀刻来执行图案化工艺。由于通过湿蚀刻形成栅电极23，因此会发生底切，会难以精细地调节线宽。
然而，根据如参照图2A至图7描述的本发明的示例性实施例，通过经由干蚀刻在第一初始绝缘层105p中形成第一孔H1，金属可以填充第一孔H1。也可以通过化学机械抛光(CMP)来形成栅电极230。因此，能够精细地调节栅电极230的线宽而不考虑形成栅电极230的金属类型。
图9是根据本发明的示例性实施例的包括薄膜晶体管(TFT)基底的显示装置1的平面图。
参照图9，显示装置1可以包括动作区(active area)AA和死区(dead area)DA。死区DA可以围绕动作区AA。动作区AA可以包括像素区PA。可以向基本上每个像素区PA提供像素。根据本发明的示例性实施例，显示装置1可以是有机发光显示装置；然而，本发明的示例性实施例不限于此。基本上每个像素区PA可以包括像素电路和有机发光二极管(OLED)。有机发光二极管(OLED)可以连接到像素电路。
图10是根据本发明的示例性实施例的像素区的像素的等效电路图。图11是根据本发明的示例性实施例的像素的剖视图。
参照图10，基本上每个像素PX可以包括第一薄膜晶体管(TFT)TR1，第二薄膜晶体管(TFT)TR2，存储电容器Cst和有机发光二极管OLED。有机发光二极管OLED可以通过使用驱动电流Ioled来发射预定亮度的光。
第一TFT TR1可以响应于施加到第i条栅极线GLi的栅极信号而输出施加到第j条数据线DLj的数据信号。第二TFT TR2可以响应于存储在存储电容器Cst中的电荷量来控制流经有机发光二极管OLED的驱动电流。像素PX可以接收第一电压ELVDD和第二电压ELVSS。第一电压ELVDD和第二电压ELVSS可以分别具有不同的电压电平。存储电容器Cst的电极可以连接到电源线PL。
参照图11，第二TFT TR2可以与参照图1至图7描述的TFT TR基本上相同。
根据本发明的示例性实施例，辅助电极250可以连接到第二TFT TR2的栅电极230。辅助电极250可以用作桥接布线(bridge wiring)，并且可以将第二TFT TR2连接到另一个TFT(例如，第一TFT TR1)。可选择地，辅助电极250可以用作桥接布线，并且可以将第二TFTTR2连接到其它电气元件，诸如存储电容器Cst。连接到第二TFT TR2的源区210s的电极270可以连接到电源线PL。连接到漏区210d的电极270可以连接到有机发光二极管OLED的像素电极310。像素电极310可以经由形成在平坦化层109中的孔而连接到第二TFT TR2。
有机发光二极管OLED的像素电极310可以从第二TFT TR2接收与第一电压ELVDD对应的电压。有机发光二极管OLED的对向电极330可以接收第二电压ELVSS。因此，有机发光二极管OLED可以发射光。有机发光二极管OLED的发射层320可以设置在像素电极310和对向电极330之间。发射层320可以经由像素限定层110暴露。发射层320可以发射预定的光。
尽管图11示出了与参照图1至图7所描述的TFT TR基本上相同的第二TFT TR2，但是本发明的示例性实施例不限于此。根据本发明的示例性实施例，第一TFT TR1可以具有与参照图1至图7所描述的TFT TR基本上相同的结构。TFT TR1也可以通过基本上相同的工艺来形成。尽管如参照图9至图11所描述的显示装置可以是有机发光显示装置，但是本发明的示例性实施例不限于此。根据本发明的示例性实施例，显示装置可以是液晶显示装置。
图12是根据本发明的示例性实施例的一个像素区的像素的等效电路图。图13是根据本发明的示例性实施例的一个像素的剖视图。根据图12和图13中示出的本发明的示例性实施例的显示装置可以是液晶显示装置；然而，本发明的示例性实施例不限于此。
参照图12，基本每个像素PX可以包括TFT TR3、存储电容器Cst和液晶电容器Clc。液晶电容器Clc可以是显示元件。存储电容器Cst可以并联连接到液晶电容器Clc。
TFT TR3可以连接到栅极线GLi和数据线DLj。TFT TR3可以响应于施加到栅极线GLi的栅极信号而输出施加到数据线DLj的数据信号。液晶电容器Clc可以使用与数据信号对应的电压来进行充电。
参照图13，TFT TR3可以与参照图1至图7所描述的TFT TR基本上相同。
液晶电容器Clc可以包括设置在第一电极410与第二电极420之间的液晶层LC。例如，液晶电容器Clc的第一电极410可以经由穿过平坦化层109的孔而连接到TFT TR3。第二电极420可以设置在上基底500下方；然而，本发明的示例性实施例不限于此。上基底500可以包括滤色器CF和黑矩阵BM。根据本发明的示例性实施例，第一电极410和第二电极420可以设置在基底100上方。
在本发明的示例性实施例中，TFT基底可以包括如图1中所示出的TFT或TFT TR已经形成在基底100上方的情况。TFT基底可以包括如图11和图13中所示出的平坦化层109已经形成在TFT TR2和TFT TR3上方的情况。此外，TFT基底可以包括像素电极310和410已经形成在TFT TR2和TFT TR3上方的情况。
尽管已经参照本发明的示例性实施例具体地示出并描述了本发明，但是本领域普通技术人员将理解的是，在不脱离由权利要求限定的发明构思的精神和范围的情况下，可以在其中在形式和细节及其等同物上进行各种变化。

Claims (8)

1.一种薄膜晶体管基底，所述薄膜晶体管基底包括：
基底；
半导体层，设置在所述基底上，所述半导体层包括沟道区、位于所述沟道区的第一侧和第二侧处的源区和漏区；
栅电极，设置在所述半导体层上；
栅极绝缘层，设置在所述栅电极与所述半导体层之间；
第一绝缘层，设置在所述基底上，其中，所述第一绝缘层暴露所述栅电极的上表面并围绕所述栅电极；
第一孔，位于所述第一绝缘层中并由所述第一绝缘层的第一侧表面限定，并且具有宽度朝向所述第一孔的上部增大的形状，其中，所述栅电极设置在所述第一孔内并且与所述第一孔直接接触；
第二孔，设置在所述第一绝缘层中，并且由所述第一绝缘层的第二侧表面限定，所述第二孔暴露所述源区和所述漏区中的至少一个；
第一电极层，接触所述源区和所述漏区中的所述至少一个，其中，所述第一电极层设置在所述第二孔内，并且与所述第二孔直接接触；
第二绝缘层，设置在所述栅电极的所述上表面和所述第一绝缘层的上表面上；
辅助电极，设置在所述第二绝缘层上，其中，所述辅助电极经由所述第二绝缘层中的接触孔接触所述栅电极，并且
其中，所述第一绝缘层的厚度与所述半导体层、所述栅极绝缘层和所述栅电极的总厚度相同，
其中，所述第一绝缘层的上表面包括位于所述栅电极和所述第一电极层之间的第一部分以及与所述第一部分相对的第二部分，所述第一电极层位于所述第一部分和所述第二部分之间，并且
其中，所述第一绝缘层的所述上表面的所述第一部分和所述第二部分与所述栅电极的上表面和所述第一电极层的上表面位于同一平面，并且所述第一绝缘层的所述上表面的所述第一部分和所述第二部分与所述第一绝缘层的所述第一侧表面的上部和所述第二侧表面的上部包括相同的材料。
2.根据权利要求1所述的薄膜晶体管基底，所述薄膜晶体管基底还包括：
电极，设置在所述第二绝缘层上，
其中，所述电极电连接到所述源区和所述漏区中的至少一个。
3.根据权利要求2所述的薄膜晶体管基底，其中，所述电极包括：
所述第一电极层；
第二电极层，设置在所述第一电极层上，其中，所述第二电极层接触所述第一电极层。
4.根据权利要求3所述的薄膜晶体管基底，其中，所述第一电极层包括与所述栅电极相同的材料。
5.根据权利要求1所述的薄膜晶体管基底，其中，所述第一绝缘层围绕所述第一电极层，并且暴露所述第一电极层的上表面。
6.根据权利要求3所述的薄膜晶体管基底，其中，所述第二电极层设置在所述第二绝缘层上，所述第二电极层经由所述第二绝缘层中的孔接触所述第一电极层。
7.根据权利要求1所述的薄膜晶体管基底，其中，所述栅电极的所述上表面具有比所述栅电极的下表面的宽度大的宽度。
8.根据权利要求1所述的薄膜晶体管基底，其中，所述半导体层在第一方向上的长度比所述栅极绝缘层在所述第一方向上的长度大。
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