CN107204360A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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CN107204360A
CN107204360A CN201710107383.6A CN201710107383A CN107204360A CN 107204360 A CN107204360 A CN 107204360A CN 201710107383 A CN201710107383 A CN 201710107383A CN 107204360 A CN107204360 A CN 107204360A
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semiconductor device
protection ring
field plate
tungsten
semiconductor substrate
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田中裕之
大井幸多
小野泽勇
小野泽勇一
伊仓巧裕
杉村和俊
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to CN202310322912.XA priority Critical patent/CN116247075A/zh
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Abstract

本发明提供容易微细加工的保护环部。还提供一种半导体装置，具备：半导体基板；有源区，其形成于半导体基板；以及保护环部，其在半导体基板形成于有源区的外侧，保护环部具有：保护环，其呈环状地形成在半导体基板的上表面；层间绝缘膜，其形成于保护环的上方；场板，其沿着保护环在层间绝缘膜的上方形成为环状；以及钨插塞，其沿着保护环形成为环状，贯穿层间绝缘膜而将保护环与场板连接。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
以往，已知在半导体元件的外周部设有保护环结构的装置(例如，专利文献1)。由此，提高关断时的耐压性。
专利文献1：日本特开2010-267655号公报
发明内容
提供一种微细加工容易的保护环结构。
在本发明的第一方式中，提供一种半导体装置。半导体装置可以具备半导体基板。半导体装置可以具备形成于半导体基板的有源区。半导体装置可以具备在半导体基板形成于有源区的外侧的保护环部。保护环部可以具有形成于半导体基板的上表面的保护环。保护环可以形成为环状。保护环部可以具有形成于保护环的上方的层间绝缘膜。保护环部可以具有形成于层间绝缘膜的上方的场板。场板可以沿着保护环形成为环状。保护环部可以具有贯穿层间绝缘膜而将保护环与场板连接的钨插塞。钨插塞沿着保护环可以形成为环状。
场板可以由钨形成。在对应的保护环和场板之间可以形成有多根环状的钨插塞。保护环部可以具有将相邻的2个钨插塞连接的连接插塞。在多根环状的钨插塞中，相邻的2个钨插塞之间的距离可以比1个钨插塞的宽度大。
半导体装置可以具备设置于有源区的上方的元件电极。元件电极可以由含有铝的材料形成。半导体装置可以具备形成在元件电极上的镀层。半导体装置可以具备形成在镀层上的保护膜。保护膜可以使镀层的一部分区域露出。
半导体装置可以具备形成于有源区的半导体元件部。半导体装置可以具备以在半导体元件部和保护环部之间贯穿层间绝缘膜的方式设置的空穴吸引插塞。空穴吸引插塞可以由钨形成。
半导体装置可以具备设置于有源区的上方的元件电极。场板可以由与元件电极相同的材料形成。
在本发明的第二方式中，提供一种半导体装置的制造方法。制造方法可以包括将保护环呈环状地形成在半导体基板的上表面的保护环形成步骤。制造方法可以包括在保护环的上方形成层间绝缘膜的绝缘膜形成步骤。制造方法可以包括形成沿着保护环设置成环状且贯穿层间绝缘膜的钨插塞的步骤。制造方法可以包括形成沿着保护环在层间绝缘膜的上方设置成环状且与钨插塞连接的场板的场板形成步骤。
制造方法可以包括在半导体基板的上表面，在被保护环包围的有源区形成元件电极的元件电极形成步骤。元件电极可以由含有铝的材料形成。制造方法可以包括在元件电极形成步骤和场板形成步骤之后对半导体基板的上表面侧进行镀覆而在元件电极上形成镀层的镀覆步骤。制造方法可以包括在半导体基板的上表面侧形成保护膜的保护膜形成步骤。
应予说明，上述的发明内容未列举本发明的所有特征。另外，这些特征群的子组合也能够成为发明。
附图说明
图1是表示本发明的一个实施方式的半导体装置100的概要的俯视图。
图2是表示半导体装置100的截面的一个例子的图。
图3是表示半导体装置100的另一结构例的截面图。
图4是钨插塞56附近的放大截面图。
图5是表示半导体基板10的上表面的钨插塞56的形状例的图。
图6A是表示半导体装置100的截面的另一例的图。
图6B是表示图6A中示出的半导体装置100的上表面的一个例子的图。
图7是放大了发射极20的附近而得到的截面图。
图8A是放大了发射极20的附近的另一例而得到的截面图。
图8B是将图8A的导线42更换成引线框43的例子。
图9是表示半导体装置100的制造方法的一个例子的图。
符号说明
10：半导体基板
11：有源区
12：层间绝缘膜
13：半导体元件部
14：栅极结构
16：漂移区
17：蓄积区
18：基极区
19：阱区
20：发射极电极
21：衬垫
22：发射极区
24：集电极区
26：集电极电极
30：连接部
32：基底电极
34：空穴吸引插塞
35：连接插塞
36：镀层
38：保护膜
40：焊料部
42：导线
43：引线框
44：三重点
50：保护环部
52：场板
54：保护环
56：钨插塞
58：连接插塞
100：半导体装置
具体实施方式
以下，通过发明的实施方式说明本发明，但以下的实施方式不限定权利要求的发明。另外，实施方式中说明的特征的组合的全部并不限定为发明的解决方案所必须的。
图1是表示本发明的一个实施方式的半导体装置100的概要的俯视图。半导体装置100具备硅或化合物半导体等的半导体基板10。在半导体基板10设有有源区11、衬垫21和1个以上的保护环部50。
在有源区11形成有IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极型晶体管)、功率MOSFET、回流二极管等半导体元件。衬垫21形成于有源区11内或者与有源区11邻接的区域。例如衬垫21与形成于有源区11的半导体元件的栅极电极电连接。
1个以上的保护环部50在半导体基板10的上表面形成于有源区11的外侧。在本例中，各保护环部50以包围有源区11的方式形成为同心状。
至少一个保护环部50具有沿着保护环部50形成为环状的钨插塞(Tungsten plug)56。在本例中，在各保护环部50分别设有2根钨插塞56。
图2是表示半导体装置100的截面的一个例子的图。在图2中，示出有源区11和保护环部50的边界附近的局部截面图。在图2中，示出一个保护环部50，但在半导体装置100中，可以在半导体基板10的上表面呈同心状地形成有多个保护环部50。本例中的半导体装置100在有源区11具有IGBT。在半导体基板10形成有漂移区16。漂移区16具有N-型的导电型。应予说明，各层或各区域的导电型也可以相反。
在漂移区16下形成有P+型的集电极区24。在集电极区24下形成有集电极电极26。在有源区11中，在漂移区16上形成有P型的基极区18。基极区18可以与形成于有源区11的外侧的P+型的阱区19连接。在基极区18上形成有N+型的发射极区22。
在半导体基板10的上表面形成有贯穿发射极区22和基极区18的多个栅极结构14。各栅极结构14在贯穿发射极区22和基极区18的沟槽内具有栅极绝缘膜和栅极电极。栅极绝缘膜以覆盖沟槽内壁的方式形成。栅极电极在沟槽内被栅极绝缘膜包覆。栅极电极至少形成在与基极区18相对的范围。如果对栅极电极施加预定的导通电压，则在与栅极电极相对的基极区18形成沟道。
半导体基板10的上表面被层间绝缘膜12覆盖。在有源区11中，在层间绝缘膜12上形成有作为元件电极的一个例子的发射极电极20。发射极电极20通过以贯穿层间绝缘膜12的方式设置的连接部30与发射极区22电连接。
连接部30可以是由钨形成的插塞。由此，能够以微细的间距设置连接部30，能够使半导体装置100微细化。
保护环部50具有保护环54、层间绝缘膜12、场板52和钨插塞56。保护环54是以与半导体基板10的上表面接触的方式形成在半导体基板10内的P+型的区域。保护环54以包围有源区11的方式呈环状地形成在半导体基板10的上表面。通过设置保护环54，能够在关断时使在半导体基板10的上表面侧产生的耗尽层延伸到有源区11的外侧。由此，抑制电场集中到有源区11的端部，使耐压性提高。
在保护环部50中，层间绝缘膜12形成在保护环54的上方。层间绝缘膜12例如是场氧化膜。场板52以与保护环54相对的方式设置于层间绝缘膜12的上方。
场板52以沿着保护环54的方式形成为环状。在与半导体基板10的上表面平行的面中，场板52的至少一个端边以比保护环54的端边突出的方式设置。通过对场板52施加电压，能够控制在半导体基板10的上表面侧产生的耗尽层的扩展。
钨插塞56贯穿层间绝缘膜12而将场板52与保护环54电连接。钨插塞56可以通过与连接部30的同一工序形成。
钨插塞56以沿着保护环54的方式形成为环状。通过呈环状连续地形成钨插塞56，与分散地设置钨插塞56的情况相比，能够提高保护环54和场板52的电连接的可靠性。另外，能够对整个保护环54施加均等的电位。
在本例中，对于一组场板52和保护环54形成有2个以上的钨插塞56。2个以上的钨插塞56在半导体基板10的上表面呈同心状地配置。另外，各钨插塞56也可以沿下述矩形配置，该矩形是4个角为圆弧状、用直线连接相邻的4个角并且使角变圆了的矩形。通过设置2个以上的钨插塞56，能够进一步提高场板52和保护环54的电连接的可靠性。另外，能够使保护环54中的电位分布变得均等。
另外，在通过蚀刻形成钨插塞56时，如果增大钨插塞56的直径或宽度，则在蚀刻时钨插塞56也会被除去。如本例所示，通过设置多个直径小的或宽度窄的钨插塞56，能够容易地形成钨插塞56，并且能够增加与场板52和保护环54的接触面积。
场板52可以由钨形成。此时，场板52的表面被自然氧化而成为WO3。由此，与使用铝等的情况相比，耐蚀性提高。
应予说明，场板52可以与钨插塞56一体地形成。例如，在层间绝缘膜12形成插塞用的开口之后，在层间绝缘膜12上形成钨膜。并且，根据场板52的形状，通过光刻法等使钨膜图案化。由此，能够用同一工序形成钨插塞56和场板52。
另外，优选在有源区11形成栅极结构14等且在层间绝缘膜12设置了插塞用的开口之后，形成场板52。作为比较例，在由多晶硅形成场板的情况下，为了不增加工序数，有时用同一工序形成栅极结构14的多晶硅电极和场板。此时，在形成了场板之后形成层间绝缘膜和插塞用的开口。
但是，在形成了场板之后形成层间绝缘膜和开口的情况下，由于场板的高低差而导致难以在场板的附近进行微细的加工。因此，在形成微细结构的有源区的情况下，必须增加场板与有源区之间的间隔，芯片尺寸会增大。
相对于此，通过在设置了层间绝缘膜12和开口之后形成场板52，能够在有源区11的附近形成场板52。因此，能够缩小芯片尺寸。
优选用同一工序形成场板52、钨插塞56和连接部30。由此，能够缩短制造工序。然而，场板52的材质不限于钨。场板52可以由与发射极电极20相同的材料形成，也可以由其它材料形成。
图3是表示半导体装置100的另一结构例的截面图。本例的半导体装置100相对于图2中示出的半导体装置100还具备基底电极32。其它结构与图2中示出的半导体装置100相同。在本例中，基底电极32、场板52和连接部30由钨形成。
基底电极32设置在发射极电极20与层间绝缘膜12之间。优选基底电极32通过与场板52的同一工序形成。
图4是钨插塞56附近的放大截面图。相邻的2个钨插塞56的距离L1可以比1根钨插塞56的宽度L2大。作为一个例子，一个钨插塞56的宽度L2为0.4μm以上且0.6μm以下。另外，钨插塞56的距离L1为0.8μm以上且1.2μm以下。
如果使距离L1比宽度L2大，则被夹在相邻的钨插塞56之间的层间绝缘膜12的形状稳定，可抑制钨插塞56的形成不良。因此，接触电阻稳定，元件耐压性和/或在未流动电流的关断状态下的泄漏电流等电特性的长期可靠性提高。另外，即便使钨插塞56为如条纹状或环状那样在长度较长方向的长度比较大的形状，也能够抑制钨插塞56的形状的溃散。钨插塞56的高度L3可以是与宽度L2相同的程度，或者可以比宽度L2短。或者，高度L3可以为宽度L2的70％以上，也可以为80％以上。由此，能够没有空隙地将钨埋入到形成于层间绝缘膜12的槽中。
图5是表示半导体基板10的上表面的钨插塞56的形状例的图。保护环部50还可以具有将相邻的2个钨插塞56连接的连接插塞58。连接插塞58由导电材料形成。由此，能够使相邻的2个钨插塞56中的电位分布变得均等。
连接插塞58在设置成环状的钨插塞56的环绕方向可以分散地设有多个。由此，即使在因制造偏差等而导致钨插塞56在环绕方向断开的情况下，也能够使钨插塞56中的电位分布变得均等。
连接插塞58可以形成到与钨插塞56相同的深度。连接插塞58可以由钨形成。连接插塞58可以通过与钨插塞56的同一工序形成。
图6A是表示半导体装置100的截面的另一例的图。本例的半导体装置100除了图2中示出的半导体装置100的构成以外，还具备1个以上的空穴吸引插塞34。
空穴吸引插塞34由钨形成。空穴吸引插塞34在形成有栅极结构14和发射极区22等的半导体元件部13与保护环部50之间贯穿层间绝缘膜12。空穴吸引插塞34将发射极电极20与阱区19电连接。
通过如上的构成，能够在半导体元件部13与保护环部50之间有效地吸引空穴。因此，能够使半导体元件部13的工作高速化。另外，由于由钨形成空穴吸引插塞34，所以即使在半导体元件部13与保护环部50之间的距离短的微细结构中，也能够容易地形成空穴吸引插塞34。
空穴吸引插塞34可以以包围半导体元件部13的方式形成为环状，也可以分散地形成在半导体元件部13的周围。另外，可以以包围半导体元件部13的方式呈同心状地形成有多个空穴吸引插塞34。优选空穴吸引插塞34通过与钨插塞56的同一工序形成。
图6B是表示图6A中示出的半导体装置100的上表面的一个例子的图。应予说明，图6A中示出的截面图与图6B中的A-A截面相对应。另外，图6B所示的半导体装置100具有6根空穴吸引插塞34。
在图6B中示出漂移区16、基极区18、阱区19、栅极结构14、空穴吸引插塞34、连接插塞35、钨插塞56、连接插塞58和场板52，省略其它结构。例如，如图6A所示，在形成于被夹在栅极结构14之间的区域的基极区18的上表面的至少一部分区域使发射极区22露出，但在图6B中省略。在形成于被夹在栅极结构14之间的区域的基极区18的上表面，可以沿着栅极结构14的沟槽的延伸方向交替形成发射极区22与P+型的接触区。
在本例中，各空穴吸引插塞34与栅极结构14的沟槽的延伸方向平行地配置。空穴吸引插塞34设置于在半导体装置100开关时流动空穴的区域。另外，连接插塞35将相邻的2个空穴吸引插塞34连接。对于连接插塞35而言，可以在相邻的2个空穴吸引插塞34之间，在空穴吸引插塞34的延伸方向分散地设有多个。由此，能够消除空穴吸引插塞34之间的电流不平衡，能够提高关断耐量。
相邻的空穴吸引插塞34之间的长度(即，相邻的空穴吸引插塞34之间的距离)可以比半导体元件部13中相邻的连接部30之间的长度(即，相邻的连接部30间的距离)短。由此，能够进一步提高关断耐量。此外，半导体元件部13在被栅极结构14的沟槽所夹的区域中，在基极区18的下方可以具备浓度比漂移区16的浓度高的N型的蓄积区17。另外，可以在空穴吸引插塞34的下方不具备N型的蓄积区17。由此，能够进一步降低导通电压，并且进一步提高关断耐量。
应予说明，如图5所示，可以形成连接2个以上的环状的钨插塞56的连接插塞58。另外，在栅极结构14的沟槽与多个空穴吸引插塞34之间也可以设有连接部30。连接部30连接到基极区18。该连接部30与相邻的空穴吸引插塞34可以通过连接插塞35连接。
图7是放大了发射极电极20的附近而得到的截面图。本例的半导体装置100还具有镀层36、保护膜38、焊料部40和导线42。镀层36形成在发射极电极20上。
镀层36例如含有镍，利用化学镀等方法形成。镀层36形成在发射极电极20的整个上表面。镀层36可以比发射极电极20厚，也可以比发射极电极20薄。为了防止镍的氧化，可以在镍表面形成置换Au(金)镀层。
发射极20由比场板52更容易镀覆的材料形成。例如发射极电极20由铝或含有铝的合金形成。作为一个例子，发射极电极20由AlSi合金形成。另外，本例中的场板52由钨或含有钨的合金形成。由于钨是稳定的材料，所以即使利用预处理除去钨表面的氧化被膜而使表面有源化，在有源化后的水洗中氧化膜也会迅速形成。因此，难以在场板52的表面形成镀层。
保护膜38在形成镀层36之后形成于半导体基板10的整个上方。然而，保护膜38在镀层36上覆盖镀层36的一部分区域。以使镀层36的一部分区域露出的方式在保护膜38形成开口。保护膜38例如由聚酰亚胺形成。保护膜38也可以形成在场板52上。
焊料部40形成在保护膜38的开口部分，将导线42与镀层36电连接。在本例中，由于场板52由钨等形成，所以在形成镀层36的情况下，即使不用保护膜等覆盖场板52，也能够在发射极电极20选择性地形成镀层36。并且，由于在形成镀层36之后形成保护膜38和开口，所以能够在镀层36上形成开口。即，由于开口的侧壁在镀层36的上表面终止，所以能够防止焊料部40等沿着开口的侧壁到达发射极电极20。由此，能够保护发射极电极20等。应予说明，保护膜38的开口、焊料部40和导线42可以分散地形成多组。
图8A是放大了发射极电极20的附近的另一例而得到的截面图。在本例中，在发射极电极20上形成有保护膜38。另外，形成于保护膜38的开口的侧壁在发射极电极20的上表面终止。在开口内形成有镀层36、焊料部40和导线42。镀层36以保护膜38为掩模而形成。图8B是将图8A的导线42更换成引线框43的例子。
在图8A和图8B的例子中，存在保护膜38、镀层36和发射极电极20的各端部重叠的三重点44。因此，焊料部40的焊料等有时穿过保护膜38的侧壁与镀层36的侧壁之间而到达发射极电极20。在图7所示出的例子中，由于不存在三重点44，所以如上所述，能够提高发射极电极20等的可靠性。应予说明，在图7的例子中，也可以将导线42更换成引线框43。
另外，在图8A和图8B所示出的例子中，由于在形成保护膜38之后形成镀层36，所以如果在高温下进行镀覆，则有可能给保护膜38造成损伤。因此，成为在低温下形成镀层36，而这样有效地形成镀层36比较困难。与此相对，在图7的例子中，能够在高温下形成镀层36。
图9是表示本发明的实施方式的半导体装置100的制造方法的一个例子的图。首先，在元件形成步骤S900中，形成半导体基板10中的各杂质区域和栅极结构14。另外，元件形成步骤S900包括形成层间绝缘膜12的绝缘膜形成步骤和形成保护环54的保护环形成步骤。
接下来，在钨形成步骤S902中，在层间绝缘膜12形成贯穿孔之后在层间绝缘膜12上沉积钨。由此，形成贯穿间绝缘膜12的钨插塞56和连接部30。另外，钨形成步骤S902包括形成场板52的场板形成步骤。在S902中，使沉积在层间绝缘膜12上的钨图案化而形成场板52。
接下来，在元件电极形成步骤S904中，利用含有铝的材料在有源区11中的半导体基板10的上表面的上方形成发射极电极20。如图3所示，也可以在基底电极32上形成发射极电极20。此时，在钨形成步骤S902中形成基底电极32。
接着，在镀覆步骤S906中，在半导体基板10的上表面侧形成镀层36。此时，也可以不形成覆盖场板52的掩模。通过镀覆步骤S906，在发射极电极20的上表面选择性地形成镀层36。
接下来，在基板厚度调整步骤S908中，根据预定的耐压性磨削半导体基板10的下表面侧，调整半导体基板10的厚度。接下来，在保护膜形成步骤S910中，在半导体基板10的上表面侧形成保护膜38。保护膜38的形成也可以在基板厚度的调整之前进行。
接着，在下表面电极形成步骤S912中，在半导体基板10的下表面形成集电极电极等。另外，在保护膜38的预定的位置形成开口，形成焊料部40和导线42。
通过如上的方法，能够制造使用了钨插塞56的半导体装置100。另外，能够制造具有图7所示出的结构的半导体装置100。
以上，使用实施方式说明了本发明，但本发明的技术的范围不限于上述实施方式中记载的范围。对上述实施方式进行各种变更或改良对于本领域技术人员而言也是明确的。根据权利要求书的记载可知其进行了各种变更或改良的方式也包括在本发明的技术方案内。
在本说明书中，“上”、“下”、“上方”、“下方”、“上表面”、“下表面”这些用语不限于重力方向的上下。这些用语表示在任意轴的相对的方向。

Claims (10)

1.一种半导体装置，其特征在于，具备：
半导体基板；
有源区，其形成于所述半导体基板；以及
保护环部，其在所述半导体基板形成于所述有源区的外侧，
所述保护环部具有：
保护环，其呈环状地形成在所述半导体基板的上表面；
层间绝缘膜，其形成于所述保护环的上方；
场板，其沿着所述保护环在所述层间绝缘膜的上方形成为环状；以及
钨插塞，其沿着所述保护环形成为环状，贯穿所述层间绝缘膜而将所述保护环与所述场板连接。
2.根据权利要求1所述的半导体装置，其特征在于，所述场板由钨形成。
3.根据权利要求1或2所述的半导体装置，其特征在于，在对应的所述保护环和所述场板之间形成有多根环状的所述钨插塞。
4.根据权利要求3所述的半导体装置，其特征在于，所述保护环部还具备将相邻的2个所述钨插塞连接的连接插塞。
5.根据权利要求3或4所述的半导体装置，其特征在于，在所述多根环状的所述钨插塞中，相邻的2个所述钨插塞之间的距离比1根所述钨插塞的宽度大。
6.根据权利要求2所述的半导体装置，其特征在于，所述半导体装置还具备：
元件电极，其设置于所述有源区的上方，且由含有铝的材料形成；
镀层，其形成在所述元件电极上；以及
保护膜，其形成在所述镀层上，且使所述镀层的一部分区域露出。
7.根据权利要求1～6中任一项所述的半导体装置，其特征在于，所述半导体装置还具备：
半导体元件部，其形成于所述有源区；以及
空穴吸引插塞，其以贯穿所述层间绝缘膜的方式设置在所述半导体元件部和所述保护环部之间，且由钨形成。
8.根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还具备设置于所述有源区的上方的元件电极，
所述场板由与所述元件电极相同的材料形成。
9.一种半导体装置的制造方法，其特征在于，包括：
保护环形成步骤，使保护环呈环状地形成在半导体基板的上表面；
绝缘膜形成步骤，在所述保护环的上方形成层间绝缘膜；以及
场板形成步骤，形成沿着所述保护环设置成环状并贯穿所述层间绝缘膜的钨插塞，并且形成沿着所述保护环在所述层间绝缘膜的上方设置成环状并与所述钨插塞连接的场板。
10.根据权利要求9所述的制造方法，其特征在于，所述半导体装置的制造方法还包括：
元件电极形成步骤，利用含有铝的材料在所述半导体基板的上表面且被所述保护环包围的有源区形成元件电极；
镀覆步骤，在所述元件电极形成步骤和所述场板形成步骤之后，对所述半导体基板的上表面侧进行镀覆而在所述元件电极上形成镀层；以及
保护膜形成步骤，在所述半导体基板的上表面侧形成保护膜。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109755293A (zh) * 2017-11-08 2019-05-14 富士电机株式会社 半导体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6854654B2 (ja) * 2017-01-26 2021-04-07 ローム株式会社 半導体装置
CN111065624B (zh) 2017-09-01 2022-07-26 Ａｇｃ株式会社 含氟磺酰基化合物、含氟磺酰基的单体及它们的制造方法
JP7028093B2 (ja) * 2017-11-08 2022-03-02 富士電機株式会社 半導体装置
JP6777245B2 (ja) 2017-11-16 2020-10-28 富士電機株式会社 半導体装置
DE102018116332B4 (de) 2018-07-05 2022-02-24 Infineon Technologies Ag Leistungshalbleitervorrichtung
US11876062B2 (en) * 2019-10-08 2024-01-16 Mitsubishi Electric Corporation Semiconductor device
WO2023286692A1 (ja) * 2021-07-14 2023-01-19 株式会社デンソー 半導体ウェハ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210350A1 (en) * 2006-03-07 2007-09-13 Kabushiki Kaisha Toshiba Power semiconductor device, method for manufacturing same, and method for driving same
CN104241347A (zh) * 2013-06-20 2014-12-24 株式会社东芝 半导体装置
CN104662667A (zh) * 2012-11-29 2015-05-27 富士电机株式会社 半导体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021526A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 電力用半導体装置及びその製造方法
US7875951B2 (en) * 2007-12-12 2011-01-25 Infineon Technologies Austria Ag Semiconductor with active component and method for manufacture
JP2010092895A (ja) * 2008-10-03 2010-04-22 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5477681B2 (ja) 2008-07-29 2014-04-23 三菱電機株式会社 半導体装置
JP5224289B2 (ja) 2009-05-12 2013-07-03 三菱電機株式会社 半導体装置
JP5606240B2 (ja) 2010-09-22 2014-10-15 三菱電機株式会社 半導体装置
JP5842415B2 (ja) * 2011-06-30 2016-01-13 トヨタ自動車株式会社 半導体装置及びその製造方法
US9412809B2 (en) * 2013-02-15 2016-08-09 Toyota Jidosha Kabushiki Kaisha Semiconductor device and manufacturing method thereof
JP2014175640A (ja) * 2013-03-13 2014-09-22 Renesas Electronics Corp 縦型複合パワーｍｏｓｆｅｔ
JP6575398B2 (ja) * 2016-03-01 2019-09-18 三菱電機株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070210350A1 (en) * 2006-03-07 2007-09-13 Kabushiki Kaisha Toshiba Power semiconductor device, method for manufacturing same, and method for driving same
CN104662667A (zh) * 2012-11-29 2015-05-27 富士电机株式会社 半导体装置
CN104241347A (zh) * 2013-06-20 2014-12-24 株式会社东芝 半导体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109755293A (zh) * 2017-11-08 2019-05-14 富士电机株式会社 半导体装置
CN109755293B (zh) * 2017-11-08 2023-11-10 富士电机株式会社 半导体装置

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