CN107134442B - 高频封装 - Google Patents

高频封装 Download PDF

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CN107134442B
CN107134442B CN201710329692.8A CN201710329692A CN107134442B CN 107134442 B CN107134442 B CN 107134442B CN 201710329692 A CN201710329692 A CN 201710329692A CN 107134442 B CN107134442 B CN 107134442B
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CN107134442A (zh
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海野友幸
稻见和喜
八十冈兴祐
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Abstract

本发明提供一种高频封装。在多层基板中,作为将所搭载的高频器件产生的高频信号从最上层向最下层传输而向基板外部输出并将从基板外部向所述最下层输入的高频信号传输到所述高频器件的结构,形成有模拟同轴线路,该模拟同轴线路将对在所述最上层的上表面形成的金属图案与在所述最下层的下表面形成的金属图案之间进行连接的上下贯通通路作为中心导体、并且将在其周围对2个以上的层间进行连接且呈环状配置的多个层间通路作为外导体,其中,使所述上下贯通通路的全部或一部分为不使用通路的使导体焊盘对置的电容器结构。

Description

高频封装
本发明申请是国际申请号为PCT/JP2012/050501,国际申请日为2012年01月12日,进入中国国家阶段的申请号为201280024505.0,名称为“高频封装”的发明专利申请的分案申请。
技术领域
本发明涉及在微波波段或毫米波波段工作的电子装置中所使用的高频封装。
背景技术
在微波波段或毫米波波段工作的电子装置中所使用的高频封装是对搭载有在微波波段或毫米波波段工作的高频器件(MMIC:单片微波集成电路)的多层基板进行封装化而成的,在该多层基板的最下层进行与外部的电连接。
因此,在构成该高频封装的多层基板上,作为将所搭载的高频器件产生的高频信号向基板外部输出并将来自基板外部的高频信号输入到高频器件的结构,在多层基板内形成有将最上层与最下层之间连通的模拟同轴线路。
该模拟同轴线路是如下结构:例如像专利文献1所公开的那样,将对与高频器件的输入输出端口连接且形成在最上层的上表面的金属图案与形成在最下层的下表面的金属图案之间进行连接的上下贯通通路(via)作为中心导体,将在其周围对2个以上的层间进行连接并呈环状配置的多个层间通路作为外导体。在最下层的下表面形成的金属图案经由BGA(球栅阵列(ball grid array))与其它的多层基板连接。
现有技术文献
专利文献
专利文献1:日本特开平6-85099号公报。
发明内容
发明要解决的课题
可是,在制造多层基板时,有时会由于热应力等而在某个层的基板产生裂缝。这样,在安装了高频器件的运用时,在该裂缝延伸到形成中心导体的上下贯通通路的形成部分的情况下,使上下贯通通路断线,因此,存在发生高频信号的通过特性较大地劣化的情况的问题。
本发明是鉴于上述问题而提出的,其目的在于得到一种利用即使裂缝以横穿模拟同轴线路的中心导体形成区域的方式产生,也能抑制高频信号的通过特性的劣化的结构的多层基板的高频封装。
用于解决课题的方案
为了解决上述的课题并达成目的,本发明提供一种利用了多层基板的高频封装,在该多层基板中,作为将所搭载的高频器件产生的高频信号从最上层向最下层传输而向基板外部输出并将从基板外部向所述最下层输入的高频信号传输到所述高频器件的结构,形成有模拟同轴线路,该模拟同轴线路将对在所述最上层的上表面形成的金属图案与在所述最下层的下表面形成的金属图案之间进行连接的上下贯通通路作为中心导体、并且将在其周围对2个以上的层间进行连接且呈环状配置的多个层间通路作为外导体,所述高频封装的特征在于,使所述上下贯通通路的全部或一部分为不使用通路的使导体焊盘对置的电容器结构。
发明效果
根据本发明,即使在内层的基板产生的裂缝延伸到形成模拟同轴线路的中心导体的区域,作为高频信号的传送路径的模拟同轴线路的结构也被电容器结构维持而继续存在,因此,起到能抑制高频信号的通过特性的劣化的效果。
附图说明
图1是示出本发明的一个实施方式的高频封装的主要部分结构的截面图。
具体实施方式
以下,基于附图详细地对本发明的高频封装的实施方式进行说明。另外,本发明并不被该实施方式所限定。
实施方式
图1是示出本发明的一个实施方式的高频封装的主要部分结构的截面图。在图1中,在构成高频封装的多层基板1上搭载有高频器件(MMIC)2。高频器件2的输入输出端口通过引线3与在多层基板1的最上层的上表面形成的微带线路4的一端连接。
此外,在多层基板1中,在最上层与最下层之间形成有模拟同轴线路5。模拟同轴线路5的中心导体由一端与微带线路3连接且另一端贯通多个内层的层间通路6和配置在层间通路6的另一端与最下层之间的电容器结构7构成。此外,模拟同轴线路5的外导体由在中心导体(层间通路6+电容器结构7)的周围对2个以上的层间进行连接并呈环状配置的多个层间通路8构成。
一般来说,嵌入在多层基板中的模拟同轴线路的中心导体由贯通最上层与最下层之间而进行连接的上下贯通通路构成,但是,在图1中示出了使该上下贯通通路的一部分为电容器结构7的情况。
在图1中,电容器结构7是在连续的三个层使导体焊盘9a、9b、9c对置的结构。导体焊盘9a与层间通路6的另一端连接,导体焊盘9b形成在最下层的下表面。导体焊盘9c配置在导体焊盘9a与导体焊盘9b之间。即,图1所示的电容器结构7是将两个电容器以串联方式配置的结构。
多层基板1的最下层隔着构成BGA的焊料球10a、10b安装在其它的多层基板11的上表面。焊料球10a将构成模拟同轴线路5的中心导体的另一端的导体焊盘9b与在其它的多层基板11的上表面形成的微带线路12之间连接。焊料球10b将构成模拟同轴线路5的外导体的层间通路8与在其它的多层基板11的上表面形成的接地导体13之间连接。
在以上的结构中,在由于制造基板时的热应力等而在多层基板1的内层产生了裂缝14的情况下,在安装了高频器件2的运用时,即使该裂缝14延伸到形成中心导体的区域,作为高频信号的传送路径的模拟同轴线路5的结构也被电容器结构7维持而继续存在,因此,能抑制高频信号的通过特性的劣化。
虽然在图1中示出了在形成电容器结构7的层的基板产生裂缝14的情况,但是,裂缝14会在内层的任意的基板产生。例如,裂缝14有时也会产生在形成有层间通路6的多个层内的任意层。在该情况下,不能利用电容器结构7进行补救,中心导体发生断线。因此,可以说优选使模拟同轴线路5的中心导体的整体为电容器结构。是在最上层与最下层之间以串联方式配置有多个电容器的结构。而且,可以说在图1中示出了能从经验上特别确定由于热应力而产生裂缝的内层的基板的情况。
像这样,根据本实施方式,即使以横穿模拟同轴线路的中心导体形成区域的方式产生裂缝,作为高频信号的传送路径的模拟同轴线路的结构也被电容器结构维持而继续存在,因此,能抑制高频信号的通过特性的劣化。
产业上的可利用性
像以上那样,本发明的高频封装作为利用即使以横穿中心导体形成区域的方式产生裂缝也能抑制高频信号的通过特性的劣化的多层基板的高频封装是有用的。
附图标记说明
1:多层基板;
2:高频器件(MMIC);
3:引线;
4、12:微带线路;
5:模拟同轴线路;
6、8:层间通路;
7:电容器结构;
9a、9b、9c:导体焊盘;
10a、10b:焊料球;
11:其它的多层基板;
13:接地导体;
14:裂缝。

Claims (1)

1.一种利用了多层基板的高频封装,在该多层基板中,作为将所搭载的高频器件产生的高频信号从最上层向最下层传输而向基板外部输出并将从基板外部向所述最下层输入的高频信号传输到所述高频器件的结构,形成有模拟同轴线路,该模拟同轴线路将对在所述最上层的上表面形成的金属图案与在所述最下层的下表面形成的最下层的导体焊盘之间进行连接的上下贯通通路作为中心导体、并且将在其周围对2个以上的层间进行连接且呈环状配置的多个层间通路作为外导体,所述高频封装的特征在于,
在构成模拟同轴线路的中心导体的层间通路连接电容器部,将模拟同轴线路的外导体与接地连接,
用焊料球将所述最下层的导体焊盘连接于其他的多层基板,
使与该焊料球连接的最下层的导体焊盘与该最下层的导体焊盘的上层的导体焊盘对置而形成电容器部,
将该电容器部中的上层的导体焊盘与构成模拟同轴线路的中心导体的层间通路连接,
所述电容器部由包括最下层的导体焊盘、其上位层的导体焊盘、以及其更上位层的导体焊盘的多个导体焊盘构成。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160192487A1 (en) * 2013-08-12 2016-06-30 Telefonaktiebolaget L M Ericsson (Publ) Via Transition and Method of Fabricating the Same
JP6107718B2 (ja) * 2014-03-20 2017-04-05 三菱電機株式会社 高周波フィルタ
US11160163B2 (en) 2017-11-17 2021-10-26 Texas Instruments Incorporated Electronic substrate having differential coaxial vias

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227177A (ja) * 2007-03-13 2008-09-25 Nec Corp インターポーザ、半導体モジュール、及びそれらの製造方法
CN101369569A (zh) * 2007-08-15 2009-02-18 奇梦达股份公司 载体衬底和集成电路

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3194445B2 (ja) * 1992-09-01 2001-07-30 新光電気工業株式会社 高周波用回路基板の信号回路
JP2000332422A (ja) 1999-05-20 2000-11-30 Sony Corp 多層回路基板及びその製造方法
US6617526B2 (en) * 2001-04-23 2003-09-09 Lockheed Martin Corporation UHF ground interconnects
JP3583396B2 (ja) * 2001-10-31 2004-11-04 富士通株式会社 半導体装置の製造方法、薄膜多層基板及びその製造方法
JP3495727B2 (ja) * 2001-11-07 2004-02-09 新光電気工業株式会社 半導体パッケージおよびその製造方法
US6711029B2 (en) * 2002-05-21 2004-03-23 Cts Corporation Low temperature co-fired ceramic with improved shrinkage control
KR20050072881A (ko) * 2004-01-07 2005-07-12 삼성전자주식회사 임피던스 정합 비아 홀을 구비하는 다층기판
KR100651414B1 (ko) * 2004-02-13 2006-11-29 삼성전기주식회사 동축 비아홀을 구비한 인쇄회로기판
JP4471281B2 (ja) 2004-09-08 2010-06-02 株式会社リコー 積層型高周波回路基板
JP2006128309A (ja) * 2004-10-27 2006-05-18 Shinko Electric Ind Co Ltd キャパシタ装置及びその製造方法
JP4575261B2 (ja) * 2005-09-14 2010-11-04 株式会社東芝 高周波用パッケージ
TWI305119B (en) * 2005-12-22 2009-01-01 Phoenix Prec Technology Corp Circuit board structure having capacitance array and embedded electronic component and method for fabricating the same
JP2006287962A (ja) * 2006-05-19 2006-10-19 Mitsubishi Electric Corp 高周波送受信モジュール
US20070278001A1 (en) * 2006-05-31 2007-12-06 Romi Mayder Method and apparatus for a high frequency coaxial through hole via in multilayer printed circuit boards
JP4990353B2 (ja) * 2007-03-14 2012-08-01 三菱電機株式会社 高周波パッケージ
JP4840935B2 (ja) * 2007-09-28 2011-12-21 双信電機株式会社 セラミック多層基板
JP2010154412A (ja) * 2008-12-26 2010-07-08 Sony Corp 配線基板および半導体装置
JP2011187812A (ja) 2010-03-10 2011-09-22 Mitsubishi Electric Corp 高周波モジュール

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227177A (ja) * 2007-03-13 2008-09-25 Nec Corp インターポーザ、半導体モジュール、及びそれらの製造方法
CN101369569A (zh) * 2007-08-15 2009-02-18 奇梦达股份公司 载体衬底和集成电路

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US9591756B2 (en) 2017-03-07
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US20140069706A1 (en) 2014-03-13
CN103563072A (zh) 2014-02-05

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