CN107104082A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN107104082A
CN107104082A CN201710041233.XA CN201710041233A CN107104082A CN 107104082 A CN107104082 A CN 107104082A CN 201710041233 A CN201710041233 A CN 201710041233A CN 107104082 A CN107104082 A CN 107104082A
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China
Prior art keywords
semiconductor chip
semiconductor
pad
package part
chip
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Pending
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CN201710041233.XA
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English (en)
Inventor
金吉洙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN107104082A publication Critical patent/CN107104082A/zh
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Abstract

可以提供一种半导体封装件，所述半导体封装件包括：安装板；第一半导体芯片，位于安装板上，第一半导体芯片具有第一外围区域、第二外围区域和位于第一外围区域与第二外围区域之间的中心区域，中心区域具有形成在其中的穿透电极；第二半导体芯片，位于第一外围区域上，第二半导体芯片包括位于其顶表面上的第二焊盘；第三半导体芯片，位于第二外围区域上，第三半导体芯片包括位于其顶表面上的第三焊盘；导电引线，分别从第二焊盘和第三焊盘延伸，导电引线分别电连接到穿透电极。

Description

半导体封装件
本申请要求于2016年2月23日在韩国知识产权局提交的第10-2016-0020908号韩国专利申请的优先权，该韩国专利申请的公开通过引用全部包含于此。
技术领域
本公开涉及半导体封装件，更具体地，涉及堆叠有多个半导体芯片的半导体封装件。
背景技术
半导体工业的目标之一是以较低的成本制造小型化、多功能的、大容量和/或高可靠性的半导体产品。半导体封装技术在实现这样的目标中发挥着重要的作用。例如，已经提出在其它半导体封装技术之中的堆叠的半导体封装件以在一个封装件中堆叠多个芯片。
随着半导体装置的集成度和存储容量增大，已经开发了用于堆叠单个芯片的三维(3D)封装。例如，已经采用了形成有穿透基底的通孔并在通孔中形成电极的硅通孔接触技术作为可代替现有的引线键合技术的一类3D封装结构。
发明内容
本公开的一些示例实施例提供了半导体芯片可高度集成到其中的半导体封装件。
本公开的一些示例实施例提供了关于半导体芯片的堆叠具有改善的自由度的半导体封装件。
本公开的一些示例实施例提供了相对易于制造的半导体封装件。
然而，本公开的示例实施例不限于在此阐述的这些。通过参照以下给出的本公开的详细的描述，对本公开所属领域的普通技术人员而言，本公开的上面和其它的示例实施例将变得更加明显。
根据本公开的示例实施例，半导体封装件包括：安装板；第一半导体芯片，位于安装板上，第一半导体芯片具有第一外围区域、第二外围区域和位于第一外围区域与第二外围区域之间的中心区域，中心区域具有形成在其中的穿透电极；第二半导体芯片，位于第一外围区域上，第二半导体芯片包括位于其顶表面上的第二焊盘；第三半导体芯片，位于第二外围区域上，第三半导体芯片包括位于其顶表面上的第三焊盘；导电引线，分别从第二焊盘和第三焊盘延伸，导电引线分别电连接到穿透电极。
根据本公开的另一个示例实施例，半导体封装件包括：安装板；第一半导体芯片，位于安装板上，第一半导体芯片包括穿透电极和第一焊盘，穿透电极位于第一半导体芯片中，第一焊盘分别位于穿透电极上；第二半导体芯片和第三半导体芯片，位于第一半导体芯片上，第二半导体芯片和第三半导体芯片彼此隔开以暴露位于其间的第一焊盘，第二半导体芯片和第三半导体芯片没有硅通孔；导电引线，电连接第一半导体芯片、第二半导体芯片和第三半导体芯片。
根据本公开的另一个示例实施例，半导体封装件包括：安装板；第一半导体芯片，位于安装板上，第一半导体芯片包括位于其中心区域处的穿透电极，穿透电极将安装板电连接到第一半导体芯片；至少一个第二半导体芯片和至少一个第三半导体芯片，位于第一半导体芯片上，第二半导体芯片包括位于其顶表面上的第二焊盘，第三半导体芯片包括位于其顶表面上的第三焊盘，第二半导体芯片和第三半导体芯片彼此隔开以暴露第一半导体芯片的中心区域；导电引线分别从第二焊盘和第三焊盘延伸；导电引线分别将第二焊盘和第三焊盘电连接到穿透电极。
通过以下的详细描述、附图和权利要求书，其它特征和方面将变得明显。
附图说明
图1是根据本公开的示例实施例的半导体封装件的剖视图。
图2是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图3是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图4是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图5是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图6是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图7是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图8是根据本公开的另一个示例实施例的半导体封装件的剖视图。
图9是示出应用根据本公开的一些示例实施例的一个或更多个半导体封装件的存储卡的示意图。
图10是应用根据本公开的一些示例实施例的一个或更多个半导体封装件的电子系统的框图。
图11是示出将图10的电子系统应用到智能电话的示例的示意性视图。
具体实施方式
在下文中将参照图1描述根据本公开的示例实施例的半导体封装件。
图1是根据本公开的示例实施例的半导体封装件的剖视图。
参照图1，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。
第一半导体芯片20可以设置在安装板10上。第二半导体芯片30和第三半导体芯片40可以设置在第一半导体芯片20上。封装成型部件60可以设置在安装板10上，并可以覆盖第一半导体芯片20、第二半导体芯片30和第三半导体芯片40。
安装板10可以是用于封装的板，例如，印刷电路板(PCB)或陶瓷基底。安装板10可以具有彼此相对的顶表面和底表面。即，第一半导体芯片20可以设置在安装板10的顶表面上，外部端子11可以形成在安装板10的底表面上以将根据本示例实施例的半导体封装件电连接到外部装置。外部端子11被示出为被设置为焊球，但是本公开不限于此。在一些示例实施例中，外部端子11可以被设置为栅格阵列(例如，引脚栅格阵列、球栅格阵列或平面栅格阵列)。
键合焊盘12可以设置在安装板10的顶表面上。键合焊盘12可以电连接到与外部装置连接的外部端子，并可以将电信号供应到第一半导体芯片20。键合焊盘12也可以将电信号供应到第二半导体芯片30和第三半导体芯片40。
至少一个键合焊盘12可以是例如接地焊盘，并可以电连接到安装板10中的接地线。键合焊盘12可以设置在例如安装板10的中心处，但是本公开不限于此。
第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以设置在安装板10上。第一半导体芯片20可以直接设置在安装板10上，第二半导体芯片30和第三半导体芯片40可以设置在第一半导体芯片20上。
第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以是例如存储器芯片或逻辑芯片。如果第一半导体芯片20、第二半导体芯片30和第三半导体芯片40是逻辑芯片，则考虑到由第一半导体芯片20、第二半导体芯片30和第三半导体芯片40执行的操作的类型，第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以以各种方式设计。逻辑芯片可以是微处理器(例如，中央处理单元(CPU)、控制器或专用集成电路(ASIC))。
第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以是存储器芯片，例如，非易失性存储器芯片。例如，存储器芯片可以是闪存芯片。更具体地，存储器芯片可以是NAND闪存芯片或NOR闪存芯片，但是本公开不限于此。即，存储器芯片的示例也可以包括相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)或电阻式随机存取存储器(RRAM)。
第一半导体芯片20可以是与第二半导体芯片30和第三半导体芯片40的类型不同的类型。例如，第一半导体芯片20可以是诸如移动CPU的逻辑芯片，第二半导体芯片30和第三半导体芯片40可以是存储器芯片(例如，动态随机存取存储器(DRAM)、宽输入/输出(I/O)DRAM、闪存或PRAM)。然而，本公开不限于该示例。
第一半导体芯片20包括穿透第一半导体芯片20的穿透电极21。第一半导体芯片20还包括形成在第一半导体芯片20的顶表面上的第一焊盘20a和形成在第一半导体芯片20的底表面上的第一端子23。第一焊盘20a和第一端子23可以通过穿透第一半导体芯片20的穿透电极21连接。图1示出了形成在第一半导体芯片20中的两个穿透电极21，但是本公开不限于此。
穿透电极21穿透第一半导体芯片20。每个穿透电极21可以具有顺序地形成有绝缘层(未示出)、种子层(未示出)和导电层(未示出)的结构。绝缘层可以使导电层电绝缘。绝缘层可以包括例如氧化物、氮化物或氮氧化物。更具体地，绝缘层可以包括例如氧化硅、氮化硅或氮氧化硅。导电层可以包括诸如金属的导电材料。形成穿透电极21的金属的示例包括例如铝(Al)、金(Au)、铍(Be)、铋(Bi)、钴(Co)、铜(Cu)、铪(Hf)、铟(In)、锰(Mn)、钼(Mo)、镍(Ni)、铅(Pb)、钯(Pd)，铂(Pt)，铑(Rh)、铼(Re)、钌(Ru)、钽(Ta)、碲(Te)、钛(Ti)、钨(W)、锌(Zn)或锆(Zr)，但是本公开不限于此。
每个穿透电极21的绝缘层、种子层和导电层可以通过化学气相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体CVD(HDP CVD)、溅射、金属有机CVD(MOCVD)或原子层沉积(ALD)来形成，但是本公开不限于此。
第一半导体芯片20可以经由形成在键合焊盘12上的第一端子23电连接到安装板10。即，第一端子23可以将第一半导体芯片20的穿透电极21与安装板10的键合焊盘12电连接。第一端子23示出为被设置为焊球，但是本公开不限于此。即，第一端子23可以被设置为作为柱和焊球的组合的焊料凸块。
例如，第一半导体芯片20可以是倒装芯片，第一端子23可以形成在形成有半导体电路器件的表面上。然而，本公开不限于该示例。第一半导体芯片20可以包括无源器件(例如，电容器、电感器或电阻器)。第一半导体芯片20可以包括静电放电(ESD)防止电路。
在第一半导体芯片20包括ESD防止电路的情况下，第二半导体芯片30和第三半导体芯片40可以形成为不包括ESD防止电路。当第二半导体芯片30和第三半导体芯片40不包括任何ESD防止电路时，根据一些示例实施例的半导体封装件可以被小型化，并可以消耗较少的电力。
在图1中，仅第一半导体芯片20被示出为包括穿透电极21，但是本公开不限于此。
第一半导体芯片20可以具有第一外围区域EA1、中心区域CA和第二外围区域EA2。中心区域CA可以设置在第一外围区域EA1与第二外围区域EA2之间。第一外围区域EA1、中心区域CA和第二外围区域EA2可以彼此连续或者可以彼此分离或隔开。第一半导体芯片20可以具有第一长度W1。
第一半导体芯片20包括形成在中心区域CA中的穿透电极21。第二半导体芯片30可以设置在第一半导体芯片20的第一外围区域EA1上。第三半导体芯片40可以设置在第一半导体芯片20的第二外围区域EA2上。因为第二半导体芯片30和第三半导体芯片40在第一半导体芯片20上方彼此隔开，所以第一半导体芯片20的中心区域CA的顶表面可以被暴露。另外，第一半导体芯片20的第一焊盘20a可以在第二半导体芯片30与第三半导体芯片40之间被暴露。
再次参照图1，第二半导体芯片30的部分可以在第一半导体芯片20上方被暴露。即，第二半导体芯片30的部分可以不与第一半导体芯片20叠置。另外，第三半导体芯片40的部分可以在第一半导体芯片20上方被暴露。即，第三半导体芯片40的部分可以不与第一半导体芯片20叠置。
与第一半导体芯片20不同，第二半导体芯片30和第三半导体芯片40可以不包括任何硅通孔。即，第一半导体芯片20包括穿透电极21，但是堆叠在第一半导体芯片20上的半导体芯片(例如，第二半导体芯片30和第三半导体芯片40)可以不包括穿透电极21或者任何其等同物。因此，可以改善关于第一半导体芯片20上的半导体芯片的堆叠的自由度。
第一外围区域EA1、中心区域CA和第二外围区域EA2在图1中被示出为彼此清楚地可区分的，如虚线所示，但是本公开不限于此。即，第一半导体芯片20的第一外围区域EA1可以指叠置在第一半导体芯片20与第二半导体芯片30之间的区域。另外，第一半导体芯片20的第二外围区域EA2可以指叠置在第一半导体芯片20与第三半导体芯片40之间的区域。另外，第一半导体芯片20的中心区域CA可以指第一半导体芯片20的包括穿透电极21的区域。
第二半导体芯片30可以设置在第一半导体芯片20的第一外围区域EA1上。第二半导体芯片30可以电连接到第一半导体芯片20。即，形成在第二半导体芯片30上的第二焊盘30a可以经由一条导电引线50连接到第一半导体芯片20的一个第一焊盘20a。因此，第二半导体芯片30可以电连接到第一半导体芯片20。导电引线50可以是导线，但是本公开不限于此。第二半导体芯片30可以具有第二长度W2。
第三半导体芯片40可以设置在第一半导体芯片20的第二外围区域EA2上。第三半导体芯片40可以电连接到第一半导体芯片20。即，形成在第三半导体芯片40上的第三焊盘40a可以经由另一条导电引线50连接到不与第二焊盘30a连接的另一个第一焊盘20a。因此，第三半导体芯片40可以电连接到第一半导体芯片20。第三半导体芯片40可以具有第三长度W3。
如上所述，第一半导体芯片20可以具有第一长度W1，第二半导体芯片30可以具有第二长度W2，第三半导体芯片40可以具有第三长度W3。第一长度W1可以比第二长度W2长。第一长度W1可以比第三长度W3长。第二长度W2和第三长度W3可以相等，但是本公开不限于此。第二长度W2和第三长度W3的和可以与第一长度W1相同，但是本公开不限于此。
例如，第二半导体芯片30和第三半导体芯片40可以通过划分包括多个半导体芯片区域的基底来获得。即，如果第一半导体芯片20包括至少两个分离的半导体芯片区域，则具有第二长度W2的第二半导体芯片30和具有第三长度W3的第三半导体芯片40可以通过物理地分离第一半导体芯片20的半导体芯片区域来获得，在该情况下，第二长度W2和第三长度W3的和可以与第一长度W1相同。如果第二长度W2和第三长度W3相等，则第一外围区域EA1和第二外围区域EA2可以相对于中心区域CA彼此对称。
第二半导体芯片30和第三半导体芯片40可以具有相同的高度，第二半导体芯片30和第三半导体芯片40的顶表面可以设置在同一平面上。
第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以都是DRAM半导体芯片。例如，如果第一半导体芯片20包括两个独立的半导体芯片区域，则根据本公开的示例实施例的半导体封装件可以基本上是包括四个DRAM半导体芯片的半导体封装件。
设置在安装板10上的第一半导体芯片20、第二半导体芯片30和第三半导体芯片40可以被封装成型部件60围绕。通过使用封装成型部件60，可以填充第一半导体芯片20与安装板10之间的空间。封装成型部件60可以包括例如环氧成型化合物(EMC)或聚酰亚胺，但是本公开不限于此。
绝缘粘合层22可以设置在第一半导体芯片20与第二半导体芯片30之间和第一半导体芯片20与第三半导体芯片40之间。通过使用绝缘粘合层22，第二半导体芯片30可以附着到第一半导体芯片20上，第三半导体芯片40可以附着到第一半导体芯片20上。绝缘粘合层22可以包括绝缘材料。绝缘粘合层22可以设置在第二半导体芯片30和第三半导体芯片40的整个底表面上，但是本公开不限于此。即，一个绝缘粘合层22可以仅设置在第二半导体芯片30的底表面的在第一半导体芯片20与第二半导体芯片30之间叠置的区域中的部分上。另外，另一个绝缘粘合层22可以仅设置在第三半导体芯片40的底表面的在第一半导体芯片20与第三半导体芯片40之间叠置的区域中的部分上。
绝缘粘合层22可以是例如裸片附着膜(DAF，die attach film)，但是本公开不限于此。
在下文中将参照图2描述根据本公开的另一个示例实施例的半导体封装件。
图2是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了导电引线的类型之外，根据图2的示例实施例的半导体封装件与根据图1的示例实施例的半导体封装件基本上相同。在图1和图2中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图2，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。
第二半导体芯片30和第三半导体芯片40可以经由导电引线51电连接到第一半导体芯片20。
例如，一条导电引线51可以从第二半导体芯片30的第二焊盘30a的顶表面沿第二半导体芯片30的顶表面和侧壁以及第一半导体芯片20的顶表面延伸以接触第一半导体芯片20的一个第一焊盘20a的顶表面。因此，第二半导体芯片30可以电连接到第一半导体芯片20。
另一条导电引线51可以从第三半导体芯片40的第三焊盘40a的顶表面沿第三半导体芯片40的顶表面和侧壁以及第一半导体芯片20的顶表面延伸以接触第一半导体芯片20的另一个第一焊盘20a的顶表面。因此，第三半导体芯片40可以电连接到第一半导体芯片20。
导电引线51可以由包括Cu的导电材料形成。
因为导电引线51沿第二半导体芯片30和第三半导体芯片40的顶表面和侧壁延伸，所以与导电引线51被设置为导线的情况相比，可以进一步小型化根据本示例实施例的半导体封装件。
在下文中将参照图3描述根据本公开的另一个示例实施例的半导体封装件。
图3是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了根据图3的示例实施例的半导体封装件还包括再布线层之外，根据图3的示例实施例的半导体封装件基本上与根据图1的示例实施例的半导体封装件相同。在图1和图3中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图3，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。
第二半导体芯片30包括第二中心焊盘30c、第二再布线层30b、第二焊盘30a和第二绝缘层30d。第二再布线层30b可以电连接第二中心焊盘30c和第二焊盘30a。第二绝缘层30d可以覆盖第二半导体芯片30的除了第二焊盘30a的顶表面之外的整个顶表面。
第三半导体芯片40包括第三中心焊盘40c、第三再布线层40b、第三焊盘40a和第三绝缘层40d。第三再布线层40b可以电连接第三中心焊盘40c和第三焊盘40a。第三绝缘层40d可以覆盖第三半导体芯片40的除了第三焊盘40a的顶表面之外的整个顶表面。
因为第二半导体芯片30包括第二再布线层30b，第三半导体芯片40包括第三再布线层40b，所以可以自由地设计第二焊盘30a和第三焊盘40a的位置。
在下文中将参照图4描述根据本公开的另一个示例实施例的半导体封装件。
图4是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了堆叠的半导体芯片的数量之外，根据图4的示例实施例的半导体封装件与根据图1的示例实施例的半导体封装件基本上相同。在图1和图4中，同样的附图标记表示同样的元件，因此将省略其详细的描述。
参照图4，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。
根据本示例实施例的半导体封装件还可以包括设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35。根据本示例实施例的半导体封装件还可以包括设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45。
第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45可以是例如存储器芯片或逻辑芯片。在第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45是逻辑芯片的情况下，考虑到通过第一半导体芯片20、第二半导体芯片30和第三半导体芯片40执行的操作的类型，第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45可以以各种方式来设计。逻辑芯片可以是微处理器(例如，CPU、控制器或ASIC)。
第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45可以是存储器芯片，例如，非易失性存储器芯片。例如，存储器芯片可以是闪存芯片。更具体地，存储器芯片可以是NAND闪存芯片或NOR闪存芯片，但是本公开不限于此。即，存储器芯片的示例可以包括PRAM、MRAM或RRAM。
与第一半导体芯片20不同，第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45可以不包括穿透电极。
第四半导体芯片33可以包括第四焊盘33a，第六半导体芯片35可以包括第六焊盘35a。第四半导体芯片33和第六半导体芯片35可以以阶梯的方式设置在第二半导体芯片30上，使得第四焊盘33a和第六焊盘35a可以被暴露。被暴露的第四焊盘33a和第六焊盘35a可以分别连接到导电引线50。因此，第四半导体芯片33和第六半导体芯片35可以电连接到第一半导体芯片20。
第五半导体芯片43可以包括第五焊盘43a，第七半导体芯片45可以包括第七焊盘45a。第五半导体芯片43和第七半导体芯片45可以以阶梯的方式设置在第三半导体芯片40上，使得第五焊盘43a和第七焊盘45a可以被暴露。被暴露的第五焊盘43a和第七焊盘45a可以分别连接到导电引线50。因此，第五半导体芯片43和第七半导体芯片45可以电连接到第一半导体芯片20。
第二半导体芯片30和第三半导体芯片40被示出为具有相同数量的堆叠在其上的半导体芯片，但是本公开不限于此。即，堆叠在第二半导体芯片30上的半导体芯片的数量可以与堆叠在第三半导体芯片40上的半导体芯片的数量不同。
第二半导体芯片30和第三半导体芯片40中的每个被示出为具有堆叠在其上的两个半导体芯片，但是本公开不限于此。即，可以在第二半导体芯片30和第三半导体芯片40中的每个上堆叠两个以上的半导体芯片。
在下文中将参照图5描述根据本公开的另一个示例实施例的半导体封装件。
图5是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了导电引线的类型之外，根据图5的示例实施例的半导体封装件与根据图4的示例实施例的半导体封装件基本上相同。在图4和图5中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图5，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。根据本示例实施例的半导体封装件还可以包括设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35。根据本示例实施例的半导体封装件还可以包括设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45。
第二半导体芯片30、第四半导体芯片33和第六半导体芯片35可以经由一条导电引线51电连接到第一半导体芯片20。导电引线51可以从第六半导体芯片35的第六焊盘35a沿第六半导体芯片35的顶表面和侧壁延伸，因此可以连接到第四半导体芯片33的第四焊盘33a。然后，导电引线51可以从第四半导体芯片33的第四焊盘33a沿第四半导体芯片33的顶表面和侧壁延伸，因此可以连接到第二半导体芯片30的第二焊盘30a。然后，导电引线51可以从第二半导体芯片30的第二焊盘30a沿第二半导体芯片30的顶表面和侧壁延伸，因此可以连接到第一半导体芯片20的第一焊盘20a。
相似地，第三半导体芯片40、第五半导体芯片43和第七半导体芯片45可以经由另一条导电引线51电连接到第一半导体芯片20。导电引线51可以从第七半导体芯片45的第七焊盘45a沿第七半导体芯片45的顶表面和侧壁延伸，因此可以电连接到第五半导体芯片43的第五焊盘43a。然后，导电引线51可以从第五半导体芯片43的第五焊盘43a沿第五半导体芯片43的顶表面和侧壁延伸，因此可以电连接到第三半导体芯片40的第三焊盘40a。然后，导电引线51可以从第三半导体芯片40的第三焊盘40a沿第三半导体芯片40的顶表面和侧壁延伸，因此可以电连接到第一半导体芯片20的另一个第一焊盘20a。
因为根据本示例实施例的半导体封装件包括沿第二半导体芯片30、第三半导体芯片40、第四半导体芯片33、第五半导体芯片43、第六半导体芯片35和第七半导体芯片45的顶表面和侧壁延伸的导电引线51，所以可以进一步小型化根据本示例实施例的半导体封装件。
在下文中将参照图6描述根据本公开的另一个示例实施例的半导体封装件。
图6是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了半导体芯片不以阶梯的方式堆叠之外，根据图6的示例实施例的半导体封装件与根据图4的示例实施例的半导体封装件基本上相同。在图4和图6中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图6，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。根据本示例实施例的半导体封装件还可以包括设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35。根据本示例实施例的半导体封装件还可以包括设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45。
设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35可以彼此对准，而不在其侧边上形成任何阶梯的结构。另外，设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45可以彼此对准，而不在其侧边上形成任何阶梯的结构。
因为焊盘需要经由绝缘粘合层24连接到导电引线50，所以绝缘粘合层24可以被形成为比包括在根据先前的示例实施例的半导体封装件中的任何一个的绝缘粘合层22相对厚，但是本公开不限于此。
绝缘粘合层24可以是例如DAF，但是本公开不限于此。
在根据本示例实施例的半导体封装件中，半导体芯片可以以其侧边对准来堆叠，以不形成任何阶梯结构。因此，因为与根据先前的示例实施例的半导体封装件相比，可以减小根据本示例实施例的半导体封装件在半导体芯片的长度方向上的长度。因此，可以进一步小型化根据本示例实施例的半导体封装件。
在下文中将参照图7描述根据本公开的另一个示例实施例的半导体封装件。
图7是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了根据图7的示例实施例的半导体封装件还包括额外的导电引线和边缘焊盘之外，根据图7的示例实施例的半导体封装件与根据图6的示例实施例的半导体封装件基本上相同。在图6和图7中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图7，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。根据本示例实施例的半导体封装件还可以包括设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35。根据本示例实施例的半导体封装件还可以包括设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45。
第一半导体芯片20可以包括第一边缘焊盘20b。第二半导体芯片30可以包括第二边缘焊盘30b。第三半导体芯片40可以包括第三边缘焊盘40b。第四半导体芯片33可以包括第四边缘焊盘33b。第五半导体芯片43可以包括第五边缘焊盘43b。第六半导体芯片35可以包括第六边缘焊盘35b。第七半导体芯片45可以包括第七边缘焊盘45b。
第一边缘焊盘20b、第二边缘焊盘30b、第三边缘焊盘40b、第四边缘焊盘33b、第五边缘焊盘43b、第六边缘焊盘35b和第七边缘焊盘45b可以经由导电引线53电连接到设置在安装板10上的边缘键合焊盘14。
例如，根据本示例实施例的半导体封装件可以经由第一边缘焊盘20b、第二边缘焊盘30b、第三边缘焊盘40b、第四边缘焊盘33b、第五边缘焊盘43b、第六边缘焊盘35b和第七边缘焊盘45b供应额外的电力。因此，根据本示例实施例的半导体封装件可以改善电力供应的稳定性。
然而，本公开不限于该示例。即，额外的数据信号可以经由第一边缘焊盘20b、第二边缘焊盘30b、第三边缘焊盘40b、第四边缘焊盘33b、第五边缘焊盘43b、第六边缘焊盘35b和第七边缘焊盘45b来输入或输出。
在下文中将参照图8描述根据本公开的另一个示例实施例的半导体封装件。
图8是根据本公开的另一个示例实施例的半导体封装件的剖视图。
除了根据图8的示例实施例的半导体封装件还包括位于第一半导体芯片下方的额外的端子之外，根据图8的示例实施例的半导体封装件与根据图7的示例实施例的半导体封装件基本上相同。在图7和图8中，同样的附图标记表示同样的元件，因此，将省略其详细的描述。
参照图8，根据本示例实施例的半导体封装件包括安装板10、第一半导体芯片20、第二半导体芯片30、第三半导体芯片40和封装成型部件60。根据本示例实施例的半导体封装件还可以包括设置在第二半导体芯片30上的第四半导体芯片33和第六半导体芯片35。根据本示例实施例的半导体封装件还可以包括设置在第三半导体芯片40上的第五半导体芯片43和第七半导体芯片45。
第一半导体芯片20还可以包括额外的端子25。通过设置除了第一端子23之外的额外的端子25，可以使由第一半导体芯片20产生的热有效地消散。因此，可以改善根据本示例实施例的半导体封装件的可靠性。
额外的端子25可以包括具有高导热性的材料。额外的端子25可以被设置为例如金属板或金属箔。更具体地，额外的端子25可以被设置为例如Cu板、Al板、Cu箔、Al箔或它们的组合，但是本公开不限于此。
图9是示出应用根据本公开的一些示例实施例的一个或更多个半导体封装件的存储卡的示意图。
参照图9，存储卡800可以包括位于外壳810中的控制器820和存储器830。控制器820和存储器830可以交换电信号。例如，存储器830和控制器820可以根据控制器820的指令交换数据。因此，存储卡800可以将数据存储在存储器830中或者从存储器830输出数据。
控制器820或存储器830可以包括根据本公开的一些示例实施例的半导体封装件。例如，控制器820可以包括系统级封装(SIP)，存储器830可以包括多芯片封装(MCP)。控制器820和/或存储器830可以被设置为堆叠封装(SP)。
存储卡800可以被用作用于各种便携式装置的数据存储介质。存储卡800的示例可以包括多媒体卡(MMC)和安全数字(SD)卡。
图10是应用根据本公开的一些示例实施例的一个或更多个半导体封装件的电子系统的框图。
参照图10，电子系统900可以采用根据本公开的上述示例实施例的半导体封装件。例如，电子系统900可以包括存储器系统902、处理器904、RAM906和用户界面908。
存储器系统902、处理器904、RAM 906和用户界面908可以经由总线910彼此交流数据。
处理器904可以执行程序，并可以控制电子系统900。RAM 906可以被用作用于处理器904的操作存储器。处理器904和RAM 906可以使用制造根据本公开的上述示例实施例的半导体封装件中的任何一个的方法被封装到单个半导体装置或单个半导体封装件中。
用户界面908可以被用来输入数据或从电子系统900输出数据。存储器系统902可以存储用于操作处理器904的代码，并且也可以存储由处理器904处理的数据或从外部源输入到此的数据。
存储器系统902可以包括控制器以驱动存储器系统902，并且也可以包括纠错块(未示出)。纠错块可以被构造为借助于纠错码(ECC)检测来自于存储器系统902中存在的数据的错误并且被构造为纠正检测到的错误。
存储器系统902可以被集成到单个半导体装置中。存储器系统902可以被集成到单个半导体装置中以形成存储卡。例如，存储器系统902可以被集成到单个半导体装置中以形成诸如PC存储卡国际联合会(PCMCIA)卡、紧凑式闪存(CF)卡、智能媒体(SM)卡(诸如SMC)、存储棒、多媒体卡(MMC)(诸如RS-MMC或MMCmicro)、安全数字(SD)卡(诸如迷你SD、微型SC或SDHC)或者通用快闪存储(UFS)的存储卡。
图10的电子系统900可以应用到用于各种电子装置的电子控制装置。图11是示出将图10的电子系统900应用到智能电话1400的示例的示意性视图。在图10的电子系统900被应用到智能电话1400的情况下，图10的电子系统900可以是但不限于应用处理器(AP)。
图10的电子系统900可以被设置为计算机、超移动PC(UMPC)、工作站、上网本计算机(net-book computer)、个人数字助理(PDA)、便携式计算机、网络平板(web tablet)、无线电话、移动电话、智能电话、电子书、便携式多媒体播放器(PMP)、便携式游戏控制台、导航装置、黑匣子、数码相机、3维电视机、数字音频记录器、数字音频播放器、数字图像记录器、数字图片播放器、数字视频记录器、数字视频播放器、能够在无线环境下传递并接收数据的装置、构成家庭网络的各种电子装置之一、构成计算机网络的各种电子装置之一、构成远程信息处理网络的各种电子装置之一、射频识别(RFID)装置或构成计算机系统的各种电子装置之一。
应理解的是，在此描述的示例实施例应仅被认为是描述性的，而不是出于限制性的目的。在根据示例实施例的每个装置或方法之内的特征或方面的描述通常应被认为是可用于根据示例实施例的其它装置或方法中的其它相似特征或方面。尽管已经具体示出并描述了一些示例实施例，本领域普通技术人员将理解的是，在不脱离权利要求的精神和范围的情况下，可以对其做出形式上和细节上的改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
安装板；
第一半导体芯片，位于安装板上，第一半导体芯片具有第一外围区域、第二外围区域和位于第一外围区域与第二外围区域之间的中心区域，中心区域具有形成在其中的穿透电极；
第二半导体芯片，位于第一外围区域上，第二半导体芯片包括位于其顶表面上的第二焊盘；
第三半导体芯片，位于第二外围区域上，第三半导体芯片包括位于其顶表面上的第三焊盘；
导电引线，分别从第二焊盘和第三焊盘延伸，导电引线分别电连接到穿透电极。
2.根据权利要求1所述的半导体封装件，其中：
第一半导体芯片在长度方向上具有第一长度，第二半导体芯片在长度方向上具有第二长度，第三半导体芯片在长度方向上具有第三长度；
第二长度和第三长度均短于第一长度。
3.根据权利要求2所述的半导体封装件，其中，第二长度和第三长度的和等于第一长度。
4.根据权利要求1所述的半导体封装件，其中，第二半导体芯片和第三半导体芯片的顶表面在同一平面上。
5.根据权利要求1所述的半导体封装件，其中，导电引线之中的至少一条第一导电引线从第二焊盘沿第二半导体芯片的顶表面和侧壁延伸。
6.根据权利要求1所述的半导体封装件，其中，第二半导体芯片还包括从第二焊盘的底表面延伸的再布线层。
7.根据权利要求1所述的半导体封装件，其中，第二半导体芯片的部分不与第一半导体芯片叠置。
8.根据权利要求1所述的半导体封装件，其中，第二半导体芯片和第三半导体芯片不包括在第二半导体芯片和第三半导体芯片中的硅通孔。
9.一种半导体封装件，所述半导体封装件包括：
安装板；
第一半导体芯片，位于安装板上，第一半导体芯片包括穿透电极和第一焊盘，穿透电极位于第一半导体芯片中，第一焊盘分别位于穿透电极上；
第二半导体芯片和第三半导体芯片，位于第一半导体芯片上，第二半导体芯片和第三半导体芯片彼此隔开以暴露位于第二半导体芯片和第三半导体芯片之间的第一焊盘，第二半导体芯片和第三半导体芯片没有硅通孔；
导电引线，电连接第一半导体芯片、第二半导体芯片和第三半导体芯片。
10.根据权利要求9所述的半导体封装件，其中：
第一半导体芯片在长度方向上具有第一长度，第二半导体芯片在长度方向上具有第二长度，第三半导体芯片在长度方向上具有第三长度；
第二长度和第三长度均短于第一长度。
11.根据权利要求10所述的半导体封装件，其中，第二长度和第三长度的和等于第一长度。
12.根据权利要求9所述的半导体封装件，其中，第二半导体芯片和第三半导体芯片的顶表面在同一平面上。
13.根据权利要求9所述的半导体封装件，其中，导电引线之中的至少一条第一导电引线从第二半导体芯片的第二焊盘沿第二半导体芯片的顶表面和侧壁延伸。
14.根据权利要求9所述的半导体封装件，其中，第二半导体芯片还包括从第二半导体芯片的第二焊盘的底表面延伸的再布线层。
15.根据权利要求9所述的半导体封装件，其中，第二半导体芯片的部分不与第一半导体芯片叠置。
16.一种半导体封装件，所述半导体封装件包括：
安装板；
第一半导体芯片，位于安装板上，第一半导体芯片包括位于其中心区域处的穿透电极，穿透电极将安装板电连接到第一半导体芯片；
至少一个第二半导体芯片和至少一个第三半导体芯片，位于第一半导体芯片上，第二半导体芯片包括位于其顶表面上的第二焊盘，第三半导体芯片包括位于其顶表面上的第三焊盘，第二半导体芯片和第三半导体芯片彼此隔开以暴露第一半导体芯片的中心区域；
导电引线，分别从第二焊盘和第三焊盘延伸，导电引线分别将第二焊盘和第三焊盘电连接到穿透电极。
17.根据权利要求16所述的半导体封装件，其中，第一数量的导电引线沿第二半导体芯片的顶表面和侧壁延伸，第二数量的导电引线沿第三半导体芯片的顶表面和侧壁延伸。
18.根据权利要求16所述的半导体封装件，其中，第二半导体芯片还包括从第二焊盘的底表面延伸的再布线层。
19.根据权利要求16所述的半导体封装件，其中，第一半导体芯片还包括位于面对安装板的表面上的散热端子。
20.根据权利要求16所述的半导体封装件，其中，所述至少一个第二半导体芯片包括多个第二半导体芯片，所述多个第二半导体芯片堆叠在第一半导体芯片上，使得所述多个第二半导体芯片彼此对准，而不在所述多个第二半导体芯片的堆叠结构的侧边上形成任何阶梯结构。
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