CN112201641B - 包括层叠的半导体芯片的半导体封装件 - Google Patents
包括层叠的半导体芯片的半导体封装件 Download PDFInfo
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- CN112201641B CN112201641B CN201911376420.9A CN201911376420A CN112201641B CN 112201641 B CN112201641 B CN 112201641B CN 201911376420 A CN201911376420 A CN 201911376420A CN 112201641 B CN112201641 B CN 112201641B
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Abstract
包括层叠的半导体芯片的半导体封装件。该半导体封装件包括:基板,其包括开口;第一半导体芯片,其设置在基板上,包括通过开口暴露的多个第一芯片焊盘;第二半导体芯片,其设置在第一半导体芯片上以与第一半导体芯片部分地交叠,包括与开口对齐的多个第二芯片焊盘;以及重分布层,其形成在其上设置有第二半导体芯片的第二芯片焊盘的表面上。第二芯片焊盘中的一个或更多个与第一半导体芯片交叠并被第一半导体芯片覆盖,并且第二芯片焊盘的其余焊盘通过开口暴露。重分布层包括通过开口暴露的重分布焊盘,并且包括被配置为将第二芯片焊盘中的一个或更多个连接至重分布焊盘的重分布线。
Description
技术领域
示例性实施方式涉及一种半导体封装件,更具体地,涉及一种在基板上层叠多个芯片的半导体封装件。
背景技术
电子产品正逐渐变小并需要处理大容量数据。因此,有必要提高在这种电子产品中使用的半导体装置的集成度。
但是,因为由于半导体集成技术的限制而仅用一个半导体芯片难以满足所需要的容量,所以已经制造出将多个半导体芯片嵌入在一个半导体封装件中的半导体封装件。
即使半导体封装件包括多个半导体芯片,也需要满足提高操作准确性和速度、最小化尺寸、简化工艺和降低成本的需求。
发明内容
在一个实施方式中,一种半导体封装件可以包括:基板,其包括开口;第一半导体芯片,其设置在基板上,包括通过开口暴露的多个第一芯片焊盘;第二半导体芯片,其设置在第一半导体芯片上以与第一半导体芯片部分地交叠,包括与开口对齐的多个第二芯片焊盘;以及重分布层,其形成在其上设置有第二半导体芯片的第二芯片焊盘的表面上。第二芯片焊盘中的一个或更多个可以与第一半导体芯片交叠并可以被第一半导体芯片覆盖,并且第二芯片焊盘的其余焊盘通过开口暴露。重分布层可以包括通过开口暴露的重分布焊盘,并且包括被配置为将第二芯片焊盘中的所述一个或更多个连接至重分布焊盘的重分布线。
附图说明
图1是示意性地例示了根据一个实施方式的半导体封装件的立体图。
图2是例示了图1的半导体封装件的基板的底表面的平面图。
图3是例示了图1的半导体封装件的第一半导体芯片的底表面的平面图。
图4A是例示了图1的半导体封装件的第二半导体芯片的底表面的平面图,并且图4B是沿着平面图的线A-A'截取的截面图。
图5是例示了图1的半导体封装件的底表面的平面图并且是主要例示了第一半导体芯片和第二半导体芯片之间的交叠以及基于该交叠的重分布层的图。
图6是例示了图1的半导体封装件的底表面的平面图并且是主要例示了第一半导体芯片和第二半导体芯片之间的交叠以及基于该交叠的与基板的连接的图。
图7是图1的半导体封装件在第二方向上的侧视图。
图8是例示了根据另一实施方式的第一半导体芯片的底表面的平面图。
图9是例示了根据另一实施方式的第二半导体芯片的底表面的平面图。
图10是例示了根据另一实施方式的半导体封装件的平面图。
图11是例示了当两个互连中的一些互连彼此接触的方式共享路径时的电以感和电阻特性的图。
图12示出了例示采用包括根据一个实施方式的半导体封装件的存储卡的电子系统的框图。
图13示出了例示包括根据一个实施方式的半导体封装件的另一电子系统的框图。
具体实施方式
下面将参照附图更详细地描述各种实施方式。然而,本发明可以以不同的形式实施,并且不应被解释为限于本文所阐述的实施方式。相反,提供这些实施方式以使得本公开将是透彻的和完整的,并将向本领域技术人员充分传达本发明的范围。贯穿本公开,相似的附图标记始终在本发明的各个附图和实施方式中指代相似的部件。
在整个说明书中,当元件被称为“连接至”或“联接至”另一元件时,这可以表示前一元件直接连接或联接至后一元件,或者以另一元件介于它们之间的方式间接电连接或联接至后一元件。此外,当元件“包括”或“包含”组件时,这意味着该元件不排除另一组件,而是可以进一步包括或包含另一组件,除非相反地指出。此外,尽管说明书中描述的组件以单数形式呈现,但是本实施方式不限于此,而是相应组件也可以以复数形式呈现。
各种实施方式旨在提供一种能够以减小的尺寸来改善工艺和操作特性的半导体封装件。
图1至图7是说明根据一个实施方式的半导体封装件的图。具体而言,图1是示意性地例示了根据一个实施方式的半导体封装件的立体图。图2是例示了图1的半导体封装件的基板的底表面的平面图。图3是例示了图1的半导体封装件的第一半导体芯片的底表面的平面图。图4A是例示了图1的半导体封装件的第二半导体芯片的底表面的平面图,并且图4B是沿着平面图的线A-A'截取的截面图。图5是例示了图1的半导体封装件的底表面的平面图并且是主要例示了第一半导体芯片和第二半导体芯片之间的交叠以及基于该交叠的重分布层的图。图6是例示了图1的半导体封装件的底表面的平面图并且是主要例示了第一半导体芯片和第二半导体芯片之间的交叠以及基于该交叠的与基板的连接的图。图7是图1的半导体封装件在第二方向上的侧视图。以下描述参照图1至图7中的至少一个。
参照图1,本实施方式的半导体封装件可以包括基板100以及以阶梯状方式层叠在基板100上的第一半导体芯片200和第二半导体芯片300。
基板100可以是用于半导体封装件的、具有传送电信号的电路和/或互连结构的基板,诸如印刷电路板(PCB)。基板100可以具有在其上可设置有半导体封装件中所包括的各种电子元件的一个表面(例如,顶表面100B)。例如,第一半导体芯片200和第二半导体芯片300可以设置在顶表面100B上。另一方面,与顶表面100B相对的另一表面(例如,底表面100A)可以连接至用于将半导体封装件连接至外部装置的元件。此外,基板100可以包括贯穿顶表面100B和底表面100A二者的开口106。开口106可以具有在一个方向上延伸的条状形状。在下文中,将开口106的延伸方向称为第一方向,并且将与第一方向基本垂直的方向称为第二方向。
参照图1和图2,第一基板焊盘102和第二基板焊盘104可以设置在基板100的底表面100A上。第一基板焊盘102可以将基板100的顶表面100B上的第一半导体芯片200和第二半导体芯片300电连接至基板100。第二基板焊盘104可以将基板100的底表面100A上的外部连接元件电连接至基板100。基板焊盘可以表示为了将基板100连接至其它组件而通过基板100的表面暴露的导电元件或端子。第一基板焊盘102和第二基板焊盘104可以是基板100中的电路和/或互连结构的一部分。
第一基板焊盘102可以设置在开口106的沿第二方向的两侧上,并且可以在开口106的每侧上沿第一方向布置成行。第一基板焊盘102可以是用于布线接合的接合指。第二基板焊盘104可以布置在距开口106比第一基板焊盘102更远的区域中。第二基板焊盘104的布置与第一基板焊盘102的布置不同。第二基板焊盘104可以是用于接合焊球的球焊座。第一基板焊盘102的尺寸和节距可以小于第二基板焊盘104的尺寸和节距。此外,在实施方式中,第一基板焊盘102可以具有沿第二方向延伸的条形状或与条形状类似的形状,并且第二基板焊盘104可以具有圆形形状或与圆形形状类似的形状。然而,本实施方式不限于此,并且第一基板焊盘102和第二基板焊盘104的尺寸、数量、布置、形状等可以以各种方式变型。
参照图1和图3,第一半导体芯片200可以包括与基板100的顶表面100B面对的底表面200A、位于底表面200A的相对侧上的顶表面200B以及将底表面200A和顶表面200B连接的侧表面。第一半导体芯片200的底表面200A可以包括两个边缘区E1。也就是说,两个边缘区E1中的每一个在第二方向上的宽度可以小于第一半导体芯片200在第二方向上的总宽度的一半,并且中央区C1位于两个边缘区E1之间。
在第一半导体芯片200的底表面200A的中央区C1中,可以设置第一芯片焊盘202以将第一半导体芯片200电连接至基板100。也就是说,第一半导体芯片200可以是中央焊盘类型。在本实施方式中,第一芯片焊盘202可以在中央区C1中沿第一方向设置成一行,并且第一芯片焊盘202的行可以在第二方向上偏向一侧(例如,右侧),而不是中央区C1的中心。然而,本实施方式不限于此,并且第一芯片焊盘202的数量和布置可以以各种方式变型。此外,第一芯片焊盘202可以具有矩形平面形状;然而,本实施方式不限于此,并且平面形状可以以各种方式变型。
第一半导体芯片200可以通过粘合材料(未示出)附接到基板100的顶表面100B,并且其上设置有第一芯片焊盘202的底表面200A可以面对基板100的顶表面100B来附接。也就是说,第一半导体芯片200可以以面朝下的方式附接到基板100。此外,第一半导体芯片200可以设置为使得中央区C1与基板100的开口106对齐和/或第一芯片焊盘202与基板100的开口106对齐。因此,第一芯片焊盘202可以通过基板100的开口106暴露出来。
第一半导体芯片200可以包括诸如动态随机存取存储器(DRAM)之类的易失性存储器。然而,本实施方式不限于此,并且第一半导体芯片200可以包括各种集成电路装置,例如,诸如静态随机存取存储器(SRAM)之类的其它易失性存储器、诸如NAND闪存、相变随机存取存储器(PRAM)和磁阻随机存取存储器(MRAM)之类的非易失性存储器、逻辑装置和处理器等。
参照图1、图4A和图4B,第二半导体芯片300可以包括与基板100的顶表面100B和/或第一半导体芯片200的顶表面200B面对的底表面300A、位于底表面300A的相对侧的顶表面300B以及将底表面300A和顶表面300B连接的侧表面。第二半导体芯片300的底表面300A可以包括两个边缘区E2。也就是说,两个边缘区E2中的每一个在第二方向上的宽度可以小于第二半导体芯片300在第二方向的总宽度的一半,并且中央区C2位于两个边缘区E2之间。
在第二半导体芯片300的底表面300A的中央区C2中,可以设置第二芯片焊盘302以将第二半导体芯片300电连接至基板100。也就是说,第二半导体芯片300可以是中央焊盘类型。在本实施方式中,第二芯片焊盘302可以在中央区C2中沿第一方向设置成行,并且第二芯片焊盘302的行可以在第二方向上偏向一侧(例如,右侧)而不是中央区C2的中心。然而,本实施方式不限于此,并且第二芯片焊盘302的数量和布置可以以各种方式变型。此外,第二芯片焊盘302可以具有矩形的平面形状;然而,本实施方式不限于此,并且平面形状可以以各种方式变型。
在本实施方式中,第二半导体芯片300可以是与第一半导体芯片200基本相同的芯片。在这种情况下,第二半导体芯片300可以包括与第一半导体芯片200基本相同种类的集成电路装置。此外,第二半导体芯片300可以具有与第一半导体芯片200基本相同的平面面积,并且第二芯片焊盘302的形状、布置和数量可以与第一芯片焊盘(图3的202)基本相同。然而,为了便于描述,将第二半导体芯片300和第二芯片焊盘302例示为比第一半导体芯片200和第一芯片焊盘(图3的202)更粗的线。
第二半导体芯片300可以通过粘合材料(未示出)附接到第一半导体芯片200的顶表面200B,并且其上设置有第二芯片焊盘302的底表面300A可以面向基板100的顶表面100B附接。也就是说,第二半导体芯片300可以以面朝下的方式安装在基板100上。第二半导体芯片300可以被设置为使得第二半导体芯片300的一部分在第一方向上与第一半导体芯片200交叠,并且中央区C2和/或第二芯片焊盘302与基板100的开口106对齐。因此,第二芯片焊盘302的位于与第一半导体芯片200交叠的区域(参见图4A的A1,在下文中称为交叠区)中的一些焊盘由于被第一半导体芯片200覆盖而没有通过开口106暴露出来。另一方面,位于交叠区A1之外的区域(参见图4A的A2,在下文中,被称为非交叠区)中的第二芯片焊盘302可以通过开口106暴露出来。
如上所述,由于第二半导体芯片300的第二芯片焊盘302当中的交叠区A1中的第二芯片焊盘302被第一半导体芯片200覆盖,因此难以通过布线接合工艺将第二芯片焊盘302连接至基板100。为了解决这样的问题,第二半导体芯片300可以进一步包括形成在底表面300A上的重分布层320。重分布层320可以包括重分布导电层322和324以及重分布绝缘层326和328。
具体地,在图4A所示的平面上,重分布导电层322和324可以包括重分布焊盘322和重分布线324。重分布焊盘322可以形成在第二半导体芯片300的中央区C2的非交叠区A2中。重分布线324可以从交叠区A1的第二芯片焊盘302延伸到非交叠区A2的重分布焊盘322。重分布焊盘322可以形成为以一对一的方式与交叠区A1的第二芯片焊盘302相对应,并且可以设置在中央区C2的非交叠区A2内的未设置第二芯片焊盘302的区域中。重分布焊盘322可以沿第一方向设置成行。例如,当第二芯片焊盘302的行在中央区C2中沿第二方向偏向一侧时,重分布焊盘322的行可以在第二方向上偏向另一侧。图4A例示出了其中第二芯片焊盘302的行被设置为偏向右侧并且重分布焊盘322的行被设置为偏向左侧的示例。为了便于描述,重分布焊盘322的平面形状被例示为圆形,但是重分布焊盘322的平面形状可以以各种方式变型,如矩形。在另一实施方式中,重分布焊盘322也可以具有与第二芯片焊盘302基本相同的平面形状和尺寸。此外,重分布焊盘322的数量和布置可以以各种方式变型。重分布线324可以具有以曲线弯曲的形状,以用于从交叠区A1的第二芯片焊盘302到非交叠区A2的重分布焊盘322的连接。重分布线324可以形成为彼此不交叉。为此,在交叠区A1的第二芯片焊盘302和非交叠区A2的重分布焊盘322当中,彼此邻近的焊盘可以彼此连接,并且彼此远离的焊盘可以彼此连接。例如,在第一方向上最靠近交叠区A1的重分布焊盘322-1和交叠区A1中的最靠近非交叠区A2的第二芯片焊盘302-1可以通过最短的重分布线324-1彼此连接,并且在第一方向上距交叠区A1最远的重分布焊盘322-2和交叠区A1中的离非交叠区A2最远的第二芯片焊盘302-2可以通过最长的重分布线324-2彼此连接。
参照图4B中所示的部分,重分布导电层322和324可以与除了通过重分布绝缘层326和328暴露出的部分之外的其它组件电隔离。覆盖第二半导体芯片300的底表面的第一重分布绝缘层326可以具有使第二芯片焊盘302的表面暴露的开口。重分布线324可以在通过填充第一重分布绝缘层326的开口来电连接至第二芯片焊盘302的同时,在第一重分布绝缘层326之上延伸。重分布线324可以在具有相对大宽度的端部的同时以具有窄宽度的线形状延伸。第二重分布绝缘层328在覆盖重分布线324和第一重分布绝缘层326的同时,可以具有使重分布线324的端部暴露的开口。重分布线324的端部的通过第二重分布绝缘层328中形成的开口所暴露的部分可以构成重分布焊盘322。
当从下面看时,上述的包括基板100、第一半导体芯片200和第二半导体芯片300的半导体封装件可以与图5和图6基本相同。此外,当从第一方向上的侧面观看时,半导体封装件可以与图7基本相同。为了便于描述,尽管图5没有例示第一基板焊盘102和第二基板焊盘104以及互连器500并且图6没有例示重分布线324,但是本实施方式的半导体封装件可以包括图5和图6中示出的所有配置。将省略与图1至图3、图4A和图4B中描述的部件基本相同的各部件的详细说明。
参照图1、图5、图6和图7,基板100可以具有沿第一方向延伸的开口106。基板100可以包括位于底表面100A上的用于与第一半导体芯片200和第二半导体芯片300连接的第一基板焊盘102以及用于与外部连接元件400连接的第二基板焊盘104。
外部连接元件400可以连接至基板100的底表面100A上的第二基板焊盘104。在本实施方式中,将焊球用作外部连接元件400。然而,本实施方式不限于此,并且可以使用各种类型的电连接器。本实施方式的封装件可以通过这样的外部连接元件400连接至诸如模块基板之类的各种外部装置。
在基板100的顶表面100B上,第一半导体芯片200和第二半导体芯片300可以在第一方向上以阶梯状方式层叠和设置。也就是说,第二半导体芯片300可以被定位为在第一方向上与第一半导体芯片200移开预定距离,以使得第一半导体芯片200和第二半导体芯片300在第一方向上彼此部分地交叠。根据实施方式,当第一半导体芯片200和第二半导体芯片300具有基本相同的平面形状时,第一半导体芯片200和第二半导体芯片300可以沿着第二方向彼此对齐。
由于第一半导体芯片200的第一芯片焊盘202设置在第一半导体芯片200的底表面200A的中央区C1中并且与基板100的开口106对齐,所以第一芯片焊盘202可以通过开口106暴露。第二半导体芯片300的第二芯片焊盘302可以设置在第二半导体芯片300的底表面300A的中央区C2中,并且可以与基板100的开口106对齐。然而,第二半导体芯片300的第二芯片焊盘302中的一些(参见图6的虚线矩形)可以与第一半导体芯片200交叠,并且因此无法通过开口106暴露。第二半导体芯片300的位于与第一半导体芯片200的交叠区A1中的第二芯片焊盘302可以通过重分布线324连接至位于第二半导体芯片300的底表面300A的中央区C2和非交叠区A2中的重分布焊盘322。重分布焊盘322可以通过开口106暴露出来。
第一芯片焊盘202和第一基板焊盘102可以通过延伸穿过开口106的互连器500彼此电连接。在本实施方式中,互连器500可以是接合布线。在这种情况下,接合布线的端部可以分别联接至第一基板焊盘102和第一芯片焊盘202。接合布线可以包括诸如金、银、铜和铂的金属或者包括金、银、铜和铂的合金,接合布线可通过超声能和/或热焊接到第一基板焊盘102和第一芯片焊盘202。然而,本实施方式不限于此,并且可以使用各种类型的诸如引线之类的电互连器。
当通过开口106暴露的第一芯片焊盘202的行在第二方向上偏向一侧(例如,右侧)时,第一芯片焊盘202可以电连接至开口106的两侧的第一基板焊盘102当中的相对靠近第一芯片焊盘202的第一基板焊盘102,即,开口106的右侧上的第一基板焊盘102。在下文中,为了便于描述,将开口106的右侧上的第一基板焊盘102称为右第一基板焊盘102A,并且将开口106的左侧上的第一基板焊盘102称为左第一基板焊盘102B。
此外,第二芯片焊盘302和重分布焊盘322可以分别通过互连器500电连接至第一基板焊盘102。将第二芯片焊盘302或重分布焊盘322与第一基板焊盘102连接的互连器500可以延伸以穿过开口106。为了抑制封装件制造工艺中的由于将第二芯片焊盘302或重分布焊盘322和第一基板焊盘102电连接的互连器500中的干扰或电短路引起的故障,可以将第二芯片焊盘302和重分布焊盘322电连接至开口106的两侧上的第一基板焊盘102当中的、相对靠近第二芯片焊盘302和重分布焊盘322的第一基板焊盘102。当第二芯片焊盘302的行沿第二方向偏向一侧(例如,右侧)时,第二芯片焊盘302可以电连接至开口106的两侧上的第一基板焊盘102当中的相对靠近第二芯片焊盘302的右第一基板焊盘102A。另一方面,当重分布焊盘322的行在第二方向上偏向另一侧(例如,左侧)时,重分布焊盘322可以电连接至左第一基板焊盘102B。
第一粘合层610可以插置于第一半导体芯片200和基板100之间,以将第一半导体芯片200的底表面200A附接到基板100的顶表面100B。第一粘合层610可以形成为在使第一半导体芯片200的底表面200A的中央区(参见图3的C1)暴露的同时覆盖边缘区(参见图3的E1)。此外,第二粘合层620可以插置于第二半导体芯片300和第一半导体芯片200之间,以将第二半导体芯片300的底表面300A附接到第一半导体芯片200的顶表面200B。第二粘合层620可以形成为在使第二半导体芯片300的底表面300A的中央区(参见图4A的C2)暴露的同时覆盖边缘区(参见图4A的E2),并且形成在重分布层320和第一半导体芯片200之间,而不是与第二半导体芯片300的底表面300A直接接触。
由于重分布层320存在于第二半导体芯片300的底表面300A上,因此第二芯片焊盘302可以通过形成于重分布绝缘层326和328中的开口而暴露。
密封剂(encapsulant)700可以形成为覆盖基板100、第一半导体芯片200和第二半导体芯片300。具体地,密封剂700可以形成为在填充第一半导体芯片200和第一半导体芯片200之间的空间以及基板100的开口106的同时围绕互连器500。密封剂700可以由诸如环氧模塑料之类的材料形成。
基于上述半导体封装件,可以获得以下优点。
首先,由于半导体封装件具有两个半导体芯片200和300在第一方向上彼此交叠的区域,所以与两个半导体芯片200和300并排设置的结构相比,可以减小半导体封装件的面积。
此外,由于仅在第二半导体芯片300中形成重分布层320,所以与在所有半导体芯片中形成有重分布层的结构相比,可以降低形成重分布层所需的工艺成本。
尽管上述实施方式已经描述了芯片焊盘布置成一行并且重分布焊盘在与芯片焊盘的行的位置不同的位置处布置成一行的情况,但是芯片焊盘可以布置成两行或更多行。在这种情况下,可能需要调整重分布焊盘的位置。以下将参照图8和图9对此进行描述。
图8是例示了根据另一实施方式的第一半导体芯片的底表面的平面图,并且图9是例示了根据另一实施方式的第二半导体芯片的底表面的平面图。图8的第一半导体芯片和图9的第二半导体芯片可以按照与前述实施方式中所述的方式基本相同的方式设置在基板100上。在下文中,将主要描述与前述实施方式的不同之处。
参照图8,本实施方式的第一半导体芯片200'的底表面可以具有中央区C1和边缘区E1,并且第一芯片焊盘202'可以暴露于中央区C1中。
第一芯片焊盘202'可以基于第二方向布置成两行。在第二方向上,第一芯片焊盘202'的相对向左布置的行在下文中被称为第一行,第一芯片焊盘202'的相对向右布置的行在下文中被称为第二行。
在本实施方式中,第一行中的第一芯片焊盘202'的数量可以小于第二行中的第一芯片焊盘202'的数量,使得与第二行相比,在第一行中可以存在空的空间。然而,本实施方式不限于此,并且第一行中的第一芯片焊盘202'的数量和第二行中的第一芯片焊盘202'的数量可以以各种方式变型。
参照图9,本实施方式的第二半导体芯片300'的底表面可以具有中央区C2和边缘区E2,并且第二芯片焊盘302'可以暴露于中央区C2中。
在本实施方式中,第二芯片焊盘302'的布置可以与第一芯片焊盘202'的布置基本相同。也就是说,第二芯片焊盘302'可以沿第二方向布置在第一行和第二行中,并且第一行中的第二芯片焊盘302'的数量可以小于第二行中的第二芯片焊盘302'的数量,使得与第二行相比,在第一行中可以存在空的空间。然而,本实施方式不限于此,并且第一行中的第二芯片焊盘302'的数量和第二行中的第二芯片焊盘302'的数量可以以各种方式变型。
由于第二芯片焊盘302'当中的交叠区A1的第二芯片焊盘302'将被第一半导体芯片200'覆盖,因此可以有必要形成连接至第二芯片焊盘302'的重分布焊盘322'和重分布线324'。
首先,与本实施方式不同,所有重分布焊盘322'可以形成在第一行和/或第二行中。换句话说,第一行和/或第二行可以具有可形成要连接至交叠区A1的全部第二芯片焊盘302'的重分布焊盘322'的空间。在这种情况下,由于第一行的重分布焊盘322'和/或第二芯片焊盘302'可以连接至基板开口的左基板焊盘,并且第二行的重分布焊盘322'和/或第二芯片焊盘302'可以连接至基板开口的右基板焊盘,因此具有促进诸如布线接合之类的工艺的优点。
另一方面,如在本实施方式中,也可以在第一行和/或第二行中仅形成重分布焊盘322'的一些。例如,如图9所示,可以存在形成七个重分布焊盘322'所需的空的空间,该七个重分布焊盘322'分别连接至交叠区A1的七个第二芯片焊盘302'。然而,能够在非交叠区A2的第一行中仅设置两个重分布焊盘322'。在这种情况下,其余的重分布焊盘322'可以设置在与第一行和第二行不同的位置处的第三行中。例如,如图9所示,可以在第一行中设置两个重分布焊盘322',并且可以在第一行和第二行之间的第三行中设置五个重分布焊盘322'。
如上所述,当重分布焊盘322'在第一方向上位于与第一行和第二行不同的第三行中时,第三行的重分布焊盘322'可以设置为在与第一行的第二芯片焊盘302'和重分布焊盘322'偏移的同时与第二行的第二芯片焊盘302'偏移。这是为了提供用于在后续布线接合期间要形成的布线的空间,从而防止布线之间的短路。例如,当第一行的第二芯片焊盘302'和重分布焊盘322'被布线接合到基板开口左侧上的基板焊盘(参见箭头①),并且第二行的第二芯片焊盘302'被布线接合到基板开口右侧上的基板焊盘(参见箭头②)时,第三行的重分布焊盘322'可以被布线接合到基板开口左侧上的基板焊盘(参见箭头③)或基板开口右侧上的基板焊盘。在这种情况下,由于连接至第三行的重分布焊盘322'的布线延伸到在第一方向上相邻的第二芯片焊盘302'之间的空间,所以可以防止与连接至第二芯片焊盘302'的布线短路。
重分布线324'可以具有以曲线弯曲的形状,以用于从交叠区A1的第二芯片焊盘302'到非交叠区A2的重分布焊盘322'的连接。重分布线324'可以形成为彼此不交叉。为此,重分布线324'可以在第二方向上绕开另一侧,以连接至不同行的重分布焊盘322'。例如,重分布线324'可以从第一行的重分布焊盘322'相对向左延伸,以在第一方向上弯曲,并且延伸到交叠区A1中的第一行的第二芯片焊盘302'。此外,重分布线324'可以从第三行的重分布焊盘322'相对向右延伸,以在第一方向上弯曲,并且延伸到交叠区A1中的第二行的第二芯片焊盘302'。
基于本实施方式,即使芯片焊盘202'和302'以及重分布焊盘322'的数量、布置等变型,也可以获得上述实施方式的优点。
图10是例示了根据又一实施方式的半导体封装件的平面图,并且与图6类似,是从下方例示了第一半导体芯片和第二半导体芯片之间的交叠以及基于该交叠的与基板的连接的图,并且没有例示出重分布线(图5的324)。在下文中,将主要描述与前述实施方式的不同之处。
参照图10,如上所述,可以基于开口106将第一基板焊盘102分类为右第一基板焊盘102A和左第一基板焊盘102B。第一基板焊盘102可以包括施加有半导体芯片的操作所需的各种输入/输出信号的输入/输出焊盘、连接至地的接地焊盘、连接至电源的电源焊盘等。为了便于描述,在右第一基板焊盘102A中,电源焊盘由附图标记102A-P表示,而接地焊盘由附图标记102A-G表示。另外,在左第一基板焊盘102B中,电源焊盘由附图标记102B-P表示,接地焊盘由附图标记102B-G表示。在本实施方式中,两个电源焊盘102A-P和102B-P以及两个接地焊盘102A-G和102B-G被标记在任意位置,但是电源焊盘和接地焊盘的数量或布置可以以各种方式变型。
连接至右电源焊盘102A-P的第二芯片焊盘302A和连接至左电源焊盘102B-P的重分布焊盘322A可以彼此连接以共享电源路径。为此,可以在重分布焊盘322A和第二芯片焊盘302A之间形成附加重分布线324P。
此外,连接至右接地焊盘102A-G的第二芯片焊盘302B和连接至左接地焊盘102B-G的重分布焊盘322B可以彼此连接以共享接地路径。为此,可以在重分布焊盘322B和第二芯片焊盘302B之间形成附加重分布线324G。
基于本实施方式,除了上述实施方式的优点之外,还能够获得以下优点。
首先,可以省略重分布焊盘322A与左电源焊盘102B-P之间的接合布线以及第二芯片焊盘302A与右电源焊盘102A-P之间的接合布线中的任何一个(参见图10的标记X)。另选地,可以省略重分布焊盘322B与左接地焊盘102B-G之间的接合布线以及第二芯片焊盘302B与右接地焊盘102A-G之间的接合布线中的任何一个(参见图10的标记X)。这是因为重分布焊盘322A和第二芯片焊盘302A可以捆绑在一起以共享电源路径,或者重分布焊盘322B和第二芯片焊盘302B可以捆绑在一起以共享接地路径。因此,通过省略接合布线,可以简化工艺并降低工艺成本。
此外,当重分布焊盘322A和322B以及第二芯片焊盘302A和302B捆绑在一起时,具体地,当它们如图10的实施方式中那样以近距离捆绑在一起时,能够改善配电网络(PDN)的特性。也就是说,可以减小电源路径或接地路径的电感和电阻。将参照图11描述具体的操作原理。
图11是例示了当两个互连中的一些互连以彼此接触的方式共享路径时的电感和电阻特性的图。
参照图11,当两个信号的传输路径在靠近起点的位置(即,焊盘)处捆绑在一起时(参见情况1),能够理解,与传输路径在远离起点的位置处捆绑在一起的情况(参见情况2)或传输路径没有捆绑在一起的情况(参见情况3)相比,电感和电阻最低。
基于图11,由于重分布焊盘322A和322B以及第二芯片焊盘302A和302B通过附加重分布线324P和324G在靠近位置处捆绑在一起,因此与它们没有捆绑在的情况或者它们在远离起点的位置处通过例如基板100中的互连等捆绑在一起的情况相比,能够改善电源路径或接地路径的电感和电阻。也就是说,情况1的PDN特性优于情况2或情况3的PDN特性。
图12示出了例示包括采用根据实施方式的半导体封装件中的至少一个的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置之类的存储器7810和存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据所描述的实施方式的半导体封装件中的至少一个。
存储器7810可以包括应用了本公开的实施方式的技术的非易失性存储器装置。存储器控制器7820可以控制存储器7810,使得响应于来自主机7830的读取/写入请求而读出所存储的数据或存储数据。
图13示出了例示包括根据所描述的实施方式的半导体封装件中的至少一个的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过提供数据移动的路径的总线8715彼此联接。
在实施方式中,控制器8711可以包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同功能的逻辑器件。控制器8711或存储器8713可以包括根据本公开的实施方式的一个或更多个半导体封装件。输入/输出装置8712可以包括从小键盘、键盘、显示装置、触摸屏等当中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储要由控制器8711执行的数据和/或命令等。
存储器8713可以包括诸如DRAM之类的易失性存储器装置和/或诸如闪存之类的非易失性存储器装置。例如,闪存可以被安装到诸如移动终端或台式计算机之类的信息处理系统。闪存可以构成固态盘(SSD)。在这种情况下,电子系统8710可以在闪存系统中稳定地存储大量数据。
电子系统8710可以进一步包括接口8714,该接口8714被配置为向通信网络发送数据和从通信网络接收数据。接口8714可以是有线类型或无线类型。例如,接口8714可以包括天线或有线或无线收发器。
电子系统8710可以被实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如,移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任何一种。
如果电子系统8710表示能够执行无线通信的设备,则电子系统8710可以被用在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强型时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
尽管已经出于示例性目的描述了各种实施方式,但是对于本领域技术人员显而易见的是,在不脱离如所附权利要求限定的本发明的精神和范围的情况下,可以进行各种改变和变型。
相关申请的交叉引用
本申请要求于2019年7月8日提交的韩国专利申请No.10-2019-0081983的优先权,该韩国专利申请的全部内容通过引用合并于本文中。
Claims (20)
1.一种半导体封装件,该半导体封装件包括:
基板,该基板包括开口;
第一半导体芯片,该第一半导体芯片被设置在所述基板上,包括通过所述开口暴露的多个第一芯片焊盘;
第二半导体芯片,该第二半导体芯片被设置在所述第一半导体芯片上以与所述第一半导体芯片部分地交叠,该第二半导体芯片包括与所述开口对齐的多个第二芯片焊盘;以及
重分布层,该重分布层形成在其上设置有所述第二半导体芯片的所述第二芯片焊盘的表面上,
其中,所述第二芯片焊盘中的一个或更多个与所述第一半导体芯片交叠并且被所述第一半导体芯片覆盖,并且所述第二芯片焊盘的其余焊盘通过所述开口暴露,
其中,所述重分布层包括通过所述开口暴露的重分布焊盘,并且包括被配置为将所述第二芯片焊盘中的被所述第一半导体芯片覆盖的一个或更多个第二芯片焊盘连接至所述重分布焊盘的重分布线,
其中,所述第二半导体芯片被设置为在第一方向上与所述第一半导体芯片部分地交叠,
所述第二芯片焊盘在所述第一方向上布置成一行,并且
所述重分布焊盘在所述第二芯片焊盘的行的一侧上沿所述第一方向布置成一行。
2.根据权利要求1所述的半导体封装件,其中,所述开口在第一方向上的宽度大于所述开口在与所述第一方向基本垂直的第二方向上的宽度,并且
所述第二半导体芯片被设置为在所述第一方向上与所述第一半导体芯片部分地交叠。
3.根据权利要求1所述的半导体封装件,其中,所述基板具有面对所述第一半导体芯片的第一表面以及与所述第一表面相对定位的第二表面,并且所述基板包括位于所述基板的所述第二表面上的第一基板焊盘。
4.根据权利要求3所述的半导体封装件,该半导体封装件还包括互连器,该互连器被配置为通过所述开口将所述第一芯片焊盘、所述第二芯片焊盘中的所述其余焊盘以及所述重分布焊盘连接至所述第一基板焊盘。
5.根据权利要求4所述的半导体封装件,其中,所述第一基板焊盘包括设置在所述开口的一侧上的一侧第一基板焊盘以及设置在所述开口的另一侧上的另一侧第一基板焊盘,
其中,连接至所述第一芯片焊盘的所述互连器和连接至所述第二芯片焊盘的所述其余焊盘的所述互连器连接至所述一侧第一基板焊盘,并且
其中,连接至所述重分布焊盘的所述互连器连接至所述另一侧第一基板焊盘。
6.根据权利要求1所述的半导体封装件,其中,所述基板具有面对所述第一半导体芯片的第一表面和与所述第一表面相对定位的第二表面,并且所述基板包括位于所述基板的所述第二表面上并设置在所述开口的一侧上的一侧第一基板焊盘以及位于所述基板的所述第二表面上并设置在所述开口的另一侧上的另一侧第一基板焊盘,并且
所述半导体封装件还包括:
互连器,该互连器被配置为将所述重分布焊盘连接至所述一侧第一基板焊盘,并将所述第二芯片焊盘的所述其余焊盘连接至所述另一侧第一基板焊盘。
7.根据权利要求1所述的半导体封装件,其中,所述基板具有面对所述第一半导体芯片的第一表面和与所述第一表面相对的第二表面,并且包括位于所述基板的所述第二表面上的电源焊盘,并且
其中,所述重分布层还包括附加重分布线,该附加重分布线将需要连接至所述电源焊盘的所述第二芯片焊盘和所述重分布焊盘连接。
8.根据权利要求7所述的半导体封装件,该半导体封装件还包括互连器,该互连器被配置为将需要连接至所述电源焊盘的所述第二芯片焊盘和所述重分布焊盘中的一个连接至所述电源焊盘。
9.根据权利要求1所述的半导体封装件,其中,所述基板具有面对所述第一半导体芯片的第一表面和与所述第一表面相对的第二表面,并且包括位于所述基板的所述第二表面上的接地焊盘,并且
其中,所述重分布层还包括附加重分布线,该附加重分布线将需要连接至所述接地焊盘的所述第二芯片焊盘和所述重分布焊盘连接。
10.根据权利要求9所述的半导体封装件,该半导体封装件还包括互连器,该互连器被配置为将需要连接至所述接地焊盘的所述第二芯片焊盘和所述重分布焊盘中的一个连接至所述接地焊盘。
11.根据权利要求1所述的半导体封装件,其中,所述第一芯片焊盘位于所述第一半导体芯片的中央区中,并且
所述第二芯片焊盘位于所述第二半导体芯片的中央区中。
12.根据权利要求1所述的半导体封装件,其中,所述第一芯片焊盘的布置与所述第二芯片焊盘的布置基本相同。
13.根据权利要求2所述的半导体封装件,其中,所述第一半导体芯片的两个侧表面在所述第二方向上与所述第二半导体芯片的两个侧表面对齐。
14.根据权利要求3所述的半导体封装件,其中,所述基板还包括:
第二基板焊盘,所述第二基板焊盘位于所述基板的所述第二表面上并且能连接至外部连接元件。
15.根据权利要求1所述的半导体封装件,该半导体封装件还包括:
第一粘合层,该第一粘合层位于所述第一半导体芯片和所述基板之间;以及
第二粘合层,该第二粘合层位于所述重分布层和所述第一半导体芯片之间。
16.根据权利要求1所述的半导体封装件,该半导体封装件还包括:
密封剂,该密封剂被配置为在覆盖所述基板、所述第一半导体芯片和所述第二半导体芯片的同时填充所述开口。
17.一种半导体封装件,该半导体封装件包括:
基板,该基板包括开口;
第一半导体芯片,该第一半导体芯片被设置在所述基板上,包括通过所述开口暴露的多个第一芯片焊盘;
第二半导体芯片,该第二半导体芯片被设置在所述第一半导体芯片上以与所述第一半导体芯片部分地交叠,该第二半导体芯片包括与所述开口对齐的多个第二芯片焊盘;以及
重分布层,该重分布层形成在其上设置有所述第二半导体芯片的所述第二芯片焊盘的表面上,
其中,所述第二芯片焊盘中的一个或更多个与所述第一半导体芯片交叠并且被所述第一半导体芯片覆盖,并且所述第二芯片焊盘的其余焊盘通过所述开口暴露,
其中,所述重分布层包括通过所述开口暴露的重分布焊盘,并且包括被配置为将所述第二芯片焊盘中的被所述第一半导体芯片覆盖的一个或更多个第二芯片焊盘连接至所述重分布焊盘的重分布线,
其中,所述第二半导体芯片被设置为在第一方向上与所述第一半导体芯片部分地交叠,
所述第二芯片焊盘包括在所述第一方向上布置成一行的第一行和在所述第一行的一侧上沿所述第一方向布置成一行的第二行,并且所述第一行和所述第二行中的至少一行具有其中未设置所述第二芯片焊盘的空间;并且
所述重分布焊盘被设置在所述空间中。
18.根据权利要求17所述的半导体封装件,其中,所述基板具有面对所述第一半导体芯片的第一表面和与所述第一表面相对定位的第二表面,并且所述基板包括位于所述基板的所述第二表面上并设置在所述开口的一侧上的一侧第一基板焊盘以及位于所述基板的所述第二表面上并设置在所述开口的另一侧上的另一侧第一基板焊盘,并且
所述半导体封装件还包括:
互连器,该互连器配置为将所述第一行的所述第二芯片焊盘的所述其余焊盘或第一行的所述重分布焊盘连接至所述一侧第一基板焊盘,并且将所述第二行的所述第二芯片焊盘的所述其余焊盘或所述第二行的所述重分布焊盘连接至所述另一侧第一基板焊盘。
19.一种半导体封装件,该半导体封装件包括:
基板,该基板包括开口;
第一半导体芯片,该第一半导体芯片被设置在所述基板上,包括通过所述开口暴露的多个第一芯片焊盘;
第二半导体芯片,该第二半导体芯片被设置在所述第一半导体芯片上以与所述第一半导体芯片部分地交叠,该第二半导体芯片包括与所述开口对齐的多个第二芯片焊盘;以及
重分布层,该重分布层形成在其上设置有所述第二半导体芯片的所述第二芯片焊盘的表面上,
其中,所述第二芯片焊盘中的一个或更多个与所述第一半导体芯片交叠并且被所述第一半导体芯片覆盖,并且所述第二芯片焊盘的其余焊盘通过所述开口暴露,
其中,所述重分布层包括通过所述开口暴露的重分布焊盘,并且包括被配置为将所述第二芯片焊盘中的被所述第一半导体芯片覆盖的一个或更多个第二芯片焊盘连接至所述重分布焊盘的重分布线,
其中,所述第二半导体芯片被设置为在第一方向上与所述第一半导体芯片部分地交叠,
所述第二芯片焊盘包括在所述第一方向上布置成一行的第一行和在所述第一行的一侧上沿所述第一方向布置成一行的第二行,并且
所述重分布焊盘被布置在沿第二方向位于所述第一行和所述第二行之间的第三行中。
20.根据权利要求19所述的半导体封装件,其中,所述重分布焊盘在所述第一方向上与所述第二芯片焊盘交替地布置。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20070088177A (ko) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20070088179A (ko) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20120068661A (ko) * | 2011-03-18 | 2012-06-27 | 테세라, 인코포레이티드 | 중앙 콘택을 구비한 적층형 마이크로전자 조립체 |
CN103887274A (zh) * | 2012-12-20 | 2014-06-25 | 三星电子株式会社 | 半导体封装件 |
CN107104082A (zh) * | 2016-02-23 | 2017-08-29 | 三星电子株式会社 | 半导体封装件 |
CN108022916A (zh) * | 2016-11-04 | 2018-05-11 | 三星电子株式会社 | 半导体封装和制造半导体封装的方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101479461B1 (ko) * | 2008-10-14 | 2015-01-06 | 삼성전자주식회사 | 적층 패키지 및 이의 제조 방법 |
US8115292B2 (en) * | 2008-10-23 | 2012-02-14 | United Test And Assembly Center Ltd. | Interposer for semiconductor package |
KR101601847B1 (ko) * | 2009-05-21 | 2016-03-09 | 삼성전자주식회사 | 반도체 패키지 |
KR20100134354A (ko) * | 2009-06-15 | 2010-12-23 | 삼성전자주식회사 | 반도체 패키지, 스택 모듈, 카드 및 전자 시스템 |
JP5646830B2 (ja) * | 2009-09-02 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の製造方法、及びリードフレーム |
KR101963883B1 (ko) * | 2012-07-05 | 2019-04-01 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
KR102161776B1 (ko) * | 2014-03-28 | 2020-10-06 | 에스케이하이닉스 주식회사 | 적층 패키지 |
KR102255758B1 (ko) * | 2017-04-26 | 2021-05-26 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
EP3764120A1 (en) * | 2019-07-10 | 2021-01-13 | Swisscom AG | Low power wide area network localization |
KR20210016216A (ko) * | 2019-08-02 | 2021-02-15 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20070088177A (ko) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20070088179A (ko) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20120068661A (ko) * | 2011-03-18 | 2012-06-27 | 테세라, 인코포레이티드 | 중앙 콘택을 구비한 적층형 마이크로전자 조립체 |
CN103887274A (zh) * | 2012-12-20 | 2014-06-25 | 三星电子株式会社 | 半导体封装件 |
CN107104082A (zh) * | 2016-02-23 | 2017-08-29 | 三星电子株式会社 | 半导体封装件 |
CN108022916A (zh) * | 2016-11-04 | 2018-05-11 | 三星电子株式会社 | 半导体封装和制造半导体封装的方法 |
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