TW202103289A - 包含堆疊半導體晶片的半導體封裝件 - Google Patents
包含堆疊半導體晶片的半導體封裝件 Download PDFInfo
- Publication number
- TW202103289A TW202103289A TW108144305A TW108144305A TW202103289A TW 202103289 A TW202103289 A TW 202103289A TW 108144305 A TW108144305 A TW 108144305A TW 108144305 A TW108144305 A TW 108144305A TW 202103289 A TW202103289 A TW 202103289A
- Authority
- TW
- Taiwan
- Prior art keywords
- pad
- substrate
- wafer
- redistribution
- semiconductor
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/301—Disposition
- H01L2224/3012—Layout
- H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3312—Layout
- H01L2224/3315—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/33154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/33155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/45169—Platinum (Pt) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
- H01L2224/85207—Thermosonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種半導體封裝件被揭示。半導體封裝件包括:基板,其包括開口;第一半導體晶片,其設置在基板上,包括通過開口暴露的多個第一晶片墊;第二半導體晶片,其設置在第一半導體晶片上以與第一半導體晶片部分地重疊,包括與開口對齊的多個第二晶片墊;以及重分佈層,其形成在其上設置有第二半導體晶片的第二晶片墊的表面上。第二晶片墊中的一個或更多個與第一半導體晶片重疊並被第一半導體晶片覆蓋,並且第二晶片墊的其餘墊通過開口暴露。重分佈層包括通過開口暴露的重分佈墊,並且包括被配置為將第二晶片墊中的一個或更多個連接至重分佈墊的重分佈線。
Description
示例性實施方式涉及一種半導體封裝件,更具體地,涉及一種在基板上堆疊多個晶片的半導體封裝件。
相關申請的交叉引用
本申請案主張於2019年7月8日提交的韓國專利申請第10-2019-0081983號的優先權,該韓國專利申請的全部內容通過引用合併於本文中。
電子產品正逐漸變小並需要處理大容量資料。因此,有必要提高在這種電子產品中使用的半導體裝置的整合度。
但是,因為由於半導體整合技術的限制而僅用一個半導體晶片難以滿足所需要的容量,所以已經製造出將多個半導體晶片嵌入在一個半導體封裝件中的半導體封裝件。
即使半導體封裝件包括多個半導體晶片,也需要滿足提高操作準確性和速度、最小化尺寸、簡化製程和降低成本的需求。
在一個實施方式中,一種半導體封裝件可以包括:基板,其包括開口;第一半導體晶片,其設置在基板上,包括通過開口暴露的多個第一晶片墊;第二半導體晶片,其設置在第一半導體晶片上以與第一半導體晶片部分地重疊,包括與開口對齊的多個第二晶片墊;以及重分佈層,其形成在其上設置有第二半導體晶片的第二晶片墊的表面上。第二晶片墊中的一個或更多個可以與第一半導體晶片重疊並可以被第一半導體晶片覆蓋,並且第二晶片墊的其餘墊通過開口暴露。重分佈層可以包括通過開口暴露的重分佈墊,並且包括被配置為將第二晶片墊中的所述一個或更多個連接至重分佈墊的重分佈線。
下面將參照附圖更詳細地描述各種實施方式。然而,本發明可以以不同的形式實施,並且不應被解釋為限於本文所闡述的實施方式。相反,提供這些實施方式以使得本公開將是透徹的和完整的,並將向本領域技術人員充分傳達本發明的範圍。貫穿本公開,相似的附圖標記始終在本發明的各個附圖和實施方式中指代相似的部件。
在整個說明書中,當元件被稱為“連接至”或“耦接至”另一元件時,這可以表示前一元件直接連接或耦接至後一元件,或者以另一元件介於它們之間的方式間接電連接或耦接至後一元件。此外,當元件“包括”或“包含”元件時,這意味著該元件不排除另一元件,而是可以進一步包括或包含另一元件,除非相反地指出。此外,儘管說明書中描述的組件以單數形式呈現,但是本實施方式不限於此,而是相應元件也可以以複數形式呈現。
各種實施方式旨在提供一種能夠以減小的尺寸來改善製程和操作特性的半導體封裝件。
圖1至圖7是說明根據一個實施方式的半導體封裝件的圖。具體而言,圖1是示意性地例示了根據一個實施方式的半導體封裝件的立體圖。圖2是例示了圖1的半導體封裝件的基板的底表面的平面圖。圖3是例示了圖1的半導體封裝件的第一半導體晶片的底表面的平面圖。圖4A是例示了圖1的半導體封裝件的第二半導體晶片的底表面的平面圖,並且圖4B是沿著平面圖的線A-A'截取的截面圖。圖5是例示了圖1的半導體封裝件的底表面的平面圖並且是主要例示了第一半導體晶片和第二半導體晶片之間的重疊以及基於該重疊的重分佈層的圖。圖6是例示了圖1的半導體封裝件的底表面的平面圖並且是主要例示了第一半導體晶片和第二半導體晶片之間的重疊以及基於該重疊的與基板的連接的圖。圖7是圖1的半導體封裝件在第二方向上的側視圖。以下描述參照圖1至圖7中的至少一個。
參照圖1,本實施方式的半導體封裝件可以包括基板100以及以階梯狀方式堆疊在基板100上的第一半導體晶片200和第二半導體晶片300。
基板100可以是用於半導體封裝件的、具有傳送電信號的電路和/或互連結構的基板,諸如印刷電路板(PCB)。基板100可以具有在其上可設置有半導體封裝件中所包括的各種電子元件的一個表面(例如,頂表面100B)。例如,第一半導體晶片200和第二半導體晶片300可以設置在頂表面100B上。另一方面,與頂表面100B相對的另一表面(例如,底表面100A)可以連接至用於將半導體封裝件連接至外部裝置的元件。此外,基板100可以包括貫穿頂表面100B和底表面100A二者的開口106。開口106可以具有在一個方向上延伸的條狀形狀。在下文中,將開口106的延伸方向稱為第一方向,並且將與第一方向基本垂直的方向稱為第二方向。
參照圖1和圖2,第一基板墊102和第二基板墊104可以設置在基板100的底表面100A上。第一基板墊102可以將基板100的頂表面100B上的第一半導體晶片200和第二半導體晶片300電連接至基板100。第二基板墊104可以將基板100的底表面100A上的外部連接元件電連接至基板100。基板墊可以表示為了將基板100連接至其它元件而通過基板100的表面暴露的導電元件或端子。第一基板墊102和第二基板墊104可以是基板100中的電路和/或互連結構的一部分。
第一基板墊102可以設置在開口106的沿第二方向的兩側上,並且可以在開口106的每側上沿第一方向佈置成一列。第一基板墊102可以是用於佈線接合的接合指。第二基板墊104可以佈置在距開口106比第一基板墊102更遠的區域中。第二基板墊104的佈置與第一基板墊102的佈置不同。第二基板墊104可以是用於接合焊球的球焊座。第一基板墊102的尺寸和節距可以小於第二基板墊104的尺寸和節距。此外,在實施方式中,第一基板墊102可以具有沿第二方向延伸的條形狀或與條形狀類似的形狀,並且第二基板墊104可以具有圓形形狀或與圓形形狀類似的形狀。然而,本實施方式不限於此,並且第一基板墊102和第二基板墊104的尺寸、數量、佈置、形狀等可以以各種方式變型。
參照圖1和圖3,第一半導體晶片200可以包括與基板100的頂表面100B面對的底表面200A、位於底表面200A的相對側上的頂表面200B以及將底表面200A和頂表面200B連接的側表面。第一半導體晶片200的底表面200A可以包括兩個邊緣區E1。也就是說,兩個邊緣區E1中的每一個在第二方向上的寬度可以小於第一半導體晶片200在第二方向上的總寬度的一半,並且中央區C1位於兩個邊緣區E1之間。
在第一半導體晶片200的底表面200A的中央區C1中,可以設置第一晶片墊202以將第一半導體晶片200電連接至基板100。也就是說,第一半導體晶片200可以是中央墊類型。在本實施方式中,第一晶片墊202可以在中央區C1中沿第一方向設置成一列,並且第一晶片墊202的列可以在第二方向上偏向一側(例如,右側),而不是中央區C1的中心。然而,本實施方式不限於此,並且第一晶片墊202的數量和佈置可以以各種方式變型。此外,第一晶片墊202可以具有矩形平面形狀;然而,本實施方式不限於此,並且平面形狀可以以各種方式變型。
第一半導體晶片200可以通過黏合材料(未示出)附接到基板100的頂表面100B,並且其上設置有第一晶片墊202的底表面200A可以面對基板100的頂表面100B來附接。也就是說,第一半導體晶片200可以以面朝下的方式附接到基板100。此外,第一半導體晶片200可以設置為使得中央區C1與基板100的開口106對齊和/或第一晶片墊202與基板100的開口106對齊。因此,第一晶片墊202可以通過基板100的開口106暴露出來。
第一半導體晶片200可以包括諸如動態隨機存取記憶體(DRAM)之類的揮發性記憶體。然而,本實施方式不限於此,並且第一半導體晶片200可以包括各種積體電路裝置,例如,諸如靜態隨機存取記憶體(SRAM)之類的其它揮發性記憶體、諸如NAND快閃記憶體、相變隨機存取記憶體(PRAM)和磁阻隨機存取記憶體(MRAM)之類的非揮發性記憶體、邏輯裝置和處理器等。
參照圖1、圖4A和圖4B,第二半導體晶片300可以包括與基板100的頂表面100B和/或第一半導體晶片200的頂表面200B面對的底表面300A、位於底表面300A的相對側的頂表面300B以及將底表面300A和頂表面300B連接的側表面。第二半導體晶片300的底表面300A可以包括兩個邊緣區E2。也就是說,兩個邊緣區E2中的每一個在第二方向上的寬度可以小於第二半導體晶片300在第二方向的總寬度的一半,並且中央區C2位於兩個邊緣區E2之間。
在第二半導體晶片300的底表面300A的中央區C2中,可以設置第二晶片墊302以將第二半導體晶片300電連接至基板100。也就是說,第二半導體晶片300可以是中央墊類型。在本實施方式中,第二晶片墊302可以在中央區C2中沿第一方向設置成一列,並且第二晶片墊302的列可以在第二方向上偏向一側(例如,右側)而不是中央區C2的中心。然而,本實施方式不限於此,並且第二晶片墊302的數量和佈置可以以各種方式變型。此外,第二晶片墊302可以具有矩形的平面形狀;然而,本實施方式不限於此,並且平面形狀可以以各種方式變型。
在本實施方式中,第二半導體晶片300可以是與第一半導體晶片200基本相同的晶片。在這種情況下,第二半導體晶片300可以包括與第一半導體晶片200基本相同種類的積體電路裝置。此外,第二半導體晶片300可以具有與第一半導體晶片200基本相同的平面面積,並且第二晶片墊302的形狀、佈置和數量可以與第一晶片墊(圖3的202)基本相同。然而,為了便於描述,將第二半導體晶片300和第二晶片墊302例示為比第一半導體晶片200和第一晶片墊(圖3的202)更粗的線。
第二半導體晶片300可以通過黏合材料(未示出)附接到第一半導體晶片200的頂表面200B,並且其上設置有第二晶片墊302的底表面300A可以面向基板100的頂表面100B附接。也就是說,第二半導體晶片300可以以面朝下的方式安裝在基板100上。第二半導體晶片300可以被設置為使得第二半導體晶片300的一部分在第一方向上與第一半導體晶片200重疊,並且中央區C2和/或第二晶片墊302與基板100的開口106對齊。因此,第二晶片墊302的位於與第一半導體晶片200重疊的區域(參見圖4A的A1,在下文中稱為重疊區)中的一些墊由於被第一半導體晶片200覆蓋而沒有通過開口106暴露出來。另一方面,位於重疊區A1之外的區域(參見圖4A的A2,在下文中,被稱為非重疊區)中的第二晶片墊302可以通過開口106暴露出來。
如上所述,由於第二半導體晶片300的第二晶片墊302當中的重疊區A1中的第二晶片墊302被第一半導體晶片200覆蓋,因此難以通過佈線接合製程將第二晶片墊302連接至基板100。為了解決這樣的問題,第二半導體晶片300可以進一步包括形成在底表面300A上的重分佈層320。重分佈層320可以包括重分佈導電層322和324以及重分佈絕緣層326和328。
具體地,在圖4A所示的平面上,重分佈導電層322和324可以包括重分佈墊322和重分佈線324。重分佈墊322可以形成在第二半導體晶片300的中央區C2的非重疊區A2中。重分佈線324可以從重疊區A1的第二晶片墊302延伸到非重疊區A2的重分佈墊322。重分佈墊322可以形成為以一對一的方式與重疊區A1的第二晶片墊302相對應,並且可以設置在中央區C2的非重疊區A2內的未設置第二晶片墊302的區域中。重分佈墊322可以沿第一方向設置成一列。例如,當第二晶片墊302的列在中央區C2中沿第二方向偏向一側時,重分佈墊322的列可以在第二方向上偏向另一側。圖4A例示出了其中第二晶片墊302的列被設置為偏向右側並且重分佈墊322的列被設置為偏向左側的示例。為了便於描述,重分佈墊322的平面形狀被例示為圓形,但是重分佈墊322的平面形狀可以以各種方式改變,如矩形。在另一實施方式中,重分佈墊322也可以具有與第二晶片墊302基本相同的平面形狀和尺寸。此外,重分佈墊322的數量和佈置可以以各種方式改變。重分佈線324可以具有以曲線彎曲的形狀,以用於從重疊區A1的第二晶片墊302到非重疊區A2的重分佈墊322的連接。重分佈線324可以形成為彼此不交叉。為此,在重疊區A1的第二晶片墊302和非重疊區A2的重分佈墊322當中,彼此鄰近的墊可以彼此連接,並且彼此遠離的墊可以彼此連接。例如,在第一方向上最靠近重疊區A1的重分佈墊322-1和重疊區A1中的最靠近非重疊區A2的第二晶片墊302-1可以通過最短的重分佈線324-1彼此連接,並且在第一方向上距重疊區A1最遠的重分佈墊322-2和重疊區A1中的離非重疊區A2最遠的第二晶片墊302-2可以通過最長的重分佈線324-2彼此連接。
參照圖4B中所示的部分,重分佈導電層322和324可以與除了通過重分佈絕緣層326和328暴露出的部分之外的其它元件電隔離。覆蓋第二半導體晶片300的底表面的第一重分佈絕緣層326可以具有使第二晶片墊302的表面暴露的開口。重分佈線324可以在通過填充第一重分佈絕緣層326的開口來電連接至第二晶片墊302的同時,在第一重分佈絕緣層326之上延伸。重分佈線324可以在具有相對大寬度的端部的同時以具有窄寬度的線形狀延伸。第二重分佈絕緣層328在覆蓋重分佈線324和第一重分佈絕緣層326的同時,可以具有使重分佈線324的端部暴露的開口。重分佈線324的端部的通過第二重分佈絕緣層328中形成的開口所暴露的部分可以構成重分佈墊322。
當從下面看時,上述的包括基板100、第一半導體晶片200和第二半導體晶片300的半導體封裝件可以與圖5和圖6基本相同。此外,當從第一方向上的側面觀看時,半導體封裝件可以與圖7基本相同。為了便於描述,儘管圖5沒有例示第一基板墊102和第二基板墊104以及互連件500並且圖6沒有例示重分佈線324,但是本實施方式的半導體封裝件可以包括圖5和圖6中示出的所有配置。將省略與圖1至圖3、圖4A和圖4B中描述的部件基本相同的各部件的詳細說明。
參照圖1、圖5、圖6和圖7,基板100可以具有沿第一方向延伸的開口106。基板100可以包括位於底表面100A上的用於與第一半導體晶片200和第二半導體晶片300連接的第一基板墊102以及用於與外部連接元件400連接的第二基板墊104。
外部連接元件400可以連接至基板100的底表面100A上的第二基板墊104。在本實施方式中,將焊球用作外部連接元件400。然而,本實施方式不限於此,並且可以使用各種類型的電連接器。本實施方式的封裝件可以通過這樣的外部連接元件400連接至諸如模組基板之類的各種外部裝置。
在基板100的頂表面100B上,第一半導體晶片200和第二半導體晶片300可以在第一方向上以階梯狀方式堆疊和設置。也就是說,第二半導體晶片300可以被定位為在第一方向上與第一半導體晶片200移開預定距離,以使得第一半導體晶片200和第二半導體晶片300在第一方向上彼此部分地重疊。根據實施方式,當第一半導體晶片200和第二半導體晶片300具有基本相同的平面形狀時,第一半導體晶片200和第二半導體晶片300可以沿著第二方向彼此對齊。
由於第一半導體晶片200的第一晶片墊202設置在第一半導體晶片200的底表面200A的中央區C1中並且與基板100的開口106對齊,所以第一晶片墊202可以通過開口106暴露。第二半導體晶片300的第二晶片墊302可以設置在第二半導體晶片300的底表面300A的中央區C2中,並且可以與基板100的開口106對齊。然而,第二半導體晶片300的第二晶片墊302中的一些(參見圖6的虛線矩形)可以與第一半導體晶片200重疊,並且因此無法通過開口106暴露。第二半導體晶片300的位於與第一半導體晶片200的重疊區A1中的第二晶片墊302可以通過重分佈線324連接至位於第二半導體晶片300的底表面300A的中央區C2和非重疊區A2中的重分佈墊322。重分佈墊322可以通過開口106暴露出來。
第一晶片墊202和第一基板墊102可以通過延伸穿過開口106的互連件500彼此電連接。在本實施方式中,互連件500可以是接合佈線。在這種情況下,接合佈線的端部可以分別耦接至第一基板墊102和第一晶片墊202。接合佈線可以包括諸如金、銀、銅和鉑的金屬或者包括金、銀、銅和鉑的合金,接合佈線可通過超聲能和/或熱焊接到第一基板墊102和第一晶片墊202。然而,本實施方式不限於此,並且可以使用各種類型的諸如引線之類的電互連件。
當通過開口106暴露的第一晶片墊202的列在第二方向上偏向一側(例如,右側)時,第一晶片墊202可以電連接至開口106的兩側的第一基板墊102當中的相對靠近第一晶片墊202的第一基板墊102,即,開口106的右側上的第一基板墊102。在下文中,為了便於描述,將開口106的右側上的第一基板墊102稱為右第一基板墊102A,並且將開口106的左側上的第一基板墊102稱為左第一基板墊102B。
此外,第二晶片墊302和重分佈墊322可以分別通過互連件500電連接至第一基板墊102。將第二晶片墊302或重分佈墊322與第一基板墊102連接的互連件500可以延伸以穿過開口106。為了抑制封裝件製造製程中的由於將第二晶片墊302或重分佈墊322和第一基板墊102電連接的互連件500中的干擾或電短路引起的故障,可以將第二晶片墊302和重分佈墊322電連接至開口106的兩側上的第一基板墊102當中的、相對靠近第二晶片墊302和重分佈墊322的第一基板墊102。當第二晶片墊302的列沿第二方向偏向一側(例如,右側)時,第二晶片墊302可以電連接至開口106的兩側上的第一基板墊102當中的相對靠近第二晶片墊302的右第一基板墊102A。另一方面,當重分佈墊322的列在第二方向上偏向另一側(例如,左側)時,重分佈墊322可以電連接至左第一基板墊102B。
第一黏合層610可以插置於第一半導體晶片200和基板100之間,以將第一半導體晶片200的底表面200A附接到基板100的頂表面100B。第一黏合層610可以形成為在使第一半導體晶片200的底表面200A的中央區(參見圖3的C1)暴露的同時覆蓋邊緣區(參見圖3的E1)。此外,第二黏合層620可以插置於第二半導體晶片300和第一半導體晶片200之間,以將第二半導體晶片300的底表面300A附接到第一半導體晶片200的頂表面200B。第二黏合層620可以形成為在使第二半導體晶片300的底表面300A的中央區(參見圖4A的C2)暴露的同時覆蓋邊緣區(參見圖4A的E2),並且形成在重分佈層320和第一半導體晶片200之間,而不是與第二半導體晶片300的底表面300A直接接觸。
由於重分佈層320存在於第二半導體晶片300的底表面300A上,因此第二晶片墊302可以通過形成於重分佈絕緣層326和328中的開口而暴露。
囊封物700可以形成為覆蓋基板100、第一半導體晶片200和第二半導體晶片300。具體地,囊封物700可以形成為在填充第一半導體晶片200和第一半導體晶片200之間的空間以及基板100的開口106的同時圍繞互連件500。囊封物700可以由諸如環氧模塑膠之類的材料形成。
基於上述半導體封裝件,可以獲得以下優點。
首先,由於半導體封裝件具有兩個半導體晶片200和300在第一方向上彼此重疊的區域,所以與兩個半導體晶片200和300並排設置的結構相比,可以減小半導體封裝件的面積。
此外,由於僅在第二半導體晶片300中形成重分佈層320,所以與在所有半導體晶片中形成有重分佈層的結構相比,可以降低形成重分佈層所需的製程成本。
儘管上述實施方式已經描述了晶片墊佈置成一列並且重分佈墊在與晶片墊的列的位置不同的位置處佈置成一列的情況,但是晶片墊可以佈置成兩列或更多列。在這種情況下,可能需要調整重分佈墊的位置。以下將參照圖8和圖9對此進行描述。
圖8是例示了根據另一實施方式的第一半導體晶片的底表面的平面圖,並且圖9是例示了根據另一實施方式的第二半導體晶片的底表面的平面圖。圖8的第一半導體晶片和圖9的第二半導體晶片可以按照與前述實施方式中所述的方式基本相同的方式設置在基板100上。在下文中,將主要描述與前述實施方式的不同之處。
參照圖8,本實施方式的第一半導體晶片200'的底表面可以具有中央區C1和邊緣區E1,並且第一晶片墊202'可以暴露於中央區C1中。
第一晶片墊202'可以基於第二方向佈置成兩列。在第二方向上,第一晶片墊202'的相對向左佈置的列在下文中被稱為第一列,第一晶片墊202'的相對向右佈置的列在下文中被稱為第二列。
在本實施方式中,第一列中的第一晶片墊202'的數量可以小於第二列中的第一晶片墊202'的數量,使得與第二列相比,在第一列中可以存在空的空間。然而,本實施方式不限於此,並且第一列中的第一晶片墊202'的數量和第二列中的第一晶片墊202'的數量可以以各種方式改變。
參照圖9,本實施方式的第二半導體晶片300'的底表面可以具有中央區C2和邊緣區E2,並且第二晶片墊302'可以暴露於中央區C2中。
在本實施方式中,第二晶片墊302'的佈置可以與第一晶片墊202'的佈置基本相同。也就是說,第二晶片墊302'可以沿第二方向佈置在第一列和第二列中,並且第一列中的第二晶片墊302'的數量可以小於第二列中的第二晶片墊302'的數量,使得與第二列相比,在第一列中可以存在空的空間。然而,本實施方式不限於此,並且第一列中的第二晶片墊302'的數量和第二列中的第二晶片墊302'的數量可以以各種方式改變。
由於第二晶片墊302'當中的重疊區A1的第二晶片墊302'將被第一半導體晶片200'覆蓋,因此可以有必要形成連接至第二晶片墊302'的重分佈墊322'和重分佈線324'。
首先,與本實施方式不同,所有重分佈墊322'可以形成在第一列和/或第二列中。換句話說,第一列和/或第二列可以具有可形成要連接至重疊區A1的全部第二晶片墊302'的重分佈墊322'的空間。在這種情況下,由於第一列的重分佈墊322'和/或第二晶片墊302'可以連接至基板開口的左基板墊,並且第二列的重分佈墊322'和/或第二晶片墊302'可以連接至基板開口的右基板墊,因此具有促進諸如佈線接合之類的製程的優點。
另一方面,如在本實施方式中,也可以在第一列和/或第二列中僅形成重分佈墊322'的一些。例如,如圖9所示,可以存在形成七個重分佈墊322'所需的空的空間,該七個重分佈墊322'分別連接至重疊區A1的七個第二晶片墊302'。然而,能夠在非重疊區A2的第一列中僅設置兩個重分佈墊322'。在這種情況下,其餘的重分佈墊322'可以設置在與第一列和第二列不同的位置處的第三列中。例如,如圖9所示,可以在第一列中設置兩個重分佈墊322',並且可以在第一列和第二列之間的第三列中設置五個重分佈墊322'。
如上所述,當重分佈墊322'在第一方向上位於與第一列和第二列不同的第三列中時,第三列的重分佈墊322'可以設置為在與第一列的第二晶片墊302'和重分佈墊322'偏移的同時與第二列的第二晶片墊302'偏移。這是為了提供用於在後續佈線接合期間要形成的佈線的空間,從而防止佈線之間的短路。例如,當第一列的第二晶片墊302'和重分佈墊322'被佈線接合到基板開口左側上的基板墊(參見箭頭①),並且第二列的第二晶片墊302'被佈線接合到基板開口右側上的基板墊(參見箭頭②)時,第三列的重分佈墊322'可以被佈線接合到基板開口左側上的基板墊(參見箭頭③)或基板開口右側上的基板墊。在這種情況下,由於連接至第三列的重分佈墊322'的佈線延伸到在第一方向上相鄰的第二晶片墊302'之間的空間,所以可以防止與連接至第二晶片墊302'的佈線短路。
重分佈線324'可以具有以曲線彎曲的形狀,以用於從重疊區A1的第二晶片墊302'到非重疊區A2的重分佈墊322'的連接。重分佈線324'可以形成為彼此不交叉。為此,重分佈線324'可以在第二方向上繞開另一側,以連接至不同列的重分佈墊322'。例如,重分佈線324'可以從第一列的重分佈墊322'相對向左延伸,以在第一方向上彎曲,並且延伸到重疊區A1中的第一列的第二晶片墊302'。此外,重分佈線324'可以從第三列的重分佈墊322'相對向右延伸,以在第一方向上彎曲,並且延伸到重疊區A1中的第二列的第二晶片墊302'。
基於本實施方式,即使晶片墊202'和302'以及重分佈墊322'的數量、佈置等改變,也可以獲得上述實施方式的優點。
圖10是例示了根據又一實施方式的半導體封裝件的平面圖,並且與圖6類似,是從下方例示了第一半導體晶片和第二半導體晶片之間的重疊以及基於該重疊的與基板的連接的圖,並且沒有例示出重分佈線(圖5的324)。在下文中,將主要描述與前述實施方式的不同之處。
參照圖10,如上所述,可以基於開口106將第一基板墊102分類為右第一基板墊102A和左第一基板墊102B。第一基板墊102可以包括施加有半導體晶片的操作所需的各種輸入/輸出信號的輸入/輸出墊、連接至地的接地墊、連接至電源的電源墊等。為了便於描述,在右第一基板墊102A中,電源墊由附圖標記102A-P表示,而接地墊由附圖標記102A-G表示。另外,在左第一基板墊102B中,電源墊由附圖標記102B-P表示,接地墊由附圖標記102B-G表示。在本實施方式中,兩個電源墊102A-P和102B-P以及兩個接地墊102A-G和102B-G被標記在任意位置,但是電源墊和接地墊的數量或佈置可以以各種方式改變。
連接至右電源墊102A-P的第二晶片墊302A和連接至左電源墊102B-P的重分佈墊322A可以彼此連接以共用電源路徑。為此,可以在重分佈墊322A和第二晶片墊302A之間形成附加重分佈線324P。
此外,連接至右接地墊102A-G的第二晶片墊302B和連接至左接地墊102B-G的重分佈墊322B可以彼此連接以共用接地路徑。為此,可以在重分佈墊322B和第二晶片墊302B之間形成附加重分佈線324G。
基於本實施方式,除了上述實施方式的優點之外,還能夠獲得以下優點。
首先,可以省略重分佈墊322A與左電源墊102B-P之間的接合佈線以及第二晶片墊302A與右電源墊102A-P之間的接合佈線中的任何一個(參見圖10的標記X)。另選地,可以省略重分佈墊322B與左接地墊102B-G之間的接合佈線以及第二晶片墊302B與右接地墊102A-G之間的接合佈線中的任何一個(參見圖10的標記X)。這是因為重分佈墊322A和第二晶片墊302A可以捆綁在一起以共用電源路徑,或者重分佈墊322B和第二晶片墊302B可以捆綁在一起以共用接地路徑。因此,通過省略接合佈線,可以簡化製程並降低製程成本。
此外,當重分佈墊322A和322B以及第二晶片墊302A和302B捆綁在一起時,具體地,當它們如圖10的實施方式中那樣以近距離捆綁在一起時,能夠改善配電網路(PDN)的特性。也就是說,可以減小電源路徑或接地路徑的電感和電阻。將參照圖11描述具體的操作原理。
圖11是例示了當兩個互連中的一些互連以彼此接觸的方式共用路徑時的電感和電阻特性的圖。
參照圖11,當兩個信號的傳輸路徑在靠近起點的位置(即,墊)處捆綁在一起時(參見情況1),能夠理解,與傳輸路徑在遠離起點的位置處捆綁在一起的情況(參見情況2)或傳輸路徑沒有捆綁在一起的情況(參見情況3)相比,電感和電阻最低。
基於圖11,由於重分佈墊322A和322B以及第二晶片墊302A和302B通過附加重分佈線324P和324G在靠近位置處捆綁在一起,因此與它們沒有捆綁在的情況或者它們在遠離起點的位置處通過例如基板100中的互連等捆綁在一起的情況相比,能夠改善電源路徑或接地路徑的電感和電阻。也就是說,情況1的PDN特性優於情況2或情況3的PDN特性。
圖12示出了例示包括採用根據實施方式的半導體封裝件中的至少一個的記憶卡7800的電子系統的方塊圖。記憶卡7800包括諸如非揮發性記憶體裝置之類的記憶體7810和記憶體控制器7820。記憶體7810和記憶體控制器7820可以存儲資料或讀出所存儲的資料。記憶體7810和記憶體控制器7820中的至少一個可以包括根據所描述的實施方式的半導體封裝件中的至少一個。
記憶體7810可以包括應用了本公開的實施方式的技術的非揮發性記憶體裝置。記憶體控制器7820可以控制記憶體7810,使得回應於來自主機7830的讀取/寫入請求而讀出所存儲的資料或存儲資料。
圖13示出了例示包括根據所描述的實施方式的半導體封裝件中的至少一個的電子系統8710的方塊圖。電子系統8710可以包括控制器8711、輸入/輸出裝置8712和記憶體8713。控制器8711、輸入/輸出裝置8712和記憶體8713可以通過提供資料移動的路徑的匯流排8715彼此耦接。
在實施方式中,控制器8711可以包括一個或更多個微處理器、數位訊號處理器、微控制器和/或能夠執行與這些元件相同功能的邏輯器件。控制器8711或記憶體8713可以包括根據本公開的實施方式的一個或更多個半導體封裝件。輸入/輸出裝置8712可以包括從小鍵盤、鍵盤、顯示裝置、觸控式螢幕等當中選擇的至少一個。記憶體8713是用於存儲資料的裝置。記憶體8713可以存儲要由控制器8711執行的資料和/或命令等。
記憶體8713可以包括諸如DRAM之類的揮發性記憶體裝置和/或諸如快閃記憶體之類的非揮發性記憶體裝置。例如,快閃記憶體可以被安裝到諸如移動終端或桌上型電腦之類的資訊處理系統。快閃記憶體可以構成固態磁碟(SSD)。在這種情況下,電子系統8710可以在快閃記憶體系統中穩定地存儲大量資料。
電子系統8710可以進一步包括介面8714,該介面8714被配置為向通信網路發送資料和從通信網路接收資料。介面8714可以是有線類型或無線類型。例如,介面8714可以包括天線或有線或無線收發器。
電子系統8710可以被實現為執行各種功能的移動系統、個人電腦、工業電腦或邏輯系統。例如,移動系統可以是個人數位助理(PDA)、可攜式電腦、平板電腦、行動電話、智慧型手機、無線電話、膝上型電腦、記憶卡、數位音樂系統和資訊發送/接收系統中的任何一種。
如果電子系統8710表示能夠執行無線通訊的設備,則電子系統8710可以被用在使用分碼多重存取(CDMA)、全球移動通信系統(GSM)、北美數位行動電話(NADC)、強化分時多重存取(E-TDMA)、寬頻分碼多重存取(WCDMA)、CDMA2000、長期演進技術(LTE)或無線寬頻網際網路(Wibro)的技術的通信系統中。
儘管已經出於示例性目的描述了各種實施方式,但是對於本領域技術人員顯而易見的是,在不脫離如所附請求項限定的本發明的精神和範圍的情況下,可以進行各種改變和變型。
100:基板
100A:底表面
100B:頂表面
102:第一基板墊
102A:右第一基板墊
102A-G:接地墊/右接地墊
102A-P:電源墊/右電源墊
102B:左第一基板墊
102B-G:接地墊/左接地墊
102B-P:電源墊/左電源墊
104:基板墊/第二基板墊
106:開口
200:第一半導體晶片
200':第一半導體晶片
200A:底表面
200B:頂表面
202:第一晶片墊
202':晶片墊/第一晶片墊
300:第二半導體晶片
300':第二半導體晶片
300A:底表面
300B:頂表面
302:第二晶片墊
302':第二晶片墊
302-1:第二晶片墊
302-2:第二晶片墊
302A:第二晶片墊
302B:第二晶片墊
320:重分佈層
322:重分佈導電層/重分佈墊
322':重分佈墊
322-1:重分佈墊
322-2:重分佈墊
322A:重分佈墊
322B:重分佈墊
324:重分佈導電層/重分佈線
324':重分佈線
324-1:重分佈線
324-2:重分佈線
324G:附加重分佈線
324P:附加重分佈線
326:重分佈絕緣層/第一重分佈絕緣層
328:重分佈絕緣層/第二重分佈絕緣層
400:外部連接元件
500:互連件
610:第一黏合層
620:第二黏合層
700:囊封物
7800:記憶卡
7810:記憶體
7820:記憶體控制器
7830:主機
8710:電子系統
8711:控制器
8712:輸入/輸出裝置
8713:記憶體
8714:介面
8715:匯流排
A1:重疊區
A2:非重疊區
A-A':截取線
C1:中央區
C2:中央區
E1:邊緣區
E2:邊緣區
圖1是示意性地例示了根據一個實施方式的半導體封裝件的立體圖。
圖2是例示了圖1的半導體封裝件的基板的底表面的平面圖。
圖3是例示了圖1的半導體封裝件的第一半導體晶片的底表面的平面圖。
圖4A是例示了圖1的半導體封裝件的第二半導體晶片的底表面的平面圖,並且圖4B是沿著平面圖的線A-A'截取的截面圖。
圖5是例示了圖1的半導體封裝件的底表面的平面圖並且是主要例示了第一半導體晶片和第二半導體晶片之間的重疊以及基於該重疊的重分佈層的圖。
圖6是例示了圖1的半導體封裝件的底表面的平面圖並且是主要例示了第一半導體晶片和第二半導體晶片之間的重疊以及基於該重疊的與基板的連接的圖。
圖7是圖1的半導體封裝件在第二方向上的側視圖。
圖8是例示了根據另一實施方式的第一半導體晶片的底表面的平面圖。
圖9是例示了根據另一實施方式的第二半導體晶片的底表面的平面圖。
圖10是例示了根據另一實施方式的半導體封裝件的平面圖。
圖11是例示了當兩個互連中的一些互連彼此接觸的方式共用路徑時的電以感和電阻特性的圖。
圖12示出了例示採用包括根據一個實施方式的半導體封裝件的記憶卡的電子系統的方塊圖。
圖13示出了例示包括根據一個實施方式的半導體封裝件的另一電子系統的方塊圖。
100:基板
100A:底表面
100B:頂表面
106:開口
200:第一半導體晶片
200A:底表面
200B:頂表面
300:第二半導體晶片
300A:底表面
300B:頂表面
320:重分佈層
Claims (21)
- 一種半導體封裝件,所述半導體封裝件包括: 基板,所述基板包括開口; 第一半導體晶片,所述第一半導體晶片被設置在所述基板上,包括通過所述開口暴露的多個第一晶片墊; 第二半導體晶片,所述第二半導體晶片被設置在所述第一半導體晶片上以與所述第一半導體晶片部分地重疊,所述第二半導體晶片包括與所述開口對齊的多個第二晶片墊;以及 重分佈層,所述重分佈層形成在其上設置有所述第二半導體晶片的所述第二晶片墊的表面上, 其中,所述第二晶片墊中的一個或更多個與所述第一半導體晶片重疊並且被所述第一半導體晶片覆蓋,並且所述第二晶片墊的其餘墊通過所述開口暴露,並且 其中,所述重分佈層包括通過所述開口暴露的重分佈墊,並且包括被配置為將所述第二晶片墊中的所述一個或更多個連接至所述重分佈墊的重分佈線。
- 根據請求項1所述的半導體封裝件,其中,所述開口在第一方向上的寬度大於所述開口在與所述第一方向基本垂直的第二方向上的寬度,並且 所述第二半導體晶片被設置為在所述第一方向上與所述第一半導體晶片部分地重疊。
- 根據請求項1所述的半導體封裝件,其中,所述基板具有面對所述第一半導體晶片的第一表面以及與所述第一表面相對定位的第二表面,並且所述基板包括位於所述基板的所述第二表面上的第一基板墊。
- 根據請求項3所述的半導體封裝件,所述半導體封裝件還包括互連件,所述互連件被配置為通過所述開口將所述第一晶片墊、所述第二晶片墊中的所述其餘墊以及所述重分佈墊連接至所述第一基板墊。
- 根據請求項4所述的半導體封裝件,其中,所述第一基板墊包括設置在所述開口的一側上的一側第一基板墊以及設置在所述開口的另一側上的另一側第一基板墊, 其中,連接至所述第一晶片墊的所述互連件和連接至所述第二晶片墊的所述其餘墊的所述互連件連接至所述一側第一基板墊,並且 其中,連接至所述重分佈墊的所述互連件連接至所述另一側第一基板墊。
- 根據請求項1所述的半導體封裝件,其中,所述第二半導體晶片被設置為在第一方向上與所述第一半導體晶片部分地重疊, 所述第二晶片墊在所述第一方向上佈置成一列,並且 所述重分佈墊在所述第二晶片墊的列的一側上沿所述第一方向佈置成一列。
- 根據請求項6所述的半導體封裝件,其中,所述基板具有面對所述第一半導體晶片的第一表面和與所述第一表面相對定位的第二表面,並且所述基板包括位於所述基板的所述第二表面上並設置在所述開口的一側上的一側第一基板墊以及位於所述基板的所述第二表面上並設置在所述開口的另一側上的另一側第一基板墊,並且 所述半導體封裝件還包括: 互連件,所述互連件被配置為將所述重分佈墊連接至所述一側第一基板墊,並將所述第二晶片墊的所述其餘墊連接至所述另一側第一基板墊。
- 根據請求項1所述的半導體封裝件,其中,所述第二半導體晶片被設置為在第一方向上與所述第一半導體晶片部分地重疊, 所述第二晶片墊包括在所述第一方向上佈置成一列的第一列和在所述第一列的一側上沿所述第一方向佈置成一列的第二列,並且所述第一列和所述第二列中的至少一列具有其中未設置所述第二晶片墊的空間;並且 所述重分佈墊被設置在所述空間中。
- 根據請求項8所述的半導體封裝件,其中,所述基板具有面對所述第一半導體晶片的第一表面和與所述第一表面相對定位的第二表面,並且所述基板包括位於所述基板的所述第二表面上並設置在所述開口的一側上的一側第一基板墊以及位於所述基板的所述第二表面上並設置在所述開口的另一側上的另一側第一基板墊,並且 所述半導體封裝件還包括: 互連件,所述互連件配置為將所述第一列的所述第二晶片墊的所述其餘墊或第一列的所述重分佈墊連接至所述一側第一基板墊,並且將所述第二列的所述第二晶片墊的所述其餘墊或所述第二列的所述重分佈墊連接至所述另一側第一基板墊。
- 根據請求項1所述的半導體封裝件,其中,所述第二半導體晶片被設置為在第一方向上與所述第一半導體晶片部分地重疊, 所述第二晶片墊包括在所述第一方向上佈置成一列的第一列和在所述第一列的一側上沿所述第一方向佈置成一列的第二列,並且 所述重分佈墊被佈置在沿第二方向位於所述第一列和所述第二列之間的第三列中。
- 根據請求項10所述的半導體封裝件,其中,所述重分佈墊在所述第一方向上與所述第二晶片墊交替地佈置。
- 根據請求項1所述的半導體封裝件,其中,所述基板具有面對所述第一半導體晶片的第一表面和與所述第一表面相對的第二表面,並且包括位於所述基板的所述第二表面上的電源墊,並且 其中,所述重分佈層還包括附加重分佈線,所述附加重分佈線將需要連接至所述電源墊的所述第二晶片墊和所述重分佈墊連接。
- 根據請求項12所述的半導體封裝件,所述半導體封裝件還包括互連件,所述互連件被配置為將需要連接至所述電源墊的所述第二晶片墊和所述重分佈墊中的一個連接至所述電源墊。
- 根據請求項1所述的半導體封裝件,其中,所述基板具有面對所述第一半導體晶片的第一表面和與所述第一表面相對的第二表面,並且包括位於所述基板的所述第二表面上的接地墊,並且 其中,所述重分佈層還包括附加重分佈線,所述附加重分佈線將需要連接至所述接地墊的所述第二晶片墊和所述重分佈墊連接。
- 根據請求項14所述的半導體封裝件,所述半導體封裝件還包括互連件,所述互連件被配置為將需要連接至所述接地墊的所述第二晶片墊和所述重分佈墊中的一個連接至所述接地墊。
- 根據請求項1所述的半導體封裝件,其中,所述第一晶片墊位於所述第一半導體晶片的中央區中,並且 所述第二晶片墊位於所述第二半導體晶片的中央區中。
- 根據請求項1所述的半導體封裝件,其中,所述第一晶片墊的佈置與所述第二晶片墊的佈置基本相同。
- 根據請求項2所述的半導體封裝件,其中,所述第一半導體晶片的兩個側表面在所述第二方向上與所述第二半導體晶片的兩個側表面對齊。
- 根據請求項3所述的半導體封裝件,其中,所述基板還包括: 第二基板墊,所述第二基板墊位於所述基板的所述第二表面上並且能連接至外部連接元件。
- 根據請求項1所述的半導體封裝件,所述半導體封裝件還包括: 第一黏合層,所述第一黏合層位於所述第一半導體晶片和所述基板之間;以及 第二黏合層,所述第二黏合層位於所述重分佈層和所述第一半導體晶片之間。
- 根據請求項1所述的半導體封裝件,所述半導體封裝件還包括: 囊封物,所述囊封物被配置為在覆蓋所述基板、所述第一半導體晶片和所述第二半導體晶片的同時填充所述開口。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190081983A KR20210006115A (ko) | 2019-07-08 | 2019-07-08 | 적층 반도체 칩을 포함하는 반도체 패키지 |
KR10-2019-0081983 | 2019-07-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202103289A true TW202103289A (zh) | 2021-01-16 |
TWI833847B TWI833847B (zh) | 2024-03-01 |
Family
ID=
Also Published As
Publication number | Publication date |
---|---|
US11088117B2 (en) | 2021-08-10 |
US20210013180A1 (en) | 2021-01-14 |
CN112201641A (zh) | 2021-01-08 |
CN112201641B (zh) | 2024-04-23 |
KR20210006115A (ko) | 2021-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10971479B2 (en) | Semiconductor package including stacked semiconductor chips | |
US11380651B2 (en) | Semiconductor package including stacked semiconductor chips | |
KR102216195B1 (ko) | 복수 개의 칩을 적층한 반도체 패키지 | |
US11462511B2 (en) | Semiconductor package including stacked semiconductor chips | |
US11133288B2 (en) | Semiconductor package including stacked semiconductor chips | |
US10971452B2 (en) | Semiconductor package including electromagnetic interference shielding layer | |
US11715708B2 (en) | Semiconductor package including decoupling capacitor | |
US11233033B2 (en) | Semiconductor packages including chips stacked on a base module | |
US20230317683A1 (en) | Semiconductor package including heat dissipation layer | |
US11152335B2 (en) | Stack packages including a supporting substrate | |
US11004831B2 (en) | Stack packages including a fan-out sub-package | |
US10998294B2 (en) | Semiconductor packages having stacked chip structure | |
US11088117B2 (en) | Semiconductor package including stacked semiconductor chips | |
TWI833847B (zh) | 包含堆疊半導體晶片的半導體封裝件 | |
US11322475B2 (en) | Stack semiconductor packages having wire-bonding connection structure | |
TW202145495A (zh) | 包括電容器的半導體封裝件 | |
US11764128B2 (en) | Semiconductor chip including through electrode, and semiconductor package including the same | |
US11227858B2 (en) | Semiconductor package including stacked semiconductor chips | |
TWI842777B (zh) | 包含支撐基板的堆疊封裝件 | |
TW202310278A (zh) | 半導體封裝件 |