CN107039341A - 晶片的加工方法 - Google Patents

晶片的加工方法 Download PDF

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CN107039341A
CN107039341A CN201611079386.5A CN201611079386A CN107039341A CN 107039341 A CN107039341 A CN 107039341A CN 201611079386 A CN201611079386 A CN 201611079386A CN 107039341 A CN107039341 A CN 107039341A
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森数洋司
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Abstract

本发明的课题在于提供晶片的加工方法,其用于使器件更薄且小型化。一种晶片的加工方法,包含如下的工序:一体化工序,使支承基板与晶片的正面相对并借助结合材料而粘贴成一体;背面磨削工序,对晶片的背面进行磨削而使晶片变薄;切断工序,从晶片的背面沿着分割预定线将晶片按照每个器件进行切断;保护部件配设工序,在晶片的背面上配设保护部件;结合材料破坏工序,将对于支承基板具有透过性的波长的激光光线的聚光点定位于结合材料而进行照射从而将结合材料破坏;以及支承基板剥离工序,将支承基板从器件剥离而分离成每个器件。

Description

晶片的加工方法
技术领域
本发明涉及晶片的加工方法,将正面上形成有器件的薄板状的晶片分别分离成各个器件。
背景技术
关于IC、LSI、功率器件等多个器件由分割预定线划分并形成在正面上的晶片,通过激光加工装置等分割装置将分割预定线切断而分割成各个器件芯片,器件芯片被应用于移动电话、个人计算机、电视等电子设备中。并且,为了使应用了这样的器件芯片的移动电话或者具有通信功能的手表等更小型、轻量化,优选使该器件芯片的厚度变得更薄的技术。
作为使通过对晶片进行分割而得到的器件变薄的技术,已经提出了一种被称为先划片的技术(例如,参照专利文献1。)。
该技术是以如下方式进行的技术:先沿着分割预定线形成深度相当于器件芯片的完工厚度的槽,之后,在晶片的正面上配设保护部件而对晶片的背面进行磨削从而使该槽在背面露出而将晶片分割成各个器件芯片。
专利文献1:日本特开平11-040520号公报
上述专利文献1所记载的技术是以如下方式进行的技术:预先沿着形成有器件的正面侧的分割预定线形成比器件芯片的完成时的厚度深的槽,在该晶片的正面侧粘贴作为保护部件的片材,并使该晶片的正面侧作为下表面而将晶片保持在卡盘工作台上,将该晶片的背面磨削、研磨至器件芯片的完成时的厚度,并将晶片分离成各个器件芯片。
但是,在上述技术中,例如,当想要进行磨削加工以使各个器件芯片成为1mm见方以下或者厚度为10μm以下那样较小或较薄时,存在因磨削加工时传递到晶片的磨削磨轮的振动、按压载荷的变动导致器件芯片从作为保护部件的片材飞散或者器件芯片破损的问题,并存在如下问题:在活用上述先划片的技术而使各器件芯片小型化或者薄型化的方面存在极限。因此,在用于使器件芯片更薄并且小型化的晶片的加工方法中存在待解决的课题。
发明内容
本发明的目的在于提供一种晶片的加工方法,使器件更薄且小型化。
为了解决上述主要的技术课题,根据本发明,提供一种晶片的加工方法,将在正面的由多条分割预定线划分的区域内分别具有器件的晶片沿着分割预定线分割成各个器件,其中,该晶片的加工方法具有如下的工序:一体化工序,使支承基板与晶片的正面相对并借助结合材料而粘贴成一体;背面磨削工序,在实施了该一体化工序之后,对该晶片的背面进行磨削而使该晶片变薄;切断工序,从磨削后的该晶片的背面沿着分割预定线将晶片按照每个器件进行切断;保护部件配设工序,在沿着分割预定线被切断的该晶片的背面上配设保护部件;结合材料破坏工序,在实施了保护部件配设工序之后,将对于该支承基板具有透过性的波长的激光光线的聚光点定位于该结合材料而进行照射从而将该结合材料破坏;以及支承基板剥离工序,在实施了该结合材料破坏工序之后,将该支承基板从该器件剥离而分离成每个器件。
优选在该保护部件配设工序中,将晶片收纳在具有对晶片进行收纳的开口部的框架的该开口部中并且利用粘合带对晶片的背面与框架的外周进行粘贴而借助粘合带将晶片支承在框架上,从而在晶片的背面上配设保护部件。优选本发明的晶片的加工方法还具有如下的拾取工序:在该支承基板剥离工序之后,对粘合带进行扩张而使器件的间隔扩张并从粘合带拾取器件。
优选该切断工序包含由切削刀具进行的切断、由激光光线进行的切断、由等离子蚀刻进行的切断以及由湿蚀刻进行的切断中的任意方式。
根据本发明的晶片的加工方法,与利用以往的先划片的晶片的加工方法相比,不会产生磨削中的飞散或器件的破坏等,能够磨削得更薄,作为结果,能够更小、更薄地形成分割得到的各个器件芯片。
附图说明
图1的(a)、(b)是示出一体化工序的立体图。
图2是示出背面磨削工序的立体图。
图3的(a)~(c)是示出切断工序的说明图。
图4是示出保护部件配设工序的立体图。
图5的(a)、(b)是示出结合材料破坏工序的说明图。
图6是示出支承基板剥离工序的立体图。
图7是示出拾取工序的剖视图。
标号说明
2:半导体晶片;3:支承基板;4:磨削装置;41:卡盘工作台;42:磨削磨具;43:磨削单元;5:切削装置;51:卡盘工作台;52:切削单元;53:拍摄单元;6:激光光线照射单元;61:聚光器;7:剥离机构;71:吸附单元;72:支承单元;8:分离装置;81:框架保持部件;82:夹具;83:扩张滚筒;84:拾取夹头;21:分割预定线;22:器件。
具体实施方式
(一体化工序)
参照附图对依照本发明而实施的晶片的加工方法进行详细地说明。首先,如图1所示,通过从环氧树脂、聚酰亚胺树脂等公知的结合材料中选择的结合剂将支承基板3粘贴在半导体晶片2的形成有器件22的正面2a侧,形成粘合晶片W(一体化工序)。另外,半导体晶片2例如由厚度为200μm的硅晶片构成,在半导体晶片2的正面2a上呈格子状形成有多条分割预定线21。并且,在半导体晶片2的正面2a上,在由形成为格子状的多条分割预定线21划分出的多个区域内形成有IC、LSI等器件22。并且,该支承基板3例如是从玻璃、蓝宝石等中选择的,优选从透明性部件中选择。
(背面磨削工序)
在如上述那样通过结合材料将半导体晶片2和支承基板3一体化之后,如图2所示,实施对半导体晶片2的背面2b进行磨削的背面磨削工序。使用图2所示的磨削装置4来实施该背面磨削工序。图2所示的磨削装置4具有:卡盘工作台41,其对被加工物进行保持;以及磨削单元43,其具有用于对保持在该卡盘工作台41上的被加工物进行磨削的磨削磨具42。要想使用该磨削装置4来实施背面磨削工序,则将粘合晶片W的支承基板3侧载置在卡盘工作台41上,通过使未图示的吸引单元工作而将该粘合晶片W吸引固定在卡盘工作台41上。因此,保持在卡盘工作台41上的粘合晶片W以半导体晶片2的背面2b侧作为上侧而被固定。在这样将粘合晶片W固定在卡盘工作台41上之后,一边使卡盘工作台41按照箭头41a所示的方向以例如300rpm旋转,一边使磨削单元43的磨削磨具42按照箭头42a所示的方向以例如6000rpm旋转并使其与半导体晶片2的背面2b接触而进行磨削,残留出规定的残存厚度(例如,5~10μm)而执行磨削。
(切断工序)
在实施了对半导体晶片2的背面2b进行磨削的背面磨削工序之后,接着实施切断工序,从半导体晶片2的背面2b沿着分割预定线21将晶片切断成每个器件。
图3的(a)所示的切削装置5具有:卡盘工作台51,其对被加工物进行保持;切削单元52,其对保持在该卡盘工作台51上的被加工物进行切削;以及拍摄单元53,其对保持在该卡盘工作台51上的被加工物进行拍摄。卡盘工作台51构成为对被加工物进行吸引保持,并通过未图示的切削进给单元使卡盘工作台51按照图3的(a)中箭头X所示的切削进给方向移动。
上述切削单元52包含:主轴外壳521,其实际上水平配置;主轴522,其被该主轴外壳521支承为自由旋转;切削刀具523,其具有安装在该主轴522的前端部的环状的切削刃523a,主轴522通过配设在主轴外壳521内的未图示的伺服电动机而向箭头522a所示的方向旋转。上述拍摄单元53由显微镜、红外线照射单元和红外线CCD照相机等光学单元构成,该拍摄单元53将拍摄得到的图像信号发送给未图示的控制单元,该控制单元执行图案匹配等图像处理并完成切削区域的对准,其中,该图案匹配等图像处理用于进行形成于半导体晶片2的正面2a侧的分割预定线21与切削刀具523的对位。另外,当在晶片的背面形成有从正面起的贯通电极的情况下,也可以以该电极为基准来完成对准。
在如以上那样实施了对准之后,将保持了粘合晶片W的卡盘工作台51移动至切削加工区域的切削开始位置,使切削刀具523向下方切入进给,并且使切削刀具523以规定的旋转速度旋转,并使卡盘工作台51按照箭头X所示的方向以规定的切削进给速度移动而移动到X轴方向上的切削结束位置,从而从半导体晶片2的背面2b侧形成切削槽21a(切削槽形成工序),并使卡盘工作台51的移动停止。然后,使切削刀具523上升,并且在箭头Y所示的方向(分度进给方向)上对卡盘工作台51进行分度进给,接着将待切削的分割预定线21定位在与切削刀具523对应的位置而实施上述的切削槽形成工序(参照图3的(a))。并且,与形成在该半导体晶片2上的全部的分割预定线21对应地实施上述的切削槽形成工序(参照图3的(b))。另外,虽然在本实施方式中,该切削深度被设定为将半导体晶片2切断,但可以根据需要设定为将结合材料层B也同时切断。至此,切断工序结束。
(保护部件配设工序)
在实施了上述的对半导体晶片2的切断工序之后,实施保护部件配设工序,在该半导体晶片2的背面2b侧粘贴作为保护部件的粘合带T。即,如图4所示,将上述的半导体晶片2侧即令半导体晶片2的背面2b朝下而粘贴在作为保护部件的粘合带T的正面上,该粘合带T的外周部被安装成覆盖环状的框架F的内侧开口部,保护部件配设工序结束。因此,粘贴在粘合带T上的粘合晶片W的支承基板3侧成为上侧。
(结合材料破坏工序)
在上述保护部件配设工序结束之后,使用图5的(a)所示的具有激光光线照射单元6的激光加工装置来实施结合材料破坏工序。另外,该激光加工装置也能够使用公知的激光加工装置,由于不是构成本发明的主要部分,所以对整体构造和其详细的情况省略了说明。
要想实施图5所示的结合材料破坏工序,则将实施了上述保护部件配设工序的粘合晶片W的粘合带T侧载置在该激光加工装置所具有的卡盘工作台(省略了图示)上。并且,通过使未图示的吸引单元工作,将粘合晶片W隔着粘合带T吸引保持在卡盘工作台上(晶片保持工序)。另外,虽然在图5的(a)中省略了示出,但环状的框架F被配设在卡盘工作台上的合适的框架保持部件保持。
在如上述那样实施了晶片保持工序之后,将吸引保持了粘合晶片W的卡盘工作台移动至加工区域,如图5的(a)所示,将其定位在激光光线照射单元6的聚光器61的正下方。并且,如图5的(b)所示,通过来自未图示的控制单元的控制信号,使激光光线照射单元6工作而从粘合晶片W的支承基板3侧对将该支承基板3与半导体晶片2结合的结合材料B照射对于支承基板3(例如蓝宝石)具有透过性并且对于结合材料(例如环氧树脂)具有吸收性的波长的激光光线,进行将结合材料B破坏的激光光线的照射。此时,一边照射激光光线,一边使卡盘工作台按照箭头X所示的加工进给方向和箭头Y所示的分度进给方向移动,并进行控制以使从聚光器61照射的脉冲激光光线的光斑照射到该粘合晶片W的半导体晶片2与支承基板3的结合面整体。其结果是,在半导体晶片2与支承基板3之间将两者结合的结合材料在整个区域内被破坏,由结合材料B实现的半导体晶片2与支承基板3的结合功能丧失,结合材料破坏工序结束。
例如按照以下的方式对上述激光光线照射工序中的加工条件进行设定。
光源:YAG激光
波长:355nm
重复频率:50kHz
输出:0.2W
光斑直径:φ50μm
脉冲宽度:10ns
进给速度:2000mm/s
(支承基板剥离工序)
在实施了上述结合材料破坏工序之后,实施支承基板剥离工序,将支承基板3从半导体晶片2剥离而分离成每个器件22(参照图6)。首先,如果结合材料破坏工序结束,则将载置有该粘合晶片W的卡盘工作台移动至配设有剥离机构7的剥离位置,并将保持在该卡盘工作台上的粘合晶片W定位在被支承单元72支承的吸附单元71的正下方而使该吸附单元71下降。并且,使支承基板3与借助吸引通路711而被支承的吸引垫712a~712c接触。如果吸引垫712a~712c与支承基板3接触,则使未图示的吸引单元工作而经由该支承单元72和吸引通路711作用负压而通过该吸引垫712a~712c对支承基板3进行吸附。在利用该吸引垫712a~712c对该支承基板3进行吸附之后,如图6所示,使吸附了该支承基板3的吸引垫712a~712c向从粘合晶片W远离的方向即向上方移动而将支承基板3从半导体晶片2剥离,支承基板剥离工序结束。当该支承基板剥离工序结束时,将剥离后的支承基板3收纳在未图示的支承基板收纳容器中,而成为此前与支承基板3结合的多个器件22被分离成各个器件而被保持在载置于卡盘工作台上的粘合带T上的状态。
(拾取工序)
当上述支承基板剥离工序结束时,实施拾取工序,从粘合带T拾取该器件22。该拾取工序是利用拾取装置8而实施的,在图7中示出了该拾取装置8的一部分,该拾取装置8具有:框架保持部件81;夹具82,其将环状的框架F载置在框架保持部件81的上表面部而对该环状的框架F进行保持;以及扩张滚筒83,其由至少上方开口的圆筒形状构成,用于对与粘合带T一起保持在上表面上的各个器件22进行扩张,该粘合带T被安装在由该夹具82保持的环状的框架F上。框架保持部件81被支承单元823支承为能够升降,该支承单元823包含以围绕扩张滚筒83的方式设置的多个气缸823a和从气缸823a延伸的活塞杆823b。
该扩张滚筒83被设定为比环状的框架F的内径小并比半导体晶片2的外径大,其中,该半导体晶片2粘贴在粘合带T上,该粘合带T安装在环状的框架F上。这里,如图7所示,分离装置8能够位于框架保持部件81与扩张滚筒83的上表面部为大致同一的高度的位置(如虚线所示)和通过支承单元823的作用来使框架保持部件81下降而使扩张滚筒83的上端部比框架保持部件81的上端部高的位置(如实线所示)。
当使上述框架保持部件81下降而使扩张滚筒83的上端从虚线所示的位置相对变化为以实线所示的比框架保持部件81高的位置时,安装在环状的框架F上的粘合带T与扩张滚筒83的上端缘接触而被扩张。其结果是,由于张力呈放射状地作用于粘贴在粘合带T上的半导体晶片2,所以已经被分割的各个器件22彼此的间隔被扩大。并且,在各个器件22彼此的间隔被扩大的状态下,使拾取夹头84工作而对已经被分割的器件22进行吸附,将器件从粘合带T剥离而进行拾取,并搬送到未图示的收纳托盘中。通过以上动作,拾取工序结束,本发明的晶片的加工方法完成。另外,在本实施方式的切断工序中,不仅切断半导体晶片2还同时将结合材料B切断,但不一定仅限于此。当在切断工序中结合材料B没有被完全切断而有残存的情况下,在该拾取工序中当粘合带T被扩张时会完全地分离。
本发明通过具有上述那样的结构,在形成沿着分割预定线的切削槽之前在利用支承基板对晶片的正面侧进行支承的状态下对晶片的背面进行磨削,因此在磨削工序时各个器件不会飞散或被破坏,因此能够起到如下的特别的作用效果:能够容易地制造出例如大小为1mm见方以下或者厚度为10μm以下这样更小型化或者薄化的器件。
并且,在上述实施方式中,对作为实施切断工序的具体的方式使用切削刀具沿着分割预定线形成切削槽进行了说明,但并不仅限于此。作为形成切削槽的方式,也可以选择如下的任意切断方式:使用激光光线来进行切断、使用等离子蚀刻来进行切断以及使用湿蚀刻来进行切断等。
进而,在上述实施方式中,在保护部件配设工序中,将晶片收纳在具有对晶片进行收纳的开口部的框架的开口部中并且利用粘合带对晶片的背面和框架的外周进行粘贴,借助粘合带将晶片支承在框架上从而在晶片的背面上配设保护部件,但并不仅限于此。例如,也可以仅将作为形成有与晶片同一形状的保护部件的带粘贴在晶片的背面,或者通过将树脂等涂布在晶片的正面上而配设保护部件。
另外,在上述的实施方式中,对在背面磨削工序之后立即实施切断工序的情况进行了说明,但在形成于将要制造的晶片上的器件为功率器件的情况下,在该背面磨削工序与切断工序之间包含有在晶片的背面侧形成电极的工序。

Claims (3)

1.一种晶片的加工方法,将在正面的由多条分割预定线划分的区域内分别具有器件的晶片沿着分割预定线分割成各个器件,其中,该晶片的加工方法具有如下的工序:
一体化工序,使支承基板与晶片的正面相对并借助结合材料而粘贴成一体;
背面磨削工序,在实施了该一体化工序之后,对该晶片的背面进行磨削而使晶片变薄;
切断工序,从磨削后的该晶片的背面沿着分割预定线按照每个器件进行切断;
保护部件配设工序,在沿着分割预定线被切断的该晶片的背面上配设保护部件;
结合材料破坏工序,在实施了保护部件配设工序之后,将对于该支承基板具有透过性的波长的激光光线的聚光点定位于该结合材料而进行照射从而将该结合材料破坏;以及
支承基板剥离工序,在实施了该结合材料破坏工序之后,将该支承基板从该器件剥离而分离成每个器件。
2.根据权利要求1所述的晶片的加工方法,其中,
在该保护部件配设工序中,将晶片收纳在具有对晶片进行收纳的开口部的框架的该开口部中并且利用粘合带对晶片的背面与框架的外周进行粘贴而借助粘合带将晶片支承在框架上,从而在晶片的背面上配设保护部件,
该晶片的加工方法还具有如下的拾取工序:在该支承基板剥离工序之后,对粘合带进行扩张而使器件的间隔扩张并从粘合带拾取器件。
3.根据权利要求1或2所述的晶片的加工方法,其中,
该切断工序包含由切削刀具进行的切断、由激光光线进行的切断、由等离子蚀刻进行的切断以及由湿蚀刻进行的切断中的任意方式。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107733389A (zh) * 2017-11-01 2018-02-23 应达利电子股份有限公司 一种石英晶体大片及利用其制造小型晶片的方法
CN109746796A (zh) * 2019-01-10 2019-05-14 湘潭大学 一种用于SiC晶圆的划片装置及方法
CN110197794A (zh) * 2018-02-27 2019-09-03 株式会社迪思科 剥离方法
CN110571132A (zh) * 2018-06-06 2019-12-13 株式会社迪思科 晶片的加工方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6980421B2 (ja) * 2017-06-16 2021-12-15 株式会社ディスコ ウエーハの加工方法
TWI783395B (zh) * 2021-03-03 2022-11-11 華泰電子股份有限公司 晶圓薄化方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1973375A (zh) * 2004-03-29 2007-05-30 J.P.瑟塞尔联合公司 使用激光束分离材料层的方法
TW201009917A (en) * 2008-08-12 2010-03-01 Disco Corp Method of processing optical device wafer
JP2013237115A (ja) * 2012-05-14 2013-11-28 Ulvac Seimaku Kk ウェハ支持体およびその製造方法
US20140001487A1 (en) * 2011-03-14 2014-01-02 Fuji Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor device
TW201438085A (zh) * 2013-03-18 2014-10-01 Disco Corp 晶圓之加工方法(四)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140520A (ja) 1997-07-23 1999-02-12 Toshiba Corp ウェーハの分割方法及び半導体装置の製造方法
JP4285455B2 (ja) 2005-07-11 2009-06-24 パナソニック株式会社 半導体チップの製造方法
TWI267913B (en) * 2005-09-23 2006-12-01 Advanced Semiconductor Eng Wafer dicing method
JP2011187479A (ja) * 2010-03-04 2011-09-22 Disco Corp ウエーハの加工方法
JP2011216753A (ja) * 2010-04-01 2011-10-27 Panasonic Corp 半導体装置及びその製造方法
JP2011253939A (ja) * 2010-06-02 2011-12-15 Sony Chemical & Information Device Corp ウエハのダイシング方法、接続方法及び接続構造体
JP5580800B2 (ja) * 2010-10-29 2014-08-27 東京応化工業株式会社 積層体、およびその積層体の分離方法
US9029238B2 (en) 2012-10-11 2015-05-12 International Business Machines Corporation Advanced handler wafer bonding and debonding

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1973375A (zh) * 2004-03-29 2007-05-30 J.P.瑟塞尔联合公司 使用激光束分离材料层的方法
TW201009917A (en) * 2008-08-12 2010-03-01 Disco Corp Method of processing optical device wafer
US20140001487A1 (en) * 2011-03-14 2014-01-02 Fuji Electric Co., Ltd. Semiconductor device manufacturing method and semiconductor device
JP2013237115A (ja) * 2012-05-14 2013-11-28 Ulvac Seimaku Kk ウェハ支持体およびその製造方法
TW201438085A (zh) * 2013-03-18 2014-10-01 Disco Corp 晶圓之加工方法(四)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107733389A (zh) * 2017-11-01 2018-02-23 应达利电子股份有限公司 一种石英晶体大片及利用其制造小型晶片的方法
CN107733389B (zh) * 2017-11-01 2020-12-01 深圳市深汕特别合作区应达利电子科技有限公司 一种石英晶体大片及利用其制造小型晶片的方法
CN110197794A (zh) * 2018-02-27 2019-09-03 株式会社迪思科 剥离方法
CN110197794B (zh) * 2018-02-27 2024-02-20 株式会社迪思科 剥离方法
CN110571132A (zh) * 2018-06-06 2019-12-13 株式会社迪思科 晶片的加工方法
CN110571132B (zh) * 2018-06-06 2024-02-20 株式会社迪思科 晶片的加工方法
CN109746796A (zh) * 2019-01-10 2019-05-14 湘潭大学 一种用于SiC晶圆的划片装置及方法

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KR20170066251A (ko) 2017-06-14
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