CN106575632A - 用于制造衬底适配器的方法、衬底适配器及用于接触半导体元件的方法 - Google Patents

用于制造衬底适配器的方法、衬底适配器及用于接触半导体元件的方法 Download PDF

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CN106575632A
CN106575632A CN201580036553.5A CN201580036553A CN106575632A CN 106575632 A CN106575632 A CN 106575632A CN 201580036553 A CN201580036553 A CN 201580036553A CN 106575632 A CN106575632 A CN 106575632A
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hardware
carrier
contact material
structurized
contact
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CN106575632B (zh
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伊利萨·维赛勒
弗兰克·克鲁格
马丁·布雷夫斯
迈克尔·舍费尔
安德列亚斯·欣里希
安德烈亚斯·斯蒂芬·克莱恩
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Heraeus Deutschland GmbH and Co KG
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Heraeus Materials Technology GmbH and Co KG
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Abstract

本发明涉及一种用于制造特别用于接触半导体元件(32)的衬底适配器(27)的方法,该方法包括下列步骤:‑将接触材料(13)施加在载体(10)的侧面(12)上,‑结构化导电的金属元件,‑将结构化的金属元件(15)定位在载体(10)上,使得金属元件(15)的第一侧面(17)和载体(10)的设置有接触材料(13)的侧面(12)相对布置,‑将结构化的金属元件(15)与设置有接触材料(13)的载体(10)结合,‑将传送元件(22)施加在结构化的金属元件(15)的第二侧面(20)上,‑分割传送元件(22)和/或结构化的且与接触材料(13)接合的金属材料(15)以便进一步加工。

Description

用于制造衬底适配器的方法、衬底适配器及用于接触半导体 元件的方法
本发明涉及一种用于制造特别用于接触半导体元件的衬底适配器(Substratadapter)的方法。此外,本发明还涉及一种利用这种方法制成的衬底适配器以及一种用于接触半导体元件,特别是用于接触功率组件的方法,其中使用了这种衬底适配器。
功率电子模块的要求不断提高,所述要求例如涉及导电性和使用寿命,需要使用铜压焊引线用于功率半导体彼此之间或功率电子模块内其它接线的接触。现在,主要仅提供铝涂层或铝金属化作为芯片金属化,其中这会导致在接触过程中和后续使用中产生问题。例如,可能会由于这种类型的金属化(Metallisierung)而造成在运行中发生故障。
因此有不同的解决方案来提高系统的使用寿命,即例如使用所谓的柔性电路板。然而,这种类型的柔性电路板也有不足之处,因为它们不能用常规的引线焊接工艺来接触,从而使得不能再使用现存的生产能力。
本发明的目的是提供一种特别是在制成的半导体设备,特别是功率半导体设备的可靠性方面得以改进的解决方案。
根据本发明,此目的在用于制造特别用于接触半导体元件的衬底适配器的方法方面通过具有权利要求1或权利要求2的特征的方法得以解决,在衬底适配器方面通过权利要求19的主题得以解决,并且在借助根据本发明的衬底适配器来接触半导体元件,特别是用于接触功率组件的方法方面通过具有权利要求20或21的特征的方法得以解决。
根据本发明的用于制造衬底适配器的方法或根据本发明的借助根据本发明的衬底适配器来接触半导体元件,特别用于接触功率组件的方法的有利和适当的实施形式在从属权利要求中提出。
根据本发明的用于制造特别用于接触半导体元件的衬底适配器的方法,包括下列步骤:
-将接触材料施加在载体的侧面上,
-结构化导电的金属元件,
-将结构化的金属元件定位在载体上,使得金属元件的第一侧面与载体的设置有接触材料的侧面相对布置,
-将结构化的金属元件与设置有接触材料的载体结合,
-将传送元件施加在结构化的金属元件的第二侧面上,
-分割传送元件和/或结构化的且与接触材料接合的金属元件以便进一步加工。
在另一方面,根据本发明的用于制造特别用于接触半导体元件的衬底适配器的方法,包括下列步骤:
-将接触材料施加在载体的侧面上,
-结构化导电的金属元件,
-将结构化的金属元件定位在载体上,使得金属元件的第一侧面与载体的设置有接触材料的侧面相对布置,
-将结构化的金属元件与设置有接触材料的载体结合,
-分割结构化的且与接触材料接合的金属元件以便进一步加工。
因此,根据本发明的方法可以可选地包括此步骤,即将传送元件施加到所构造的金属元件的第二侧面上。
接触材料的施加也可以称为传送。此外,接触材料作为接触层被施加或被传送到载体的侧面上是可能的。
结构化导电的金属元件涉及将结构并入导电的金属元件中,其中该结构可以并入导电的金属元件的一个侧面上以及多个侧面上。优选地,导电的金属元件的结构化在将要获得的衬底适配器的形状或将要获得的接触介质的形状方面来实现。例如,相同类型的或一致的形状彼此保持一定的距离并入导电的金属元件中。
据此,设置有接触材料的载体和结构化的导电金属元件首先涉及两个彼此分离的待加工或可加工的元件,这两个元件随后彼此相对定位。结构化的金属元件在载体上的定位以这种方式实现,使得金属元件的第一侧面与载体的设置有接触材料的侧面相对地布置。换言之,金属元件的第一侧面和载体的设置有接触材料的侧面彼此相对,或接触材料与金属元件的第一侧面彼此相对。将结构化的金属元件优选适当地相对于载体定位后将结构化的金属元件与设置有接触材料的载体结合。换言之,载体与结构化的金属元件接合,其中接触材料在接合时或在接合后与结构化的金属元件在第一侧面上接触。
在构成第一中间元件,即与载体接合的结构化的金属元件之后,可以在其上优选未设置有接触材料的结构化的金属元件的第二侧面上施加传送元件。换言之,接触材料和载体位于结构化的金属元件的一侧面上。传送元件位于结构化的金属元件的另一侧面或相对的侧面上。
分割传送元件和/或结构化的且与接触材料接合的金属元件以便进一步加工涉及实现或提供各个衬底适配器。因此,衬底适配器可选地包括或不包括传送元件在理论上是可能的。
在这种情况下应注意,衬底适配器即可以理解为一个单独的衬底适配器,又可以理解为布置在载体上的大量适配器。因此,根据本发明的方法涉及用于制造衬底适配器的方法以及用于制造在载体上的多个适配器的布置的方法。
借助分割传送元件和/或结构化的且与接触材料接合的金属元件可以制造衬底适配器的形状或在载体上并排布置的衬底适配器的形状。例如,传送元件或通过分割传送元件制成的传送元件部分、结构化的且与接触材料接合的且可选择地被分割的金属元件构成衬底适配器或多个衬底适配器,其布置在优选不会被分割的载体上。另外,仅与接触材料接合的、被分割的且可选择地进行涂覆的金属元件构成衬底适配器或多个衬底适配器是可考虑的,其布置在优选不会被分割的载体上。载体利用位于其上的衬底适配器或利用位于其上的多个衬底适配器构成半成品,该半成品例如需要用于接触半导体元件。半成品或位于载体上的衬底适配器可以独立操作,并且可以在时间上或空间上分开的工序中来进一步加工或应用在用于接触半导体元件的方法中。
可选地,可以这样设置,即使用第一涂层系统对结构化的金属元件的第一侧面进行涂覆,并且/或者使用第二涂层系统对结构化的金属元件的第二侧面进行涂覆,其中优选在将结构化的金属元件定位在载体上之前涂覆结构化的金属元件的第一侧面和/或第二侧面。
因此,在下文中术语结构化的金属元件始终包括这一选项,即这种结构化的金属元件要么在一个侧面上要么在两个侧面上,或在第一侧面和/或第二侧面上进行涂覆。
在本发明的一个实施形式中,载体可以是片材(Folie),特别是具有可调节的粘结力的片材,其中该片材在框架中,特别是在膜框架中是张紧的。另外,片材连续地缠绕在线圈载体上是可能的。载体片材例如是一种UV片材。
粘结力,特别是片材或载体片材的可调节的粘结力在载体和接触材料之间可以小于接触材料和结构化的金属元件之间的粘结力。当结构化的金属元件从载体分离时,接触材料仍然粘附在结构化的且可选择地进行涂覆的金属元件上。换言之,载体和接触材料之间的粘附优选小于接触材料和结构化的且可选择地进行涂覆的金属元件之间的粘附,从而在结构化的且可选择地进行涂覆的金属元件从载体分离时,接触材料仍然粘附在结构化的且可选择地进行涂覆的金属元件上。
施加在载体的侧面上的接触材料可以例如是可烧结的材料或烧结材料。接触材料可以是烧结膏(Sinterpaste)和/或烧结箔,其中烧结材料和/或烧结膏和/或烧结箔例如可以含有银和/或银化合物。
在本发明的另一个实施形式中,接触材料可以是焊料和/或导电黏合剂(Leitkleber)。
将接触材料施加在载体的侧面上可以通过压印,特别是通过筛网压制和/或模板压制,和/或橡胶辊刷(Rakeln)和/或喷涂和/或喷射得以实施或实现。
优选地,将接触材料施加在载体的侧面上可以通过预先规定的结构来实施,其中该预先规定的结构特别与金属元件的结构,特别是与结构化的金属元件的结构精确配合。优选地,接触材料用这种类型的形状或用这种类型的结构施加到载体的侧面上,该形状或结构符合结构化的金属元件的金属元件的形状或结构,从而在结构化的金属元件与设置有接触材料的载体结合时,结构化的接触材料可以精确配合地施加或安装在金属元件的结构上。
金属元件可以是金属片材,特别是铜片材。
使用第一涂层系统和/或第二涂层系统对金属元件的第一侧面和/或第二侧面的可选择涂覆例如可以借助电镀来实施。例如,涂覆层或第一涂层系统和/或第二涂层系统例如可以以高炉材料电镀技术(Gestellgutgalvanik)施加到金属元件的第一侧面和/或第二侧面上。
优选地,第一涂层系统和第二涂层系统是不同的金属,特别是镍、银和/或金。
在本发明的另一个实施形式中可以这样设置,即将施加在载体上的接触材料,特别是施加的烧结膏和/或烧结箔和/或施加的焊料预先干燥。优选地,施加在载体上的接触材料的预先干燥优选在将结构化的且可选择涂覆的金属元件定位在载体上之前来实施。换言之,施加在载体上的接触材料在结构化的且可选择涂覆的金属元件与接触材料结合时已经预先干燥了。
结构化的且可选择涂覆的金属元件,特别是金属元件的第二侧面可以在金属元件与载体结合期间,特别是压制期间借助加热的冲头被加热到60℃至100℃,特别是70℃至90℃,特别为80℃的温度。
在压制期间,反向保持件(Gegenhalter)和/或反向冲头可以作用在其上没有施加接触材料的载体侧面上。
所描述的施加在或会施加在结构化且可选择涂覆的金属元件的第二侧面上的传送元件可以是传送片材,特别是具有粘合剂涂层的自粘合的片材,优选为PSA(压敏黏合剂)粘合剂涂层。优选地,传送元件是传送片材或传送元件具有传送片材。
在根据本发明的方法的范围内,与载体和/或与接触材料接合的、结构化的、可选择涂覆的且设置有传送元件的金属元件优选通过锯开和/或激光切割和/或冲压和/或蚀刻和/或水射流切割来分割是可能的。由于将传送元件和/或金属元件的分割,所以在载体上制造或提供了多个衬底适配器的布置。
例如,有可能仅分割传送元件。另外,还可以考虑将传送元件和与接触材料接合的金属元件分割。除此之外,也有可能仅分割与接触材料接合的金属元件。也还可以考虑分割载体的部分区域。优选地,通过分割在相邻的堆叠件(Stapel)之间产生自由空间,其中堆叠件由金属元件部分以及接触材料部分构成,且可选择地包括传送元件部分。各个堆叠件可以平行排列地固定或位于一个或共同的载体上。
在一个并列的方面,本发明涉及一种衬底适配器,其用方法或用根据本发明的方法制成。衬底适配器包括至少一个金属元件部分以及至少一个接触材料部分。另外,衬底适配器也包括至少一个传送元件部分是可能的。可选地,这些部分可以位于载体上。
在另一个并列的方面,本发明涉及一种在载体上的多个衬底适配器的布置,其中该多个衬底适配器的布置用根据本发明的方法制成。
本发明的另一个并列的方面涉及一种借助根据本发明的衬底适配器来接触半导体元件,特别是接触功率组件的方法。根据本发明的接触方法包括下列步骤:
-将分割的衬底适配器从载体分离,该衬底适配器包括具有接合的接触材料的可选择涂覆的金属元件以及传送元件,
-将衬底适配器定位在半导体元件上,使得接触材料和半导体元件相对放置或相对指向,
-通过施加热量和/或压力使衬底适配器附着在半导体元件上,
-移除传送元件并且暴露可选择涂覆的金属元件的第二侧面,
-将可选择涂覆的金属元件的第二侧面与接触元件,特别是与压焊引线,特别是铜压焊引线,和/或与焊料小板和/或与铜芯片接触。
本发明的另一个并列的方面涉及一种借助根据本发明的衬底适配器来接触半导体元件,特别是接触功率组件的方法。根据本发明的接触方法包括下列步骤:
-将分割的衬底适配器从载体分离,该衬底适配器包括具有接合的接触材料的可选择涂覆的金属元件,
-将衬底适配器定位在半导体元件上,使得接触材料和半导体元件相对指向,
-通过施加热量和/或压力使衬底适配器附着在半导体元件上,
-将可选择涂覆的金属元件的第二侧面与接触元件,特别是与压焊引线,特别是铜压焊引线,和/或与焊料小板和/或与铜芯片接触。
另外,根据本发明的接触方法包括此方法步骤,即将衬底适配器与半导体元件和/或与具有半导体元件的衬底烧结和/或焊接和/或粘贴。
借助根据本发明的用于制造衬底适配器的方法提供了一种衬底适配器,包括接触材料的该衬底适配器可以提供给客户和/或其它的加工线或生产线使用。可在膜片框架上提供衬底适配器或具有多个衬底适配器的布置。在这种类型的运输方式中可直接在下一个工艺步骤或方法步骤中将它从膜片框架中取出,并且烧结在半导体元件上,特别是烧结在功率组件上。这对应于所谓的拾取和放置技术(Pick and Place-Technologie)。这意味着,可借助机器人技术或抓取装置或喷嘴或抽吸设备将衬底适配器从载体或膜片框架移走并将其运输到对应的半导体元件处。
接下来将根据实施例并参照具有其它细节的附图进一步阐述本发明。
其中:
图1至图6示出了用于制造用于半导体功率模块的特殊的衬底适配器的方法的各个阶段和步骤,其中衬底适配器保护半导体功率模块免受机械应力,并且应借助于铜压焊引线实现焊接;
图7至图11通过各个阶段或步骤示出了用于制造衬底适配器的方法的另一个示例性的实施例;
图12-14示出了借助衬底适配器来接触半导体元件的根据本发明的方法的各个阶段或步骤;
图15示出了已接触的半导体元件;并且
图16至图21通过各个阶段或步骤示出了用于制造衬底适配器的方法的另一个示例性的实施例以及借助衬底适配器来接触半导体元件的方法。
以下对于相同的或相同作用的部件使用相同的参考标记。
在图1至图6中,用俯视图和截面图示出了各个方法步骤和半成品。
在图1中示出了载体10,其在所谓的膜片框架(Film-Frame)11上被张紧。示出的载体10涉及一种具有可调节的粘结力的片材。将片材10张紧到膜片框架11中时应注意片材或载体10具有足够的机械稳定性,从而可能在随后的干燥过程中不会使位于其上的元件或位于其上的接触材料13变形。
根据图2,将接触材料13施加在载体10的侧面12上。接触材料13在示出的实施例中是烧结膏。优选地,该烧结膏含有银和/或银化合物。将接触材料13构造在载体10的侧面12上或利用结构14施加在载体10的侧面12上。换言之,分四个单一部分来施加接触材料13,其中每个部分具有粗略的L形状。将接触材料13施加在载体10的侧面12上优选地通过压印,特别是通过筛网压制和/或模板印制来实现。随后,将压印在载体10的侧面12上的接触材料13,即烧结膏预先干燥。将优选使用的银烧结膏例如在约100℃下干燥10分钟。
图3示出了金属元件15的第一侧面的俯视图。优选地,金属元件15是一种金属片材,特别是一种铜片材。将导电的金属元件15结构化。该结构化例如可以通过蚀刻和/或冲压和/或激光来实现。换言之,将一个结构或多个结构16引入导电的金属元件15中。优选地,结构16或形状符合接触元件13的结构14。优选地,金属元件15的结构16符合后来将要使用的衬底适配器的形状。
将接触材料13施加在载体10的侧面12上利用预先规定的结构14来实现,其中该结构14实施为与金属元件15的结构16精确相配。因此,如同L形状或如同接触材料13的各个结构14一样,导电的金属元件15的结构16也实施为L形状,其具有彼此相等的间距。
在图4中示出了用于制造衬底适配器的根据本发明的方法的另一个步骤。这涉及将结构化的金属元件15定位在载体10上,其中该定位以如下方式进行,即金属元件15的第一侧面17与载体10设置有接触材料13的侧面12相对地布置。因此,导电的、结构化的金属元件15精确相配地放置在涂覆了烧结膏的载体片材上。为了使载体10或载体片材不翘曲,反向保持件19作用在载体10的不具有接触材料13的底侧面或第二侧面18上。
如在图5中识别出的,接下来是将结构化的金属元件15与设置有接触材料13的载体10结合。在结合期间或在压紧期间,金属元件15,特别是金属元件15的第二侧面20借助加热的冲头21被加热到60℃至100℃,特别是70℃至90℃,特别是80℃的温度。通过施加热量和/或压力将金属元件15与载体10或与位于载体10上的接触材料13压紧。在压紧期间,反向保持件19也作用在载体10的第二侧面18上。
在结构化的金属元件15与设置有接触材料13的载体10压紧或结合之后,在结构化的金属元件15的第二侧面20上施加传送元件22。优选地,传送元件22是传送片材。特别地,传送片材可以是具有粘合剂涂层的自粘合的片材。优选地,偏向于PSA(压敏黏合剂)粘合剂涂层。
如已经描述的那样,载体10也可以是片材或载体片材。特别地,载体10是具有可调节的粘合力的片材。优选地,片材或载体片材10的粘合力以这种方式设置,使得载体10或载体10的第一侧面12和接触材料13之间的粘合力小于接触材料13和结构化的金属元件15或结构化的金属元件15的第一侧面17之间的粘合力。这样设置粘合力会使在结构化的金属元件15以及位于其上的接触材料13从载体10分离时接触材料13仍粘附在结构化的金属元件15上成为可能。换言之,当结构化的金属元件15分离时,位于金属元件15上的接触材料13也一起分离,因为接触材料13由于较小的粘合力可从载体10或从载体10的第一侧面12分离,
在图6中示出了分割传送元件22以及结构化的且与接触材料13接合的金属元件15以便进一步加工。因此优选地,与载体10和/或与接触材料13接合的、结构化的、可选择涂覆且设置有传送元件22的金属元件15可以通过锯开和/或激光切割和/或冲压和/或蚀刻和/或水射流切割被分割。由于随后例如沿接触材料13的结构14以及沿金属元件15的结构16分割,可以实现或制成各个衬底适配器。优选地,分割时不分离或仅部分分离载体10。因此,被分割的衬底适配器仍然能粘附在载体10上。换言之,分割优选仅涉及传送元件22以及与接触材料13接合的金属元件15。因此,被分割的衬底适配器可以借助膜片框架11和载体10以简单的方式和方法进行运输。
接下来的图7至图11涉及用于制造衬底适配器的根据本发明的方法的另一个实施形式。
在图7中示出了金属元件15,即首先结构化的铜片材。为此,在金属元件15的第一侧面17上引入凹口23。由于引入的凹口23以及在总厚度d上将金属元件15分离的分离点24,在金属元件15的第一侧面17上产生结构16。
根据图8,对金属元件15的第一侧面17和金属元件15的第二侧面20进行涂覆,其中在第一侧面17上应用第一涂层系统25,并且在第二侧面20上应用第二涂层系统26,因此,可选择地涂覆结构化的金属元件15优选在金属元件15结构化之后进行。优选地,金属元件15的第一侧面17以及第二侧面20的涂覆借助电镀来实施。
优选地,第一涂层系统25和第二涂层系统26是不同的金属,优选是镍、银和/或金。
在图9中示出了具有施加在其上的接触材料13的载体10。接触材料13例如为含银的或含银合金的烧结膏。接触材料13具有结构14,其中结构14与金属元件15的结构16相同。被涂覆的金属元件15被定位在载体10上,特别被定位在接触材料13上。优选地,具有位于其上的第一涂层系统25的金属元件15的第一侧面17布置在接触材料13之上。接着将结构化的金属元件15与接触材料13结合。这种结合例如可以借助压紧来实现,如其关于图5所描述的那样。
根据图10可以施加传送元件22。传送元件22例如是传送片材,其中该传送片材被施加在金属元件15的第二侧面20上,特别是被施加在第二涂层系统26上。优选地,传送元件22完全覆盖被涂覆的结构化的金属元件15。
在图11中再次示出了将传送元件22以及结构化的、被涂覆的且与接触材料13接合的金属元件15分割。如已经描述的,该分割可以通过锯开和/或激光切割和/或冲压和/或蚀刻和/或水射流切割来实现。由于分割产生各个堆叠件27,其各自由传送元件部分28、被涂覆的金属元件部分29以及接触材料部分30组成。在当前的实施例中,示出的载体10未分离。此外显而易见的是,例如中间的堆叠件27由两个并排布置的堆叠件构成,然而这两个并排布置的堆叠件仅通过传送元件部分28相连。各个堆叠件27表示将要施加在半导体元件上的衬底适配器。各个堆叠件27或衬底适配器可以用载体10进行运输。
在图12中示出了可以在后期的服务流程(Kundenprozess)中借助拾取和放置技术用夹爪或抽吸装置或喷嘴31将中间的堆叠件27或衬底适配器从载体10分割。堆叠件或衬底适配器27被定位在半导体元件32上,其中接触材料13与半导体元件32相对放置(见图13)。通过施加热量和/或压力使衬底适配器或堆叠件27附着在半导体元件32上得以实现。
在随后的步骤中(见图14),将传送元件22或传送元件部分28去除并且暴露金属元件15的第二侧面20或第二涂层系统26。
如在图15中示出的,可选择涂覆的金属元件15的第二侧面20可以与接触元件,即与铜压焊引线33接触。接下来进行烧结和/或通常的构造工序或连接工序以制造所接触的半导体元件32或功率组件。
在下面描述的图16至图21涉及根据本发明的用于制造衬底适配器的方法的另一种实施形式以及借助衬底适配器来接触半导体元件的方法。
在图16中示出了金属元件15,即首先结构化的铜片材。为此,在金属元件15的第一侧面17上引入凹口23。由于引入的凹口23以及在总厚度d上将金属元件15分离的分离点24,在金属元件15的第一侧面17上产生结构16。
根据图17,对金属元件15的第一侧面17和金属元件15的第二侧面20进行涂覆,其中在第一侧面17上应用第一涂层系统25,并且在第二侧面20上应用第二涂层系统26。因此,可选择地涂覆结构化的金属元件15优选在金属元件15结构化之后进行。优选地,金属元件15的第一侧面17和第二侧面20的涂覆借助电镀来实施。
优选地,第一涂层系统25和第二涂层系统26是不同的金属,优选是镍、银和/或金。
在图18中示出了具有施加在其上的接触材料13的载体10。接触材料13例如是含银的或含银合金的烧结膏。接触材料13具有结构14,其中结构14与金属元件15的结构16相同。被涂覆的金属元件15被定位在载体10上,特别被定位在接触材料13上。优选地,金属元件15的具有位于第一侧面上的第一涂层系统25的第一侧面17布置在接触材料13之上。随后将结构化的金属元件15与接触材料13结合。这种结合例如可以借助压紧来实现,如其关于图5描述的那样。
在图19中再次示出了将结构化的、被涂覆的且与接触材料13接合的金属元件15分割。分割可以通过锯开和/或激光切割和/或冲压和/或蚀刻和/或水射流切割来实现。由于分割产生各个堆叠件或衬底适配器27’,其各自由经过涂覆的金属元件部分29以及接触材料部分30组成。在本实施例中,示出的载体10未分离。各个堆叠件27’表示将要施加在半导体元件上的衬底适配器。各个堆叠件27’或衬底适配器可以用例如可被张紧在膜片框架中的载体10进行运输。
在图20中示出了可以在后期的服务流程中借助拾取和放置技术用夹爪或抽吸装置或喷嘴31将中间的堆叠件27’或衬底适配器与载体10分割。在本实施例中,堆叠件或衬底适配器27’是被定位在半导体元件32上的发射极(Emitter),其中接触材料13与半导体元件32相对放置(见图21)。通过施加热量和/或压力使衬底适配器或堆叠件27’附着在半导体元件32上得以实现。另外位于载体10上且表示栅极(Gate)的堆叠件或衬底适配器27’可以单独涂覆在半导体元件32上。如图21所示,这可以利用其它的附加的抽吸装置或喷嘴31’来实现。在图13示出的方法步骤中,可实现在一个步骤中将发射极和栅极定位,因为这两个堆叠件27通过传送元件部分28彼此相连。
优选地,金属元件15的第二侧面20或第二涂层系统26可以在随后且未示出的方法步骤中例如与铜压焊引线接触。接下来进行烧结和/或通常的构造工序或连接工序以制造所接触的半导体元件32或功率组件。
在此指出,所有以上根据图1至图21的实施形式所描述的方法步骤以及元件单独看或任意组合,特别是在附图中示出的细节,将作为本发明主要要求保护的部分。
附图标记表
10 载体
11 膜片框架
12 载体的第一侧面
13 接触材料
14 接触材料的结构
15 金属元件
16 金属元件的结构
17 金属元件的第一侧面
18 载体的第二侧面
19 反向保持件
20 金属元件的第二侧面
21 冲头
22 传送元件
23 凹口
24 分离点
25 第一涂层系统
26 第二涂层系统
27、27’ 堆叠件、衬底适配器
28 传送元件部分
29 金属元件部分
30 接触材料部分
31、31’ 喷嘴
32 半导体元件
33 铜压焊引线
d 金属元件的厚度

Claims (22)

1.一种用于制造衬底适配器(27)的方法,所述衬底适配器特别用于接触半导体元件(32),所述方法包括下列步骤:
-将接触材料(13)施加在载体(10)的侧面(12)上,
-将导电的金属元件(15)结构化,
-将结构化的金属元件(15)定位在所述载体(10)上,使得所述金属元件(15)的第一侧面(17)与所述载体(10)的设置有所述接触材料(13)的所述侧面(12)相对地布置,
-将结构化的金属元件(15)与设置有接触材料(13)的所述载体(10)结合,
-将传送元件(22)施加在结构化的金属元件(15)的第二侧面(20)上,
-分割所述传送元件(22)和/或结构化的且与接触材料(13)结合在一起的所述金属元件(15)以便进一步加工。
2.一种用于制造衬底适配器(27’)的方法,所述衬底适配器特别用于接触半导体元件(32),所述方法包括下列步骤:
-将接触材料(13)施加在载体(10)的侧面(12)上,
-将导电的金属元件(15)结构化,
-将结构化的金属元件(15)定位在所述载体(10)上,使得所述金属元件(15)的第一侧面(17)与所述载体(10)的设置有所述接触材料(13)的所述侧面(12)相对地布置,
-将结构化的金属元件(15)与设置有接触材料(13)的所述载体(10)结合,
-将结构化的、与接触材料(13)结合在一起的所述金属元件(15)分割以便进一步加工。
3.根据权利要求1或2所述的方法,其特征在于,应用第一涂层系统(25)涂覆结构化的金属元件(15)的所述第一侧面(17),并且/或者应用第二涂层系统(26)涂覆结构化的金属元件(15)的第二侧面(20),特别是在将结构化的金属元件(15)定位在所述载体(10)上之前进行涂覆。
4.根据权利要求1至3中任一项所述的方法,其特征在于,所述载体(10)是片材,特别是具有可调节的粘结力的片材,所述片材被张紧在框架中,特别是膜片框架(11)中,或连续地缠绕在线圈载体上。
5.根据权利要求4所述的方法,其特征在于,所述载体(10)和所述接触材料(13)之间的粘合力小于所述接触材料(13)和结构化的金属元件(15)之间的粘合力,从而使得在将结构化的金属元件(15)从所述载体(10)分离时,所述接触材料(13)仍粘附在结构化的金属元件(15)上。
6.根据权利要求1至5中任一项所述的方法,其特征在于,所述接触材料(13)是烧结材料。
7.根据权利要求6所述的方法,其特征在于,所述接触材料(13)是烧结膏和/或烧结片材,并且优选含有银和/或银化合物。
8.根据前述权利要求中任一项所述的方法,其特征在于,所述接触材料(13)是焊料和/或传导黏合剂。
9.根据前述权利要求中任一项所述的方法,其特征在于,将所述接触材料(13)施加在所述载体(10)的侧面(12)上通过压印,特别是通过筛网压制和/或模板压制,和/或橡胶辊刷和/或喷涂和/或喷射得以实施。
10.根据前述权利要求中任一项所述的方法,其特征在于,将所述接触材料(13)施加在所述载体(10)的侧面(12)上利用预先规定的结构(14)来实施,所述预先规定的结构(14)与所述金属元件(15)的结构(16),特别地与结构化的金属元件的结构(16)精确配合。
11.根据前述权利要求中任一项所述的方法,其特征在于,所述金属元件(15)是金属片材,特别是铜片材。
12.根据权利要求3至11中任一项所述的方法,其特征在于,所述金属元件(15)的所述第一侧面(17)和/或所述第二侧面(20)的涂覆借助电镀来实施。
13.根据权利要求3至12中任一项所述的方法,其特征在于,所述第一涂层系统(25)和所述第二涂层系统(26)是不同的金属,优选是镍、银和/或金。
14.根据前述权利要求中任一项所述的方法,特别是根据权利要求6至13中任一项所述的方法,其特征在于,将施加在所述载体(10)上的所述接触材料(13),特别是所施加的烧结膏和/或烧结片材和/或所施加的焊料预先干燥。
15.根据前述权利要求中任一项所述的方法,其特征在于,在所述金属元件(15)与所述载体(10)结合期间,特别是在所述金属元件(15)与所述载体(10)压紧期间,所述金属元件(15),特别是所述金属元件(15)的所述第二侧面(20)借助加热的冲头(21)被加热到60℃至100℃,特别是70℃至90℃,特别是80℃的温度。
16.根据权利要求15所述的方法,其特征在于,在压紧期间,反向保持件(19)和/或反向冲头作用在所述载体(10)的优选不具有接触材料(13)的侧面(18)上。
17.根据前述权利要求中任一项所述的方法,特别是根据权利要求1或3至16中任一项所述的方法,其特征在于,所述传送元件(22)是传送片材,特别是具有粘合剂涂层的自粘合的片材,所述粘合剂涂层优选为PSA(压敏黏合剂)粘合剂涂层。
18.根据前述权利要求中任一项所述的方法,其特征在于,与所述载体(10)和/或与所述接触材料(13)结合在一起的、结构化的、可选择涂覆的,且可选择地设置有所述传送元件(22)的所述金属元件(15)特别通过锯开和/或激光切割和/或冲压和/或蚀刻和/或水射流切割来分割。
19.一种衬底适配器(27、27’),其通过根据前述权利要求中任一项所述的方法制成。
20.一种借助根据权利要求19所述的衬底适配器(27)来接触半导体元件(32),特别是接触功率组件的方法,包括下列步骤:
-将分割的衬底适配器(27)从载体(10)分离,所述衬底适配器包括具有结合在一起的接触材料(13)的可选择涂覆的金属元件(15)以及传送元件(22),
-将所述衬底适配器(27)定位在所述半导体元件(32)上,使得所述接触材料(13)和所述半导体元件(32)相对指向,
-通过施加热量和/或压力使所述衬底适配器(27)附着在所述半导体元件(32)上,
-移除所述传送元件(22)并且暴露可选择涂覆的金属元件(15)的第二侧面(20),
-使所述可选择涂覆的金属元件(15)的所述第二侧面(20)与接触元件,特别是与压焊引线,特别是铜压焊引线(33),和/或与焊料小板和/或与铜芯片接触。
21.一种借助根据权利要求19所述的衬底适配器(27’)来接触半导体元件(32),特别是接触功率组件的方法,包括下列步骤:
-将分割的衬底适配器(27’)从载体(10)分离,所述衬底适配器包括具有结合在一起的接触材料(13)的可选择涂覆的金属元件(15),
-将所述衬底适配器(27’)定位在所述半导体元件(32)上,使得所述接触材料(13)和所述半导体元件(32)相对指向,
-通过施加热量和/或压力使所述衬底适配器(27’)附着在所述半导体元件(32)上,
-使可选择涂覆的金属元件(15)的所述第二侧面(20)与接触元件,特别是与压焊引线,特别与铜压焊引线(33),和/或与焊料小板和/或与铜芯片接触。
22.根据权利要求20或21所述的方法,其特征在于,将所述衬底适配器(27、27’)与所述半导体元件(32)和/或与具有所述半导体元件(32)的衬底进行烧结和/或焊接和/或粘附。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111201598A (zh) * 2017-09-12 2020-05-26 罗杰斯德国有限公司 用于将诸如激光二极管的器件连接到冷却体上的适配器元件,由激光二极管、冷却体和适配器元件构成的系统和制造适配器元件的方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015113421B4 (de) 2015-08-14 2019-02-21 Danfoss Silicon Power Gmbh Verfahren zum Herstellen von Halbleiterchips
EP3154079A1 (de) * 2015-10-08 2017-04-12 Heraeus Deutschland GmbH & Co. KG Verfahren zum verbinden einer substratanordnung mit einem elektronikbauteil mit verwendung eines auf eine kontaktierungsmaterialschicht aufgebrachten vorfixiermittels, entsprechende substratanordnung und verfahren zu ihrem herstellen

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996961B2 (ja) * 2007-03-30 2012-08-08 ニッタ株式会社 チップ型電子部品の外部電極形成方法
EP2498283A2 (de) * 2011-03-10 2012-09-12 SEMIKRON Elektronik GmbH & Co. KG Verfahren zur Herstellung eines Leistungshalbleitersubstrates
CN103827353A (zh) * 2011-09-30 2014-05-28 罗伯特·博世有限公司 由承载膜和包括由至少一种金属粉末制成的可烧结的层和焊接层的层组件组成的复合层

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005136184A (ja) * 2003-10-30 2005-05-26 Seiko Epson Corp 基板接合体の製造方法及び製造装置、基板接合体、電気光学装置
DE102005047566C5 (de) * 2005-10-05 2011-06-09 Semikron Elektronik Gmbh & Co. Kg Anordnung mit einem Leistungshalbleiterbauelement und mit einem Gehäuse sowie Herstellungsverfahren hierzu
JP4156637B2 (ja) * 2006-07-31 2008-09-24 シャープ株式会社 半導体装置、電子回路の製造方法および電子回路の製造装置
DE102009018541A1 (de) * 2009-04-24 2010-10-28 W.C. Heraeus Gmbh Kontaktierungsmittel und Verfahren zur Kontaktierung elektrischer Bauteile
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
DE102011115886B4 (de) * 2011-10-15 2020-06-18 Danfoss Silicon Power Gmbh Verfahren zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten
DE102013104572A1 (de) * 2013-05-03 2014-11-06 Osram Opto Semiconductors Gmbh Verfahren zum Ausbilden einer optoelektronischen Baugruppe und optoelektronische Baugruppe

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996961B2 (ja) * 2007-03-30 2012-08-08 ニッタ株式会社 チップ型電子部品の外部電極形成方法
EP2498283A2 (de) * 2011-03-10 2012-09-12 SEMIKRON Elektronik GmbH & Co. KG Verfahren zur Herstellung eines Leistungshalbleitersubstrates
CN103827353A (zh) * 2011-09-30 2014-05-28 罗伯特·博世有限公司 由承载膜和包括由至少一种金属粉末制成的可烧结的层和焊接层的层组件组成的复合层

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111201598A (zh) * 2017-09-12 2020-05-26 罗杰斯德国有限公司 用于将诸如激光二极管的器件连接到冷却体上的适配器元件,由激光二极管、冷却体和适配器元件构成的系统和制造适配器元件的方法
CN111201598B (zh) * 2017-09-12 2024-03-26 罗杰斯德国有限公司 多个适配器元件的复合件和用于制造复合件的方法

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